OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr35767-5.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* Test that we generate aligned load when memory is aligned.  */
2
/* { dg-do compile } */
3
/* { dg-options "-O -msse2 -mtune=generic" } */
4
/* { dg-require-effective-target sse2 } */
5
/* { dg-final { scan-assembler-not "movups" } } */
6
/* { dg-final { scan-assembler "movaps" } } */
7
 
8
typedef float v4sf __attribute__ ((__vector_size__ (16)));
9
 
10
extern void foo(v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf, v4sf);
11
 
12
int test(void)
13
{
14
  v4sf x = { 0.0, 1.0, 2.0, 3.0 };
15
 
16
  foo (x, x, x, x, x, x, x, x, x);
17
  return 0;
18
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.