OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [pr39315-3.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* PR middle-end/39315  */
2
/* { dg-do compile } */
3
/* { dg-options "-O -msse2 -mtune=generic" } */
4
/* { dg-require-effective-target sse2 } */
5
/* { dg-final { scan-assembler-not "movups" } } */
6
/* { dg-final { scan-assembler-not "movlps" } } */
7
/* { dg-final { scan-assembler-not "movhps" } } */
8
/* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-128,\[\\t \]*%\[re\]?sp" } } */
9
/* { dg-final { scan-assembler "movaps" } } */
10
 
11
typedef float __m128 __attribute__ ((__vector_size__ (16)));
12
 
13
extern void bar (__m128 *);
14
 
15
void
16
foo (__m128 *x)
17
{
18
  __m128 b  __attribute__ ((aligned(128))) = *x;
19
  bar (&b);
20
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.