OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [sse4_1-pmaxuw.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do run } */
2
/* { dg-require-effective-target sse4 } */
3
/* { dg-options "-O2 -msse4.1" } */
4
 
5
#ifndef CHECK_H
6
#define CHECK_H "sse4_1-check.h"
7
#endif
8
 
9
#ifndef TEST
10
#define TEST sse4_1_test
11
#endif
12
 
13
#include CHECK_H
14
 
15
#include <smmintrin.h>
16
 
17
#define NUM 64
18
 
19
static void
20
TEST (void)
21
{
22
  union
23
    {
24
      __m128i x[NUM / 8];
25
      unsigned short i[NUM];
26
    } dst, src1, src2;
27
  int i;
28
  unsigned short max;
29
 
30
  for (i = 0; i < NUM; i++)
31
    {
32
      src1.i[i] = i * i;
33
      src2.i[i] = i + 20;
34
      if ((i % 8))
35
        src2.i[i] |= 0x8000;
36
    }
37
 
38
  for (i = 0; i < NUM; i += 8)
39
    dst.x[i / 8] = _mm_max_epu16 (src1.x[i / 8], src2.x[i / 8]);
40
 
41
  for (i = 0; i < NUM; i++)
42
    {
43
      max = src1.i[i] <= src2.i[i] ? src2.i[i] : src1.i[i];
44
      if (max != dst.i[i])
45
        abort ();
46
    }
47
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.