OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [ssetype-3.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* { dg-do compile } */
2
/* This test checks for absolute memory operands.  */
3
/* { dg-require-effective-target nonpic } */
4
/* { dg-require-effective-target sse2 } */
5
/* { dg-options "-O2 -msse2 -march=k8" } */
6
/* { dg-final { scan-assembler "andps\[^\\n\]*magic" } } */
7
/* { dg-final { scan-assembler "andnps\[^\\n\]*magic" } } */
8
/* { dg-final { scan-assembler "xorps\[^\\n\]*magic" } } */
9
/* { dg-final { scan-assembler "orps\[^\\n\]*magic" } } */
10
/* { dg-final { scan-assembler-not "movdqa" } } */
11
/* { dg-final { scan-assembler "movaps\[^\\n\]*magic" } } */
12
 
13
/* Verify that we generate proper instruction with memory operand.  */
14
 
15
#include <xmmintrin.h>
16
 
17
static __m128 magic_a, magic_b;
18
__m128
19
t1(void)
20
{
21
return _mm_and_ps (magic_a,magic_b);
22
}
23
__m128
24
t2(void)
25
{
26
return _mm_andnot_ps (magic_a,magic_b);
27
}
28
__m128
29
t3(void)
30
{
31
return _mm_or_ps (magic_a,magic_b);
32
}
33
__m128
34
t4(void)
35
{
36
return _mm_xor_ps (magic_a,magic_b);
37
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.