URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [stackalign/] [pr39146.c] - Blame information for rev 318

Go to most recent revision | Details | Compare with Previous | View Log


/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
/* { dg-options "-O2 -mavx" } */
 
typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__));
 
 
__m256i
bar (__m256i x)
{
  return x;
}
 
/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]*-32,\[^\\n\]*sp" } } */

Line No.	Rev	Author	Line
1	318	jeremybenn	`/* { dg-do compile { target i?86-- x86_64-- } } */`
2			`/* { dg-options "-O2 -mavx" } */`
3
4			`typedef long long __m256i __attribute__ ((__vector_size__ (32), __may_alias__));`
5
6
7			`__m256i`
8			`bar (__m256i x)`
9			`{`
10			`return x;`
11			`}`
12
13			`/* { dg-final { scan-assembler-not "and\[lq\]?\[^\\n\]-32,\[^\\n\]sp" } } */`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [stackalign/] [pr39146.c] - Blame information for rev 318