OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [i386/] [xop-shift2-vector.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 318 jeremybenn
/* Test that the compiler properly optimizes vector shift instructions into
2
   psha/pshl on XOP systems.  */
3
 
4
/* { dg-do compile } */
5
/* { dg-require-effective-target lp64 } */
6
/* { dg-options "-O2 -mxop -ftree-vectorize" } */
7
 
8
extern void exit (int);
9
 
10
typedef long __m128i  __attribute__ ((__vector_size__ (16), __may_alias__));
11
 
12
#define SIZE 10240
13
 
14
union {
15
  __m128i i_align;
16
  int i32[SIZE];
17
  unsigned u32[SIZE];
18
} a, b, c;
19
 
20
void
21
right_sign_shift32 (void)
22
{
23
  int i;
24
 
25
  for (i = 0; i < SIZE; i++)
26
    a.i32[i] = b.i32[i] >> c.i32[i];
27
}
28
 
29
int main ()
30
{
31
  right_sign_shfit32 ();
32
  exit (0);
33
}
34
 
35
/* { dg-final { scan-assembler "vpshad" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.