OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [branch-1.c] - Blame information for rev 321

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* Octeon targets should use "bbit" instructions for these "if" statements,
2
   but we test for "bbit" elsewhere.  On other targets, we should implement
3
   the "if" statements using an "andi" instruction followed by a branch
4
   on zero.  */
5
/* { dg-options "-O2 forbid_cpu=octeon" } */
6
 
7
void bar (void);
8
NOMIPS16 void f1 (int x) { if (x & 4) bar (); }
9
NOMIPS16 void f2 (int x) { if ((x >> 2) & 1) bar (); }
10
NOMIPS16 void f3 (unsigned int x) { if (x & 0x10) bar (); }
11
NOMIPS16 void f4 (unsigned int x) { if ((x >> 4) & 1) bar (); }
12
/* { dg-final { scan-assembler "\tandi\t.*\tandi\t.*\tandi\t.*\tandi\t" } } */
13
/* { dg-final { scan-assembler-not "\tsrl\t" } } */
14
/* { dg-final { scan-assembler-not "\tsra\t" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.