URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [ext-2.c] - Blame information for rev 338

Details | Compare with Previous | View Log


/* Turn the truncate,zero_extend,lshiftrt sequence before the or into a
   zero_extract.  The truncate is due to TARGET_PROMOTE_PROTOTYPES, the
   zero_extend to PROMOTE_MODE.  */
/* { dg-do compile } */
/* { dg-options "-O isa_rev>=2 -mgp64" } */
/* { dg-final { scan-assembler "\tdext\t" } } */
/* { dg-final { scan-assembler-not "and" } } */
/* { dg-final { scan-assembler-not "srl" } } */
 
void
f (unsigned char x, unsigned char *r)
{
  *r = 0x50 | (x >> 4);
}

Line No.	Rev	Author	Line
1	321	jeremybenn	`/* Turn the truncate,zero_extend,lshiftrt sequence before the or into a`
2			`zero_extract. The truncate is due to TARGET_PROMOTE_PROTOTYPES, the`
3			`zero_extend to PROMOTE_MODE. */`
4			`/* { dg-do compile } */`
5			`/* { dg-options "-O isa_rev>=2 -mgp64" } */`
6			`/* { dg-final { scan-assembler "\tdext\t" } } */`
7			`/* { dg-final { scan-assembler-not "and" } } */`
8			`/* { dg-final { scan-assembler-not "srl" } } */`
9
10			`void`
11			`f (unsigned char x, unsigned char *r)`
12			`{`
13			`*r = 0x50 \| (x >> 4);`
14			`}`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [ext-2.c] - Blame information for rev 338