OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [mips/] [ext-8.c] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 321 jeremybenn
/* Also make sure we don't use ext for MIPS*r1.  */
2
/* { dg-do compile } */
3
/* { dg-options "-O isa_rev<=1" } */
4
/* { dg-final { scan-assembler "\tand\t" } } */
5
/* { dg-final { scan-assembler-not "\td?ext\t" } } */
6
 
7
unsigned
8
f (unsigned i)
9
{
10
  return i & 0x7fffff;
11
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.