OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-25.c] - Blame information for rev 322

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 322 jeremybenn
/* { dg-do compile { target powerpc*-*-* } } */
2
/* { dg-require-effective-target powerpc_altivec_ok } */
3
/* { dg-options "-maltivec -O2 -Wall" } */
4
 
5
 
6
#define vector __attribute__((__vector_size__(16) ))
7
vector int f()
8
{
9
  int t = 4;
10
  return (vector int){t,t,t,t};
11
}
12
vector int f1()
13
{
14
  return (vector int){4,4,4,4};
15
}
16
 
17
/* We should be able to materialize the constant vector without
18
   any lvewx instructions as it is constant. */
19
/* { dg-final { scan-assembler-not "lvewx" } } */
20
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.