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[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-splat.c] - Blame information for rev 338

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Line No. Rev Author Line
1 322 jeremybenn 
/* { dg-do compile { target powerpc*-*-* } } */
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/* { dg-require-effective-target powerpc_altivec_ok } */
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/* { dg-options "-maltivec -mabi=altivec -O2" } */
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/* Testcase by Richard Guenther and Steven Bosscher.
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   Check that "easy" AltiVec constants are correctly synthesized
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   if they need to be reloaded.  */
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typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
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typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
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typedef __attribute__ ((vector_size (16))) unsigned int v4si;
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#define REGLIST                                                         \
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  "77",  "78",  "79",  "80",  "81",  "82",  "83",  "84",  "85",  "86",  \
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  "87",  "88",  "89",  "90",  "91",  "92",  "93",  "94",  "95",  "96",  \
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  "97",  "98",  "99", "100", "101", "102", "103", "104", "105", "106",  \
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 "107", "108"
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#define TEST(a, result, b)                              \
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  void a##_##b (int h)                                  \
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  {                                                     \
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    volatile a tmp;                                     \
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    while (h-- > 0)                                      \
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      {                                                 \
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        asm ("" : : : REGLIST);                         \
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        tmp = (a) (result) __builtin_altivec_##b (5);   \
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      }                                                 \
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  }                                                     \
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                                                        \
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  void a##_##b##_neg (int h)                            \
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  {                                                     \
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    volatile a tmp;                                     \
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    while (h-- > 0)                                      \
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      {                                                 \
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        asm ("" : : : REGLIST);                         \
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        tmp = (a) (result) __builtin_altivec_##b (-5);  \
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      }                                                 \
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  }
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TEST(v16qi, v16qi, vspltisb)
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TEST(v16qi, v8hi, vspltish)
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TEST(v16qi, v4si, vspltisw)
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TEST(v8hi, v16qi, vspltisb)
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TEST(v8hi, v8hi, vspltish)
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TEST(v8hi, v4si, vspltisw)
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TEST(v4si, v16qi, vspltisb)
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TEST(v4si, v8hi, vspltish)
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TEST(v4si, v4si, vspltisw)

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