URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc1/] [gcc/] [testsuite/] [gcc.target/] [sparc/] [20001102-1.c] - Blame information for rev 326

Line No.	Rev	Author	Line
1	326	jeremybenn	`/* { dg-do run } */`
2			`/* { dg-require-effective-target ultrasparc_hw } */`
3			`/* { dg-options "-O2 -mcpu=ultrasparc -mvis" } */`
4
5			`extern void abort (void);`
6			`extern void exit (int);`
7
8			`int foo(double a, int b, int c, double *d, int h)`
9			`{`
10			`int f, g;`
11			`double e;`
12
13			`l:`
14			`f = (int) a;`
15			`a -= (double) f;`
16			`if (b == 1)`
17			`{`
18			`g = c;`
19			`f += g;`
20			`c -= g;`
21			`}`
22			`if (b == 2)`
23			`{`
24			`f++;`
25			`h = c;`
26			`goto l;`
27			`}`
28
29			`asm volatile ("" : : :`
30			`"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",`
31			`"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",`
32			`"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",`
33			`"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31");`
34
35			`return f & 7;`
36			`}`
37
38			`int main()`
39			`{`
40			`if (foo(0.1, 1, 3, 0, 1) != 3)`
41			`abort ();`
42			`exit (0);`
43			`}`