Subversion Repositories openrisc_2011-10-31

;; Frv Machine Description

;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005, 2007, 2008

;; Free Software Foundation, Inc.

;; Contributed by Red Hat, Inc.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify

;; it under the terms of the GNU General Public License as published by

;; the Free Software Foundation; either version 3, or (at your option)

;; any later version.

;; GCC is distributed in the hope that it will be useful,

;; but WITHOUT ANY WARRANTY; without even the implied warranty of

;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING3.  If not see

;; .

;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.

;; ::::::::::::::::::::

;; ::

;; :: Unspec's used

;; ::

;; ::::::::::::::::::::

;; GOT constants must go 12/HI/LO for the splitter to work

(define_constants

  [(UNSPEC_BLOCKAGE             0)

   (UNSPEC_CC_TO_GPR            1)

   (UNSPEC_GPR_TO_CC            2)

   (UNSPEC_PIC_PROLOGUE         3)

   (UNSPEC_CR_LOGIC             4)

   (UNSPEC_STACK_ADJUST         5)

   (UNSPEC_EH_RETURN_EPILOGUE   6)

   (UNSPEC_GOT                  7)

   (UNSPEC_LDD                  8)

   (UNSPEC_OPTIONAL_MEMBAR      9)

   (UNSPEC_GETTLSOFF                    200)

   (UNSPEC_TLS_LOAD_GOTTLSOFF12         201)

   (UNSPEC_TLS_INDIRECT_CALL            202)

   (UNSPEC_TLS_TLSDESC_LDD              203)

   (UNSPEC_TLS_TLSDESC_LDD_AUX          204)

   (UNSPEC_TLS_TLSOFF_LD                205)

   (UNSPEC_TLS_LDDI                     206)

   (UNSPEC_TLSOFF_HILO                  207)

   (R_FRV_GOT12                 11)

   (R_FRV_GOTHI                 12)

   (R_FRV_GOTLO                 13)

   (R_FRV_FUNCDESC              14)

   (R_FRV_FUNCDESC_GOT12        15)

   (R_FRV_FUNCDESC_GOTHI        16)

   (R_FRV_FUNCDESC_GOTLO        17)

   (R_FRV_FUNCDESC_VALUE        18)

   (R_FRV_FUNCDESC_GOTOFF12     19)

   (R_FRV_FUNCDESC_GOTOFFHI     20)

   (R_FRV_FUNCDESC_GOTOFFLO     21)

   (R_FRV_GOTOFF12              22)

   (R_FRV_GOTOFFHI              23)

   (R_FRV_GOTOFFLO              24)

   (R_FRV_GPREL12               25)

   (R_FRV_GPRELHI               26)

   (R_FRV_GPRELLO               27)

   (R_FRV_GOTTLSOFF_HI          28)

   (R_FRV_GOTTLSOFF_LO          29)

   (R_FRV_TLSMOFFHI             30)

   (R_FRV_TLSMOFFLO             31)

   (R_FRV_TLSMOFF12             32)

   (R_FRV_TLSDESCHI             33)

   (R_FRV_TLSDESCLO             34)

   (R_FRV_GOTTLSDESCHI          35)

   (R_FRV_GOTTLSDESCLO          36)

   (GR8_REG                     8)

   (GR9_REG                     9)

   (GR14_REG                    14)

   ;; LR_REG conflicts with definition in frv.h

   (LRREG                       169)

   (FDPIC_REG                   15)

   ])

(define_mode_iterator IMODE [QI HI SI DI])

(define_mode_attr IMODEsuffix [(QI "b") (HI "h") (SI "") (DI "d")])

(define_mode_attr BREADsuffix [(QI "ub") (HI "uh") (SI "") (DI "d")])

;; ::::::::::::::::::::

;; ::

;; :: Constraints

;; ::

;; ::::::::::::::::::::

;; Standard Constraints

;;

;; `m' A memory operand is allowed, with any kind of address that the

;;     machine supports in general.

;;

;; `o' A memory operand is allowed, but only if the address is

;;     "offsettable".  This means that adding a small integer (actually, the

;;     width in bytes of the operand, as determined by its machine mode) may be

;;     added to the address and the result is also a valid memory address.

;;

;; `V' A memory operand that is not offsettable.  In other words,

;;     anything that would fit the `m' constraint but not the `o' constraint.

;;

;; `<' A memory operand with autodecrement addressing (either

;;     predecrement or postdecrement) is allowed.

;;

;; `>' A memory operand with autoincrement addressing (either

;;     preincrement or postincrement) is allowed.

;;

;; `r' A register operand is allowed provided that it is in a general

;;     register.

;;

;; `d', `a', `f', ...

;;     Other letters can be defined in machine-dependent fashion to stand for

;;     particular classes of registers.  `d', `a' and `f' are defined on the

;;     68000/68020 to stand for data, address and floating point registers.

;;

;; `i' An immediate integer operand (one with constant value) is allowed.

;;     This includes symbolic constants whose values will be known only at

;;     assembly time.

;;

;; `n' An immediate integer operand with a known numeric value is allowed.

;;     Many systems cannot support assembly-time constants for operands less

;;     than a word wide.  Constraints for these operands should use `n' rather

;;     than `i'.

;;

;; 'I' First machine-dependent integer constant (6-bit signed ints).

;; 'J' Second machine-dependent integer constant (10-bit signed ints).

;; 'K' Third machine-dependent integer constant (-2048).

;; 'L' Fourth machine-dependent integer constant (16-bit signed ints).

;; 'M' Fifth machine-dependent integer constant (16-bit unsigned ints).

;; 'N' Sixth machine-dependent integer constant (-2047..-1).

;; 'O' Seventh machine-dependent integer constant (zero).

;; 'P' Eighth machine-dependent integer constant (1..2047).

;;

;;     Other letters in the range `I' through `P' may be defined in a

;;     machine-dependent fashion to permit immediate integer operands with

;;     explicit integer values in specified ranges.  For example, on the 68000,

;;     `I' is defined to stand for the range of values 1 to 8.  This is the

;;     range permitted as a shift count in the shift instructions.

;;

;; `E' An immediate floating operand (expression code `const_double') is

;;     allowed, but only if the target floating point format is the same as

;;     that of the host machine (on which the compiler is running).

;;

;; `F' An immediate floating operand (expression code `const_double') is

;;     allowed.

;;

;; 'G' First machine-dependent const_double.

;; 'H' Second machine-dependent const_double.

;;

;; `s' An immediate integer operand whose value is not an explicit

;;     integer is allowed.

;;

;;     This might appear strange; if an insn allows a constant operand with a

;;     value not known at compile time, it certainly must allow any known

;;     value.  So why use `s' instead of `i'?  Sometimes it allows better code

;;     to be generated.

;;

;;     For example, on the 68000 in a fullword instruction it is possible to

;;     use an immediate operand; but if the immediate value is between -128 and

;;     127, better code results from loading the value into a register and

;;     using the register.  This is because the load into the register can be

;;     done with a `moveq' instruction.  We arrange for this to happen by

;;     defining the letter `K' to mean "any integer outside the range -128 to

;;     127", and then specifying `Ks' in the operand constraints.

;;

;; `g' Any register, memory or immediate integer operand is allowed,

;;     except for registers that are not general registers.

;;

;; `X' Any operand whatsoever is allowed, even if it does not satisfy

;;     `general_operand'.  This is normally used in the constraint of a

;;     `match_scratch' when certain alternatives will not actually require a

;;     scratch register.

;;

;; `0' Match operand 0.

;; `1' Match operand 1.

;; `2' Match operand 2.

;; `3' Match operand 3.

;; `4' Match operand 4.

;; `5' Match operand 5.

;; `6' Match operand 6.

;; `7' Match operand 7.

;; `8' Match operand 8.

;; `9' Match operand 9.

;;

;;     An operand that matches the specified operand number is allowed.  If a

;;     digit is used together with letters within the same alternative, the

;;     digit should come last.

;;

;;     This is called a "matching constraint" and what it really means is that

;;     the assembler has only a single operand that fills two roles considered

;;     separate in the RTL insn.  For example, an add insn has two input

;;     operands and one output operand in the RTL, but on most CISC machines an

;;     add instruction really has only two operands, one of them an

;;     input-output operand:

;;

;;          addl #35,r12

;;

;;     Matching constraints are used in these circumstances.  More precisely,

;;     the two operands that match must include one input-only operand and one

;;     output-only operand.  Moreover, the digit must be a smaller number than

;;     the number of the operand that uses it in the constraint.

;;

;;     For operands to match in a particular case usually means that they are

;;     identical-looking RTL expressions.  But in a few special cases specific

;;     kinds of dissimilarity are allowed.  For example, `*x' as an input

;;     operand will match `*x++' as an output operand.  For proper results in

;;     such cases, the output template should always use the output-operand's

;;     number when printing the operand.

;;

;; `p' An operand that is a valid memory address is allowed.  This is for

;;     "load address" and "push address" instructions.

;;

;;     `p' in the constraint must be accompanied by `address_operand' as the

;;     predicate in the `match_operand'.  This predicate interprets the mode

;;     specified in the `match_operand' as the mode of the memory reference for

;;     which the address would be valid.

;;

;; `Q` First non constant, non register machine-dependent insns

;; `R` Second non constant, non register machine-dependent insns

;; `S` Third non constant, non register machine-dependent insns

;; `T` Fourth non constant, non register machine-dependent insns

;; `U` Fifth non constant, non register machine-dependent insns

;;

;;     Letters in the range `Q' through `U' may be defined in a

;;     machine-dependent fashion to stand for arbitrary operand types.  The

;;     machine description macro `EXTRA_CONSTRAINT' is passed the operand as

;;     its first argument and the constraint letter as its second operand.

;;

;;     A typical use for this would be to distinguish certain types of memory

;;     references that affect other insn operands.

;;

;;     Do not define these constraint letters to accept register references

;;     (`reg'); the reload pass does not expect this and would not handle it

;;     properly.

;; Multiple Alternative Constraints

;; `?' Disparage slightly the alternative that the `?' appears in, as a

;;     choice when no alternative applies exactly.  The compiler regards this

;;     alternative as one unit more costly for each `?' that appears in it.

;;

;; `!' Disparage severely the alternative that the `!' appears in.  This

;;     alternative can still be used if it fits without reloading, but if

;;     reloading is needed, some other alternative will be used.

;; Constraint modifiers

;; `=' Means that this operand is write-only for this instruction: the

;;     previous value is discarded and replaced by output data.

;;

;; `+' Means that this operand is both read and written by the

;;     instruction.

;;

;;     When the compiler fixes up the operands to satisfy the constraints, it

;;     needs to know which operands are inputs to the instruction and which are

;;     outputs from it.  `=' identifies an output; `+' identifies an operand

;;     that is both input and output; all other operands are assumed to be

;;     input only.

;;

;; `&' Means (in a particular alternative) that this operand is written

;;     before the instruction is finished using the input operands.  Therefore,

;;     this operand may not lie in a register that is used as an input operand

;;     or as part of any memory address.

;;

;;     `&' applies only to the alternative in which it is written.  In

;;     constraints with multiple alternatives, sometimes one alternative

;;     requires `&' while others do not.

;;

;;     `&' does not obviate the need to write `='.

;;

;; `%' Declares the instruction to be commutative for this operand and the

;;     following operand.  This means that the compiler may interchange the two

;;     operands if that is the cheapest way to make all operands fit the

;;     constraints.  This is often used in patterns for addition instructions

;;     that really have only two operands: the result must go in one of the

;;     arguments.

;;

;; `#' Says that all following characters, up to the next comma, are to be

;;     ignored as a constraint.  They are significant only for choosing

;;     register preferences.

;;

;; `*' Says that the following character should be ignored when choosing

;;     register preferences.  `*' has no effect on the meaning of the

;;     constraint as a constraint, and no effect on reloading.

;; ::::::::::::::::::::

;; ::

;; :: Attributes

;; ::

;; ::::::::::::::::::::

;; The `define_attr' expression is used to define each attribute required by

;; the target machine.  It looks like:

;;

;; (define_attr NAME LIST-OF-VALUES DEFAULT)

;; NAME is a string specifying the name of the attribute being defined.

;; LIST-OF-VALUES is either a string that specifies a comma-separated list of

;; values that can be assigned to the attribute, or a null string to indicate

;; that the attribute takes numeric values.

;; DEFAULT is an attribute expression that gives the value of this attribute

;; for insns that match patterns whose definition does not include an explicit

;; value for this attribute.

;; For each defined attribute, a number of definitions are written to the

;; `insn-attr.h' file.  For cases where an explicit set of values is specified

;; for an attribute, the following are defined:

;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.

;;

;; * An enumeral class is defined for `attr_NAME' with elements of the

;;   form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first

;;   converted to upper case.

;;

;; * A function `get_attr_NAME' is defined that is passed an insn and

;;   returns the attribute value for that insn.

;; For example, if the following is present in the `md' file:

;;

;; (define_attr "type" "branch,fp,load,store,arith" ...)

;;

;; the following lines will be written to the file `insn-attr.h'.

;;

;; #define HAVE_ATTR_type

;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};

;; extern enum attr_type get_attr_type ();

;; If the attribute takes numeric values, no `enum' type will be defined and

;; the function to obtain the attribute's value will return `int'.

(define_attr "length" "" (const_int 4))

;; Processor type -- this attribute must exactly match the processor_type

;; enumeration in frv-protos.h.

(define_attr "cpu" "generic,fr550,fr500,fr450,fr405,fr400,fr300,simple,tomcat"

  (const (symbol_ref "frv_cpu_type")))

;; Attribute is "yes" for branches and jumps that span too great a distance

;; to be implemented in the most natural way.  Such instructions will use

;; a call instruction in some way.

(define_attr "far_jump" "yes,no" (const_string "no"))

;; Instruction type

;; "unknown" must come last.

(define_attr "type"

  "int,sethi,setlo,mul,div,gload,gstore,fload,fstore,movfg,movgf,macc,scan,cut,branch,jump,jumpl,call,spr,trap,fnop,fsconv,fsadd,fscmp,fsmul,fsmadd,fsdiv,sqrt_single,fdconv,fdadd,fdcmp,fdmul,fdmadd,fddiv,sqrt_double,mnop,mlogic,maveh,msath,maddh,mqaddh,mpackh,munpackh,mdpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx,mcut,mclracc,mclracca,mdunpackh,mbhconve,mrdacc,mwtacc,maddacc,mdaddacc,mabsh,mdrot,mcpl,mdcut,mqsath,mqlimh,mqshift,mset,ccr,multi,load_or_call,unknown"

  (const_string "unknown"))

(define_attr "acc_group" "none,even,odd"

  (symbol_ref "frv_acc_group (insn)"))

;; Scheduling and Packing Overview

;; -------------------------------

;;

;; FR-V instructions are divided into five groups: integer, floating-point,

;; media, branch and control.  Each group is associated with a separate set

;; of processing units, the number and behavior of which depend on the target

;; target processor.  Integer units have names like I0 and I1, floating-point

;; units have names like F0 and F1, and so on.

;;

;; Each member of the FR-V family has its own restrictions on which

;; instructions can issue to which units.  For example, some processors

;; allow loads to issue to I0 or I1 while others only allow them to issue

;; to I0.  As well as these processor-specific restrictions, there is a

;; general rule that an instruction can only issue to unit X + 1 if an

;; instruction in the same packet issued to unit X.

;;

;; Sometimes the only way to honor these restrictions is by adding nops

;; to a packet.  For example, on the fr550, media instructions that access

;; ACC4-7 can only issue to M1 or M3.  It is therefore only possible to

;; execute these instructions by packing them with something that issues

;; to M0.  When no useful M0 instruction exists, an "mnop" can be used

;; instead.

;;

;; Having decided which instructions should issue to which units, the packet

;; should be ordered according to the following template:

;;

;;     I0 F0/M0 I1 F1/M1 .... B0 B1 ...

;;

;; Note that VLIW packets execute strictly in parallel.  Every instruction

;; in the packet will stall until all input operands are ready.  These

;; operands are then read simultaneously before any registers are modified.

;; This means that it's OK to have write-after-read hazards between

;; instructions in the same packet, even if the write is listed earlier

;; than the read.

;;

;; Three gcc passes are involved in generating VLIW packets:

;;

;;    (1) The scheduler.  This pass uses the standard scheduling code and

;;        behaves in much the same way as it would for a superscalar RISC

;;        architecture.

;;

;;    (2) frv_reorg.  This pass inserts nops into packets in order to meet

;;        the processor's issue requirements.  It also has code to optimize

;;        the type of padding used to align labels.

;;

;;    (3) frv_pack_insns.  The final packing phase, which puts the

;;        instructions into assembly language order according to the

;;        "I0 F0/M0 ..." template above.

;;

;; In the ideal case, these three passes will agree on which instructions

;; should be packed together, but this won't always happen.  In particular:

;;

;;    (a) (2) might not pack predicated instructions in the same way as (1).

;;        The scheduler tries to schedule predicated instructions for the

;;        worst case, assuming the predicate is true.  However, if we have

;;        something like a predicated load, it isn't always possible to

;;        fill the load delay with useful instructions.  (2) should then

;;        pack the user of the loaded value as aggressively as possible,

;;        in order to optimize the case when the predicate is false.

;;        See frv_pack_insn_p for more details.

;;

;;    (b) The final shorten_branches pass runs between (2) and (3).

;;        Since (2) inserts nops, it is possible that some branches

;;        that were thought to be in range during (2) turned out to

;;        out-of-range in (3).

;;

;; All three passes use DFAs to model issue restrictions.  The main

;; question that the DFAs are supposed to answer is simply: can these

;; instructions be packed together?  The DFAs are not responsible for

;; assigning instructions to execution units; that's the job of

;; frv_sort_insn_group, see below for details.

;;

;; To get the best results, the DFAs should try to allow packets to

;; be built in every possible order.  This gives the scheduler more

;; flexibility, removing the need for things like multipass lookahead.

;; It also means we can take more advantage of inter-packet dependencies.

;;

;; For example, suppose we're compiling for the fr400 and we have:

;;

;;      addi    gr4,#1,gr5

;;      ldi     @(gr6,gr0),gr4

;;

;; We can pack these instructions together by assigning the load to I0 and

;; the addition to I1.  However, because of the anti dependence between the

;; two instructions, the scheduler must schedule the addition first.

;; We should generally get better schedules if the DFA allows both

;; (ldi, addi) and (addi, ldi), leaving the final packing pass to

;; reorder the packet where appropriate.

;;

;; Almost all integer instructions can issue to any unit in the range I0

;; to Ix, where the value of "x" depends on the type of instruction and

;; on the target processor.  The rules for other instruction groups are

;; usually similar.

;;

;; When the restrictions are as regular as this, we can get the desired

;; behavior by claiming the DFA unit associated with the highest unused

;; execution unit.  For example, if an instruction can issue to I0 or I1,

;; the DFA first tries to take the DFA unit associated with I1, and will

;; only take I0's unit if I1 isn't free.  (Note that, as mentioned above,

;; the DFA does not assign instructions to units.  An instruction that

;; claims DFA unit I1 will not necessarily issue to I1 in the final packet.)

;;

;; There are some cases, such as the fr550 media restriction mentioned

;; above, where the rule is not as simple as "any unit between 0 and X".

;; Even so, allocating higher units first brings us close to the ideal.

;;

;; Having divided instructions into packets, passes (2) and (3) must

;; assign instructions to specific execution units.  They do this using

;; the following algorithm:

;;

;;    1. Partition the instructions into groups (integer, float/media, etc.)

;;

;;    2. For each group of instructions:

;;

;;       (a) Issue each instruction in the reset DFA state and use the

;;           DFA cpu_unit_query interface to find out which unit it picks

;;           first.

;;

;;       (b) Sort the instructions into ascending order of picked units.

;;           Instructions that pick I1 first come after those that pick

;;           I0 first, and so on.  Let S be the sorted sequence and S[i]

;;           be the ith element of it (counting from zero).

;;

;;       (c) If this is the control or branch group, goto (i)

;;

;;       (d) Find the largest L such that S[0]...S[L-1] can be issued

;;           consecutively from the reset state and such that the DFA

;;           claims unit X when S[X] is added.  Let D be the DFA state

;;           after instructions S[0]...S[L-1] have been issued.

;;

;;       (e) If L is the length of S, goto (i)

;;

;;       (f) Let U be the number of units belonging to this group and #S be

;;           the length of S.  Create a new sequence S' by concatenating

;;           S[L]...S[#S-1] and (U - #S) nops.

;;

;;       (g) For each permutation S'' of S', try issuing S'' from last to

;;           first, starting with state D.  See if the DFA claims unit

;;           X + L when each S''[X] is added.  If so, set S to the

;;           concatenation of S[0]...S[L-1] and S'', then goto (i).

;;

;;       (h) If (g) found no permutation, abort.

;;

;;       (i) S is now the sorted sequence for this group, meaning that S[X]

;;           issues to unit X.  Trim any unwanted nops from the end of S.

;;

;; The sequence calculated by (b) is trivially correct for control

;; instructions since they can't be packed.  It is also correct for branch

;; instructions due to their simple issue requirements.  For integer and

;; floating-point/media instructions, the sequence calculated by (b) is

;; often the correct answer; the rest of the algorithm is optimized for

;; the case in which it is correct.

;;

;; If there were no irregularities in the issue restrictions then step

;; (d) would not be needed.  It is mainly there to cope with the fr550

;; integer restrictions, where a store can issue to I1, but only if a store

;; also issues to I0.  (Note that if a packet has two stores, they will be

;; at the beginning of the sequence calculated by (b).)  It also copes

;; with fr400 M-2 instructions, which must issue to M0, and which cannot

;; be issued together with an mnop in M1.

;;

;; Step (g) is the main one for integer and float/media instructions.

;; The first permutation it tries is S' itself (because, as noted above,

;; the sequence calculated by (b) is often correct).  If S' doesn't work,

;; the implementation tries varying the beginning of the sequence first.

;; Thus the nops towards the end of the sequence will only move to lower

;; positions if absolutely necessary.

;;

;; The algorithm is theoretically exponential in the number of instructions

;; in a group, although it's only O(n log(n)) if the sequence calculated by

;; (b) is acceptable.  In practice, the algorithm completes quickly even

;; in the rare cases where (g) needs to try other permutations.

(define_automaton "integer, float_media, branch, control, idiv, div")

;; The main issue units.  Note that not all units are available on

;; all processors.

(define_query_cpu_unit "i0,i1,i2,i3" "integer")

(define_query_cpu_unit "f0,f1,f2,f3" "float_media")

(define_query_cpu_unit "b0,b1" "branch")

(define_query_cpu_unit "c" "control")

;; Division units.

(define_cpu_unit "idiv1,idiv2" "idiv")

(define_cpu_unit "div1,div2,root" "div")

;; Control instructions cannot be packed with others.

(define_reservation "control" "i0+i1+i2+i3+f0+f1+f2+f3+b0+b1")

;; Generic reservation for control insns

(define_insn_reservation "control" 1

  (eq_attr "type" "trap,spr,unknown,multi")

  "c + control")

;; Reservation for relaxable calls to gettlsoff.

(define_insn_reservation "load_or_call" 3

  (eq_attr "type" "load_or_call")

  "c + control")

;; ::::::::::::::::::::

;; ::

;; :: Generic/FR500 scheduler description

;; ::

;; ::::::::::::::::::::

;; Integer insns

;; Synthetic units used to describe issue restrictions.

(define_automaton "fr500_integer")

(define_cpu_unit "fr500_load0,fr500_load1,fr500_store0" "fr500_integer")

(exclusion_set "fr500_load0,fr500_load1" "fr500_store0")

(define_bypass 0 "fr500_i1_sethi" "fr500_i1_setlo")

(define_insn_reservation "fr500_i1_sethi" 1

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "sethi"))

  "i1|i0")

(define_insn_reservation "fr500_i1_setlo" 1

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "setlo"))

  "i1|i0")

(define_insn_reservation "fr500_i1_int" 1

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "int"))

  "i1|i0")

(define_insn_reservation "fr500_i1_mul" 3

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "mul"))

  "i1|i0")

(define_insn_reservation "fr500_i1_div" 19

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "div"))

  "(i1|i0),(idiv1*18|idiv2*18)")

(define_insn_reservation "fr500_i2" 4

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "gload,fload"))

  "(i1|i0) + (fr500_load0|fr500_load1)")

(define_insn_reservation "fr500_i3" 0

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "gstore,fstore"))

  "i0 + fr500_store0")

(define_insn_reservation "fr500_i4" 3

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "movgf,movfg"))

  "i0")

(define_insn_reservation "fr500_i5" 0

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "jumpl"))

  "i0")

;;

;; Branch-instructions

;;

(define_insn_reservation "fr500_branch" 0

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "jump,branch,ccr"))

  "b1|b0")

(define_insn_reservation "fr500_call" 0

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "call"))

  "b0")

;; Floating point insns.  The default latencies are for non-media

;; instructions; media instructions incur an extra cycle.

(define_bypass 4 "fr500_farith" "fr500_m1,fr500_m2,fr500_m3,

                                 fr500_m4,fr500_m5,fr500_m6")

(define_insn_reservation "fr500_farith" 3

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "fnop,fsconv,fsadd,fsmul,fsmadd,fdconv,fdadd,fdmul,fdmadd"))

  "(f1|f0)")

(define_insn_reservation "fr500_fcmp" 4

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "fscmp,fdcmp"))

  "(f1|f0)")

(define_bypass 11 "fr500_fdiv" "fr500_m1,fr500_m2,fr500_m3,

                                fr500_m4,fr500_m5,fr500_m6")

(define_insn_reservation "fr500_fdiv" 10

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "fsdiv,fddiv"))

  "(f1|f0),(div1*9 | div2*9)")

(define_bypass 16 "fr500_froot" "fr500_m1,fr500_m2,fr500_m3,

                                 fr500_m4,fr500_m5,fr500_m6")

(define_insn_reservation "fr500_froot" 15

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "sqrt_single,sqrt_double"))

  "(f1|f0) + root*15")

;; Media insns.  Conflict table is as follows:

;;

;;           M1  M2  M3  M4  M5  M6

;;        M1  -   -   -   -   -   -

;;        M2  -   -   -   -   X   X

;;        M3  -   -   -   -   X   X

;;        M4  -   -   -   -   -   X

;;        M5  -   X   X   -   X   X

;;        M6  -   X   X   X   X   X

;;

;; where X indicates an invalid combination.

;;

;; Target registers are as follows:

;;

;;        M1 : FPRs

;;        M2 : FPRs

;;        M3 : ACCs

;;        M4 : ACCs

;;        M5 : FPRs

;;        M6 : ACCs

;;

;; The default FPR latencies are for integer instructions.

;; Floating-point instructions need one cycle more and media

;; instructions need one cycle less.

(define_automaton "fr500_media")

(define_cpu_unit "fr500_m2_0,fr500_m2_1" "fr500_media")

(define_cpu_unit "fr500_m3_0,fr500_m3_1" "fr500_media")

(define_cpu_unit "fr500_m4_0,fr500_m4_1" "fr500_media")

(define_cpu_unit "fr500_m5" "fr500_media")

(define_cpu_unit "fr500_m6" "fr500_media")

(exclusion_set "fr500_m5,fr500_m6" "fr500_m2_0,fr500_m2_1,

                                    fr500_m3_0,fr500_m3_1")

(exclusion_set "fr500_m6" "fr500_m4_0,fr500_m4_1,fr500_m5")

(define_bypass 2 "fr500_m1" "fr500_m1,fr500_m2,fr500_m3,

                             fr500_m4,fr500_m5,fr500_m6")

(define_bypass 4 "fr500_m1" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")

(define_insn_reservation "fr500_m1" 3

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "mnop,mlogic,maveh,msath,maddh,mqaddh"))

  "(f1|f0)")

(define_bypass 2 "fr500_m2" "fr500_m1,fr500_m2,fr500_m3,

                             fr500_m4,fr500_m5,fr500_m6")

(define_bypass 4 "fr500_m2" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")

(define_insn_reservation "fr500_m2" 3

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "mrdacc,mpackh,munpackh,mbhconv,mrot,mshift,mexpdhw,mexpdhd,mwcut,mcut,mdunpackh,mbhconve"))

  "(f1|f0) + (fr500_m2_0|fr500_m2_1)")

(define_bypass 1 "fr500_m3" "fr500_m4")

(define_insn_reservation "fr500_m3" 2

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "mclracc,mwtacc"))

  "(f1|f0) + (fr500_m3_0|fr500_m3_1)")

(define_bypass 1 "fr500_m4" "fr500_m4")

(define_insn_reservation "fr500_m4" 2

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mqmulh,mqmulxh,mqmach,mcpx,mqcpx"))

  "(f1|f0) + (fr500_m4_0|fr500_m4_1)")

(define_bypass 2 "fr500_m5" "fr500_m1,fr500_m2,fr500_m3,

                             fr500_m4,fr500_m5,fr500_m6")

(define_bypass 4 "fr500_m5" "fr500_farith,fr500_fcmp,fr500_fdiv,fr500_froot")

(define_insn_reservation "fr500_m5" 3

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "mdpackh"))

  "(f1|f0) + fr500_m5")

(define_bypass 1 "fr500_m6" "fr500_m4")

(define_insn_reservation "fr500_m6" 2

  (and (eq_attr "cpu" "generic,fr500,tomcat")

       (eq_attr "type" "mclracca"))

  "(f1|f0) + fr500_m6")

;; ::::::::::::::::::::

;; ::

;; :: FR400 scheduler description

;; ::

;; ::::::::::::::::::::

;; Category 2 media instructions use both media units, but can be packed

;; with non-media instructions.  Use fr400_m1unit to claim the M1 unit

;; without claiming a slot.

;; Name         Class   Units   Latency

;; ====         =====   =====   =======

;; int          I1      I0/I1   1

;; sethi        I1      I0/I1   0       -- does not interfere with setlo

;; setlo        I1      I0/I1   1

;; mul          I1      I0      3  (*)

;; div          I1      I0      20 (*)

;; gload        I2      I0      4  (*)

;; fload        I2      I0      4       -- only 3 if read by a media insn

;; gstore       I3      I0      0       -- provides no result

;; fstore       I3      I0      0       -- provides no result

;; movfg        I4      I0      3  (*)

;; movgf        I4      I0      3  (*)

;; jumpl        I5      I0      0       -- provides no result

;;

;; (*) The results of these instructions can be read one cycle earlier

;; than indicated.  The penalty given is for instructions with write-after-

;; write dependencies.

;; The FR400 can only do loads and stores in I0, so we there's no danger

;; of memory unit collision in the same packet.  There's only one divide

;; unit too.

(define_automaton "fr400_integer")

(define_cpu_unit "fr400_mul" "fr400_integer")

(define_insn_reservation "fr400_i1_int" 1

  (and (eq_attr "cpu" "fr400,fr405,fr450")

       (eq_attr "type" "int"))

  "i1|i0")

(define_bypass 0 "fr400_i1_sethi" "fr400_i1_setlo")

(define_insn_reservation "fr400_i1_sethi" 1

  (and (eq_attr "cpu" "fr400,fr405,fr450")

       (eq_attr "type" "sethi"))

  "i1|i0")

(define_insn_reservation "fr400_i1_setlo" 1

  (and (eq_attr "cpu" "fr400,fr405,fr450")

       (eq_attr "type" "setlo"))

  "i1|i0")

;; 3 is the worst case (write-after-write hazard).

(define_insn_reservation "fr400_i1_mul" 3

  (and (eq_attr "cpu" "fr400,fr405")

       (eq_attr "type" "mul"))

  "i0 + fr400_mul")

(define_insn_reservation "fr450_i1_mul" 2

  (and (eq_attr "cpu" "fr450")

       (eq_attr "type" "mul"))

  "i0 + fr400_mul")

(define_bypass 1 "fr400_i1_macc" "fr400_i1_macc")

(define_insn_reservation "fr400_i1_macc" 2

  (and (eq_attr "cpu" "fr405,fr450")

       (eq_attr "type" "macc"))

  "(i0|i1) + fr400_mul")

(define_insn_reservation "fr400_i1_scan" 1

  (and (eq_attr "cpu" "fr400,fr405,fr450")

       (eq_attr "type" "scan"))

  "i0")

(define_insn_reservation "fr400_i1_cut" 2

  (and (eq_attr "cpu" "fr405,fr450")

       (eq_attr "type" "cut"))

  "i0 + fr400_mul")

;; 20 is for a write-after-write hazard.

(define_insn_reservation "fr400_i1_div" 20

  (and (eq_attr "cpu" "fr400,fr405")

       (eq_attr "type" "div"))

  "i0 + idiv1*19")

(define_insn_reservation "fr450_i1_div" 19

  (and (eq_attr "cpu" "fr450")

       (eq_attr "type" "div"))

  "i0 + idiv1*19")

;; 4 is for a write-after-write hazard.

(define_insn_reservation "fr400_i2" 4

  (and (eq_attr "cpu" "fr400,fr405")

       (eq_attr "type" "gload,fload"))

  "i0")

(define_insn_reservation "fr450_i2_gload" 3

  (and (eq_attr "cpu" "fr450")

       (eq_attr "type" "gload"))

  "i0")

;; 4 is for a write-after-write hazard.

(define_insn_reservation "fr450_i2_fload" 4

  (and (eq_attr "cpu" "fr450")

       (eq_attr "type" "fload"))

  "i0")

(define_insn_reservation "fr400_i3" 0

  (and (eq_attr "cpu" "fr400,fr405,fr450")

       (eq_attr "type" "gstore,fstore"))

  "i0")

;; 3 is for a write-after-write hazard.

(define_insn_reservation "fr400_i4" 3

  (and (eq_attr "cpu" "fr400,fr405")

       (eq_attr "type" "movfg,movgf"))

  "i0")

(define_insn_reservation "fr450_i4_movfg" 2

  (and (eq_attr "cpu" "fr450")

       (eq_attr "type" "movfg"))

  "i0")

;; 3 is for a write-after-write hazard.

(define_insn_reservation "fr450_i4_movgf" 3

  (and (eq_attr "cpu" "fr450")

       (eq_attr "type" "movgf"))

  "i0")

(define_insn_reservation "fr400_i5" 0

  (and (eq_attr "cpu" "fr400,fr405,fr450")

       (eq_attr "type" "jumpl"))

  "i0")

;; The bypass between FPR loads and media instructions, described above.

(define_bypass 3

  "fr400_i2"

  "fr400_m1_1,fr400_m1_2,\

   fr400_m2_1,fr400_m2_2,\

   fr400_m3_1,fr400_m3_2,\

   fr400_m4_1,fr400_m4_2,\

   fr400_m5")

;; The branch instructions all use the B unit and produce no result.

(define_insn_reservation "fr400_b" 0

  (and (eq_attr "cpu" "fr400,fr405,fr450")

       (eq_attr "type" "jump,branch,ccr,call"))

  "b0")

;; FP->FP moves are marked as "fsconv" instructions in the define_insns

;; below, but are implemented on the FR400 using "mlogic" instructions.

;; It's easier to class "fsconv" as a "m1:1" instruction than provide

;; separate define_insns for the FR400.

;; M1 instructions store their results in FPRs.  Any instruction can read

;; the result in the following cycle, so no penalty occurs.

(define_automaton "fr400_media")

(define_cpu_unit "fr400_m1a,fr400_m1b,fr400_m2a" "fr400_media")

(exclusion_set "fr400_m1a,fr400_m1b" "fr400_m2a")

(define_reservation "fr400_m1" "(f1|f0) + (fr400_m1a|fr400_m1b)")

(define_reservation "fr400_m2" "f0 + fr400_m2a")

(define_insn_reservation "fr400_m1_1" 1

  (and (eq_attr "cpu" "fr400,fr405")

       (eq_attr "type" "fsconv,mnop,mlogic,maveh,msath,maddh,mabsh,mset"))

  "fr400_m1")

(define_insn_reservation "fr400_m1_2" 1

  (and (eq_attr "cpu" "fr400,fr405")

       (eq_attr "type" "mqaddh,mqsath,mqlimh,mqshift"))

  "fr400_m2")

;; M2 instructions store their results in accumulators, which are read

;; by M2 or M4 media commands.  M2 instructions can read the results in

;; the following cycle, but M4 instructions must wait a cycle more.

(define_bypass 1

  "fr400_m2_1,fr400_m2_2"

  "fr400_m2_1,fr400_m2_2")

(define_insn_reservation "fr400_m2_1" 2

  (and (eq_attr "cpu" "fr400,fr405")

       (eq_attr "type" "mmulh,mmulxh,mmach,mmrdh,mcpx,maddacc"))

  "fr400_m1")

(define_insn_reservation "fr400_m2_2" 2

  (and (eq_attr "cpu" "fr400,fr405")

       (eq_attr "type" "mqmulh,mqmulxh,mqmach,mqcpx,mdaddacc"))

  "fr400_m2")

;; For our purposes, there seems to be little real difference between

;; M1 and M3 instructions.  Keep them separate anyway in case the distinction

;; is needed later.

(define_insn_reservation "fr400_m3_1" 1

  (and (eq_attr "cpu" "fr400,fr405")