Subversion Repositories openrisc_2011-10-31

;; GCC machine description for picochip

;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.

;; Contributed by picoChip Designs Ltd (http://www.picochip.com)

;; Maintained by Daniel Towner (dant@picochip.com) and Hariharan

;; Sandanagobalane (hariharan@picochip.com)

;;

;; This file is part of GCC.

;;

;; GCC is free software; you can redistribute it and/or modify

;; it under the terms of the GNU General Public License as published by

;; the Free Software Foundation; either version 3, or (at your option)

;; any later version.

;;

;; GCC is distributed in the hope that it will be useful,

;; but WITHOUT ANY WARRANTY; without even the implied warranty of

;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

;; GNU General Public License for more details.

;;

;; You should have received a copy of the GNU General Public License

;; along with GCC; see the file COPYING3.  If not, see

;; .

;; -------------------------------------------------------------------------

;; In addition to the normal output operand formats, the following

;; letter formats are also available:

;;

;;  The following can be used for constants, or the constant part of a

;;  memory offset.

;;   Q - Output constant unaltered (byte mode).

;;   M - Alias for Q, which only works with memory operands.

;;   H - Divide constant by 2 (i.e., HImode is 2 bytes)

;;   S - Divide constant by 4 (i.e., SImode is 4 bytes)

;;

;;  The following can be used for two part addresses (i.e., base +

;;  offset or base[offset]).

;;   o - Output offset only.

;;   b - Output base only.

;;

;;  The following are used on SI registers and constants

;;   R - Output register pair (i.e., R[n:m])

;;   L - Output lower word/register

;;   U - Output upper word/register

;;

;;  The following are used on DI mode registers.

;;   X - Output 3rd register

;;   Y - Output 4th register

;;

;;  Miscellaneous

;;   | - Output VLIW separator

;;   r - Output register value of memory operand.

;;   I - Output an opcode (e.g., ADD for plus, LSL for lshift)

;;   i - Output an opcode in symbolic notation (e.g., + for plus)

;; Define the length of an instruction.  Used to allow different types

;; of branches to be used for different branch offsets.  Default to 6

;; bytes, which is the longest possible single instruction.

(define_attr "length" "" (const_int 6))

;; Define some constants which are used in conjuction with branch

;; scheduling.  Branches must be 10-bit signed, which equates to

;; [-512,511]. However, to compensate for the lack of branch alignment

;; these offsets are reduced by a factor of 2.

(define_constants

  [

   (MIN_BRANCH_OFFSET -256)

   (MAX_BRANCH_OFFSET 255)

   (SHORT_BRANCH_LENGTH 6)    ; The size of a schedulable short branch.

   (LONG_BRANCH_LENGTH 16)    ; The size of an expanded JMP?? macro.

   ]

)

;; Define identifiers for various special instructions.  These

;; instructions may then be used in RTL expansions, or builtins.

(define_constants

  [

   ; Special instruction builtins.

   (UNSPEC_SBC             0) ; Sign-bit count

   (UNSPEC_ADDS            1) ; Saturating addition

   (UNSPEC_SUBS            2) ; Saturating subtraction

   (UNSPEC_BREV            3) ; Bit reversal

   ; Special internal instructions (only used by compiler)

   (UNSPEC_COPYSW          5) ; Get status word

   (UNSPEC_ADDC            6) ; Add with carry.

   ; Scalar port communication builtins

   (UNSPEC_PUT             7) ; Communication (put):       port[op0] := op1

   (UNSPEC_GET             8) ; Communication (get):       op0 := get_port[op1]

   (UNSPEC_TESTPORT        9) ; Communication (test):      op0 := testport[op1]

   ; Array port communication builtins.  These all take extra

   ; arguments giving information about the array access being used.

   (UNSPEC_PUT_ARRAY      10) ; Array put

   (UNSPEC_GET_ARRAY      11) ; Array get

   (UNSPEC_TESTPORT_ARRAY 12) ; Array test port

   ;; Array port expansions

   (UNSPEC_CALL_GET_ARRAY 13) ;

   (UNSPEC_CALL_PUT_ARRAY 14) ;

   (UNSPEC_CALL_TESTPORT_ARRAY 15) ;

   ; Array port low-level fn calls

   (UNSPEC_CALL_GET_FN  16)

   (UNSPEC_CALL_TESTPORT_FN  17)

   ; Halt instruction.

   (UNSPEC_HALT 18)

   ; Internal TSTPORT instruction, used to generate a single TSTPORT

   ; instruction for use in the testport branch split.

   (UNSPEC_INTERNAL_TESTPORT        19)

  ]

)

;; Register ID's

(define_constants

  [

   (LINK_REGNUM           12) ; Function link register.

   (CC_REGNUM             17) ; Condition flags.

   (ACC_REGNUM             16) ; Condition flags.

   ]

)

;;============================================================================

;; Predicates and constraints

;;============================================================================

(include "predicates.md")

(include "constraints.md")

;;============================================================================

;; First operand shifting patterns.  These allow certain instructions

;; (e.g., add, and, or, xor, sub) to apply a shift-by-constant to

;; their first operand.

;;

;; Note that only the first operand is matched by the shift, to ensure

;; that non-commutative instructions (like subtract) work

;; properly.  When a commutative instruction, with a shift in the

;; second operand is found, the compiler will reorder the operands to

;; match.

;;============================================================================

(define_insn "*firstOpGenericAshift"

  [(set (match_operand:HI 0 "register_operand" "=r")

        (match_operator:HI 1 "picochip_first_op_shift_operator"

                        [(ashift:HI

                          (match_operand:HI 2 "register_operand" "r")

                          (match_operand:HI 3 "picochip_J_operand" "J"))

                         (match_operand:HI 4 "picochip_register_or_immediate_operand" "ri")]))

   (clobber (reg:CC CC_REGNUM))]

  ""

  "%I1.0 [LSL %2,%3],%4,%0\t// %0 := (%2 << %3) %i1 %4"

  [(set_attr "type" "picoAlu")

   ;; A long constant must be used if the operator instruction doesn't

   ;; accept immediates, or if the constant is too big to fit the

   ;; immediate. Note that the following condition is written in the

   ;; way which uses the least number of predicates.

   (set (attr "longConstant")

     (cond [(ior (match_operand 4 "register_operand")

                 (and (match_operand 1 "picochip_first_op_shift_operator_imm")

                      (match_operand 1 "picochip_J_operand")))

              (const_string "false")]

              (const_string "true")))])

;; During combine, ashift gets converted into a multiply, necessitating the following pattern.

;; Note that we do a log_2(imm) to get the actual LSL operand.

(define_insn "*firstOpGenericAshift"

  [(set (match_operand:HI 0 "register_operand" "=r")

        (match_operator:HI 1 "picochip_first_op_shift_operator"

                        [(mult:HI

                          (match_operand:HI 2 "register_operand" "r")

                          (match_operand:HI 3 "power_of_2_imm_operand" "n"))

                         (match_operand:HI 4 "picochip_register_or_immediate_operand" "ri")]))

   (clobber (reg:CC CC_REGNUM))]

  ""

  "%I1.0 [LSL %2,%P3],%4,%0\t// %0 := (%2 << %3) %i1 %4"

  [(set_attr "type" "picoAlu")

   ;; A long constant must be used if the operator instruction doesn't

   ;; accept immediates, or if the constant is too big to fit the

   ;; immediate. Note that the following condition is written in the

   ;; way which uses the least number of predicates.

   (set (attr "longConstant")

     (cond [(ior (match_operand 4 "register_operand")

                 (and (match_operand 1 "picochip_first_op_shift_operator_imm")

                      (match_operand 1 "picochip_J_operand")))

              (const_string "false")]

              (const_string "true")))])

(define_insn "*firstOpGenericAshiftrt"

  [(set (match_operand:HI 0 "register_operand" "=r")

        (match_operator:HI 1 "picochip_first_op_shift_operator"

                        [(ashiftrt:HI

                          (match_operand:HI 2 "register_operand" "r")

                          (match_operand:HI 3 "picochip_J_operand" "J"))

                         (match_operand:HI 4 "picochip_register_or_immediate_operand" "ri")]))

   (clobber (reg:CC CC_REGNUM))]

  ""

  "%I1.0 [ASR %2,%3],%4,%0\t// %0 := (%2 >>{arith} %3) %i1 %4"

  [(set_attr "type" "picoAlu")

   ;; A long constant must be used if the operator instruction doesn't

   ;; accept immediates, or if the constant is too big to fit the

   ;; immediate. Note that the following condition is written in the

   ;; way which uses the least number of predicates.

   (set (attr "longConstant")

     (cond [(ior (match_operand 4 "register_operand")

                 (and (match_operand 1 "picochip_first_op_shift_operator_imm")

                      (match_operand 1 "picochip_J_operand")))

              (const_string "false")]

              (const_string "true")))])

(define_insn "*firstOpGenericLshiftrt"

  [(set (match_operand:HI 0 "register_operand" "=r")

        (match_operator:HI 1 "picochip_first_op_shift_operator"

                        [(lshiftrt:HI

                          (match_operand:HI 2 "register_operand" "r")

                          (match_operand:HI 3 "picochip_J_operand" "J"))

                         (match_operand:HI 4 "picochip_register_or_immediate_operand" "ri")]))

   (clobber (reg:CC CC_REGNUM))]

  ""

  "%I1.0 [LSR %2,%3],%4,%0\t// %0 := (%2 >> %3) %i1 %4"

  [(set_attr "type" "picoAlu")

   ;; A long constant must be used if the operator instruction doesn't

   ;; accept immediates, or if the constant is too big to fit the

   ;; immediate. Note that the following condition is written in the

   ;; way which uses the least number of predicates.

   (set (attr "longConstant")

     (cond [(ior (match_operand 4 "register_operand")

                 (and (match_operand 1 "picochip_first_op_shift_operator_imm")

                      (match_operand 1 "picochip_J_operand")))

              (const_string "false")]

              (const_string "true")))])

;;===========================================================================

;; Jump instructions.

;;===========================================================================

(define_insn "indirect_jump"

  [(set (pc) (match_operand:HI 0 "register_operand" "r"))]

  ""

  "JR (%0)\t// Indirect_jump to %0 %>"

  [(set_attr "type" "realBranch")

   (set_attr "length" "3")])

(define_insn "jump"

  [(set (pc)

        (label_ref (match_operand 0 "" "")))]

  ""

  "* return picochip_output_jump(insn);"

  [(set (attr "length")

        (if_then_else

         (and (ge (minus (match_dup 0) (pc)) (const_int MIN_BRANCH_OFFSET))

              (le (minus (match_dup 0) (pc)) (const_int MAX_BRANCH_OFFSET)))

         (const_int SHORT_BRANCH_LENGTH)

         (const_int LONG_BRANCH_LENGTH)))

   (set (attr "type")

        (if_then_else

         (eq_attr "length" "6")

         (const_string "realBranch")

         (const_string "unknown")))])

(define_insn "*fn_return"

  [(return)

   (use (reg:HI LINK_REGNUM))]

  ""

  "JR (R12)\t// Return to caller %>"

  [(set_attr "length" "2")

   (set_attr "type" "realBranch")

   (set_attr "longConstant" "false")])

;; Peephole either 2 LDWs or STWs into LDL/STL.

(define_peephole2

  [(set (match_operand:HI 0 "register_operand" "")

        (match_operand:HI 1 "memory_operand" ""))

   (set (match_operand:HI 2 "register_operand" "")

        (match_operand:HI 3 "memory_operand" ""))]

  "ok_to_peephole_ldw(operands[0],operands[1],operands[2],operands[3])"

  [(set (match_dup 4) (match_dup 5))]

  "{

     operands[4] = gen_min_reg(operands[0],operands[2]);

     operands[5] = gen_SImode_mem(operands[1],operands[3]);

   }")

(define_peephole2

  [(set (match_operand:HI 0 "memory_operand" "")

        (match_operand:HI 1 "register_operand" ""))

   (set (match_operand:HI 2 "memory_operand" "")

        (match_operand:HI 3 "register_operand" ""))]

  "ok_to_peephole_stw(operands[0],operands[1],operands[2],operands[3])"

  [(set (match_dup 4) (match_dup 5))]

  "{

     operands[4] = gen_SImode_mem(operands[0],operands[2]);

     operands[5] = gen_min_reg(operands[1],operands[3]);

   }")

;; We have instructions like add,subtract,ior,and that set condition

;; codes if they are executed on slot 0. If we have

;;    add a = b + c

;;    if (a!=0)

;;    {}

;; We would have RTL sequence like

;;    add.# rb,rc,ra   # will be replaced by slot no, after scheduling

;;    sub.0 ra,0,r15

;;    bnz

;; Instead, we can just do

;;    add.0 rb,rc,ra

;;    bnz

(define_peephole2

  [(parallel [(set (match_operand:HI 0 "register_operand" "")

                   (plus:HI (match_operand:HI 1 "register_operand" "")

                            (match_operand:HI 2 "general_operand" "")))

              (clobber (reg:CC CC_REGNUM))])

   (parallel [(set (pc)

                   (if_then_else

                    (match_operator:CC 3 "picochip_peephole_comparison_operator"

                            [(match_dup 0) (const_int 0)])

                   (label_ref       (match_operand    6 "" ""))

                   (pc)))

              (clobber (reg:CC CC_REGNUM))])]

  ""

  [(parallel [(set (match_dup 0)

                   (plus:HI (match_dup 1) (match_dup 2)))

              (set (reg:CC CC_REGNUM)

                   (match_op_dup 3 [(const_int 0) (const_int 0)]))])

   (parallel [(set (pc)

                   (if_then_else

                    (match_op_dup:HI 3 [(reg:CC CC_REGNUM) (const_int 0)])

                   (label_ref (match_dup 6))

                   (pc)))

              (use (match_dup 7))])]

  "{

     operands[7] = GEN_INT(0);

   }")

(define_peephole2

  [(parallel [(set (match_operand:HI 0 "register_operand" "")

                   (plus:HI (match_operand:HI 1 "register_operand" "")

                     (match_operand:HI 2 "general_operand" "")))

              (clobber (reg:CC CC_REGNUM))])

   (set (reg:CC CC_REGNUM)

         (match_operator:CC 3 "picochip_peephole_comparison_operator"

                   [(match_dup 0) (const_int 0)]))

   (parallel [(set (pc)

                    (if_then_else

                          (match_operator 4 "comparison_operator"

                              [(reg:CC CC_REGNUM) (const_int 0)])

                     (label_ref (match_operand 5 "" ""))

                     (pc)))

               (use (match_operand:HI 6 "const_int_operand" ""))])]

  ""

  [(parallel [(set (match_dup 0)

                   (plus:HI (match_dup 1) (match_dup 2)))

              (set (reg:CC CC_REGNUM)

                   (match_op_dup 3 [(const_int 0) (const_int 0)]))])

   (parallel [(set (pc)

                   (if_then_else (match_op_dup:HI 4 [(reg:CC CC_REGNUM) (const_int 0)])

                    (label_ref (match_dup 5))

                    (pc)))

              (use (match_dup 6))])]

  "{

     operands[7] = GEN_INT(0);

   }")

;; If peephole happens before the cbranch split

(define_peephole2

  [(parallel [(set (match_operand:HI 0 "register_operand" "")

                    (minus:HI (match_operand:HI 1 "general_operand" "")

                              (match_operand:HI 2 "register_operand" "")))

              (clobber (reg:CC CC_REGNUM))])

   (parallel [(set (pc)

                   (if_then_else

                    (match_operator:CC 3 "picochip_peephole_comparison_operator"

                            [(match_dup 0) (const_int 0)])

                     (label_ref       (match_operand    6 "" ""))

                     (pc)))

              (clobber (reg:CC CC_REGNUM))])]

  ""

  [(parallel [(set (match_dup 0)

                   (minus:HI (match_dup 1) (match_dup 2)))

              (set (reg:CC CC_REGNUM)

                   (match_op_dup 3 [(const_int 0) (const_int 0)]))])

   (parallel [(set (pc)

                   (if_then_else

                       (match_op_dup:HI 3 [(reg:CC CC_REGNUM) (const_int 0)])

                        (label_ref (match_dup 6))

                        (pc)))

              (use (match_dup 7))])]

  "{

     operands[7] = GEN_INT(0);

   }")

;; If peephole happens after the cbranch split

(define_peephole2

  [(parallel [(set (match_operand:HI 0 "register_operand" "")

                   (minus:HI (match_operand:HI 1 "general_operand" "")

                             (match_operand:HI 2 "register_operand" "")))

              (clobber (reg:CC CC_REGNUM))])

   (set (reg:CC CC_REGNUM)

         (match_operator:CC 3 "picochip_peephole_comparison_operator"

                 [(match_dup 0) (const_int 0)]))

    (parallel [(set (pc)

                     (if_then_else

                         (match_operator 4 "comparison_operator"

                             [(reg:CC CC_REGNUM) (const_int 0)])

                      (label_ref (match_operand 5 "" ""))

                      (pc)))

                (use (match_operand:HI 6 "const_int_operand" ""))])]

  ""

  [(parallel [(set (match_dup 0)

                   (minus:HI (match_dup 1) (match_dup 2)))

              (set (reg:CC CC_REGNUM)

                   (match_op_dup 3 [(const_int 0) (const_int 0)]))])

   (parallel [(set (pc)

                   (if_then_else (match_op_dup:HI 4 [(reg:CC CC_REGNUM) (const_int 0)])

                                 (label_ref (match_dup 5))

                                 (pc)))

              (use (match_dup 6))])]

  "{

      operands[7] = GEN_INT(0);

   }")

;; If peephole happens before the cbranch split

(define_peephole2

   [(parallel[(set (match_operand:HI 0 "register_operand" "")

                   (and:HI (match_operand:HI 1 "register_operand" "")

                           (match_operand:HI 2 "general_operand" "")))

              (clobber (reg:CC CC_REGNUM))])

   (parallel [(set (pc)

                   (if_then_else

                    (match_operator:CC 3 "picochip_peephole_comparison_operator"

                            [(match_dup 0) (const_int 0)])

                   (label_ref       (match_operand    6 "" ""))

                   (pc)))

              (clobber (reg:CC CC_REGNUM))])]

  ""

  [(parallel [(set (match_dup 0)

                   (and:HI (match_dup 1) (match_dup 2)))

              (set (reg:CC CC_REGNUM)

                   (match_op_dup 3 [(const_int 0) (const_int 0)]))])

   (parallel [(set (pc)

                   (if_then_else

                       (match_op_dup:HI 3 [(reg:CC CC_REGNUM) (const_int 0)])

                                 (label_ref (match_dup 6))

                                 (pc)))

              (use (match_dup 7))])]

  "{

     operands[7] = GEN_INT(0);

   }")

(define_peephole2

   [(parallel[(set (match_operand:HI 0 "register_operand" "")

                   (and:HI (match_operand:HI 1 "register_operand" "")

                           (match_operand:HI 2 "general_operand" "")))

              (clobber (reg:CC CC_REGNUM))])

   (set (reg:CC CC_REGNUM)

        (match_operator:CC 3 "picochip_peephole_comparison_operator"

                    [(match_dup 0) (const_int 0)]))

  (parallel [(set (pc)

                  (if_then_else

                      (match_operator 4 "comparison_operator"

                         [(reg:CC CC_REGNUM) (const_int 0)])

                   (label_ref (match_operand 5 "" ""))

                   (pc)))

              (use (match_operand:HI 6 "const_int_operand" ""))])]

  ""

  [(parallel [(set (match_dup 0)

                   (and:HI (match_dup 1) (match_dup 2)))

              (set (reg:CC CC_REGNUM)

                   (match_op_dup 3 [(const_int 0) (const_int 0)]))])

   (parallel [(set (pc)

                   (if_then_else (match_op_dup:HI 4 [(reg:CC CC_REGNUM) (const_int 0)])

                                 (label_ref (match_dup 5))

                                 (pc)))

              (use (match_dup 6))])]

  "{

      operands[7] = GEN_INT(0);

   }")

;; If peephole happens before the cbranch split

(define_peephole2

   [(parallel[(set (match_operand:HI 0 "register_operand" "")

                   (ior:HI (match_operand:HI 1 "register_operand" "")

                           (match_operand:HI 2 "general_operand" "")))

              (clobber (reg:CC CC_REGNUM))])

   (parallel [(set (pc)

                   (if_then_else

                    (match_operator:CC 3 "picochip_peephole_comparison_operator"

                          [(match_dup 0) (const_int 0)])

                   (label_ref       (match_operand    6 "" ""))

                   (pc)))

              (clobber (reg:CC CC_REGNUM))])]

  ""

  [(parallel [(set (match_dup 0)

                   (ior:HI (match_dup 1) (match_dup 2)))

              (set (reg:CC CC_REGNUM)

                   (match_op_dup 3 [(const_int 0) (const_int 0)]))])

   (parallel [(set (pc)

                   (if_then_else

                       (match_op_dup:HI 3 [(reg:CC CC_REGNUM) (const_int 0)])

                                 (label_ref (match_dup 6))

                                 (pc)))

              (use (match_dup 7))])]

  "{

     operands[7] = GEN_INT(0);

   }")

(define_peephole2

   [(parallel[(set (match_operand:HI 0 "register_operand" "")

                   (ior:HI (match_operand:HI 1 "register_operand" "")

                           (match_operand:HI 2 "general_operand" "")))

              (clobber (reg:CC CC_REGNUM))])

   (set (reg:CC CC_REGNUM)

        (match_operator:CC 3 "picochip_peephole_comparison_operator"

              [(match_dup 0) (const_int 0)]))

  (parallel [(set (pc)

                  (if_then_else

                     (match_operator 4 "comparison_operator"

                        [(reg:CC CC_REGNUM) (const_int 0)])

                   (label_ref (match_operand 5 "" ""))

                   (pc)))

             (use (match_operand:HI 6 "const_int_operand" ""))])]

  ""

  [(parallel [(set (match_dup 0)

                   (ior:HI (match_dup 1) (match_dup 2)))

              (set (reg:CC CC_REGNUM)

                   (match_op_dup 3 [(const_int 0) (const_int 0)]))])

   (parallel [(set (pc)

                   (if_then_else (match_op_dup:HI 4 [(reg:CC CC_REGNUM) (const_int 0)])

                                 (label_ref (match_dup 5))

                                 (pc)))

              (use (match_dup 6))])]

  "{

      operands[7] = GEN_INT(0);

   }")

;; Conditional branch (HI). This is split into separate compare and

;; branch instructions if scheduling is enabled.  The branch

;; instruction is supplied with the type of comparison on which the

;; branch should occur.

(define_insn_and_split "cbranchhi4"

  [(set (pc)

        (if_then_else

            (match_operator:CC 0 "ordered_comparison_operator"

                            [(match_operand:HI 1 "register_operand" "r")

                             (match_operand:HI 2 "picochip_comparison_operand" "ri")])

            (label_ref       (match_operand    3 "" ""))

            (pc)))

   (clobber (reg:CC CC_REGNUM))]

  ""

  "* return picochip_output_cbranch(operands);"

  "reload_completed

   && (picochip_schedule_type != DFA_TYPE_NONE || flag_delayed_branch)"

  [(set (reg:CC CC_REGNUM) (match_dup 0))

   (parallel [(set (pc)

                   (if_then_else (match_op_dup:HI 0 [(reg:CC CC_REGNUM) (const_int 0)])

                                 (label_ref (match_dup 3))

                                 (pc)))

              (use (match_dup 4))])]

  "{

     operands[4] = GEN_INT(GET_CODE(operands[0]));

   }")

;; The only difference between this and the next pattern is that the next pattern

;; might introduce subtracts whose first operand is a constant. This would have to

;; be a longConstant. But, we know that such a situation wouldnt arise for supported

;; comparison operator and hence this pattern assumes that the second constraint combo

;; would still generate a normal instruction.

(define_insn "*supported_compare"

  [(set (reg:CC CC_REGNUM)

        (match_operator:CC 0 "picochip_supported_comparison_operator"

                        [(match_operand:HI 1 "register_operand" "r,r,r")

                         (match_operand:HI 2 "picochip_comparison_operand" "r,J,i")]))]

  ""

  "* return picochip_output_compare(operands);"

  [; Must be picoAlu because it sets the condition flags.

   (set_attr "type" "picoAlu,picoAlu,picoAlu")

   (set_attr "longConstant" "false,false,true")

   (set_attr "length" "2,2,4")

   ])

(define_insn "*compare"

  [(set (reg:CC CC_REGNUM)

        (match_operator:CC 0 "comparison_operator"

                        [(match_operand:HI 1 "register_operand" "r,r,r")

                         (match_operand:HI 2 "picochip_comparison_operand" "r,M,i")]))]

  ""

  "* return picochip_output_compare(operands);"

  [; Must be picoAlu because it sets the condition flags.

   (set_attr "type" "picoAlu,picoAlu,picoAlu")

   (set_attr "longConstant" "false,true,true")

   (set_attr "length" "2,4,4")

   ])

; Match a branch instruction, created from a tstport/cbranch split.

; We use a "use" clause so GCC doesnt try to use this pattern generally.

(define_insn "*branch"

  [(set (pc)

        (if_then_else

            (match_operator 2 "comparison_operator"

                 [(reg:CC CC_REGNUM) (const_int 0)])

                      (label_ref (match_operand 0 "" ""))

                      (pc)))

   (use (match_operand:HI 1 "const_int_operand" ""))]

  ""

  "* return picochip_output_branch(operands, insn);"

  [(set (attr "length")

        (if_then_else

         (and (ge (minus (match_dup 0) (pc)) (const_int MIN_BRANCH_OFFSET))

              (le (minus (match_dup 0) (pc)) (const_int MAX_BRANCH_OFFSET)))

         (const_int SHORT_BRANCH_LENGTH)

         (const_int LONG_BRANCH_LENGTH)))

    (set (attr "type")

        (if_then_else

         (eq_attr "length" "6")

         (const_string "realBranch")

         (const_string "unknown")))])

;; If a movqi is used which accesses memory on a machine which doesn't

;; have byte addressing, synthesise the instruction using word load/store

;; operations. The movqi's that are required during reload phase are

;; handled using reload_inqi/reload_outqi.

(define_expand "movqi"

  [(set (match_operand:QI 0 "nonimmediate_operand" "")

        (match_operand:QI 1 "general_operand" ""))]

  ""

{

     if (!reload_completed &&

         !TARGET_HAS_BYTE_ACCESS &&

         (MEM == GET_CODE(operands[0]) || MEM == GET_CODE(operands[1])))

     {

       rtx address;

       rtx wordAddress;

       rtx const1;

       rtx shiftVal;

       rtx loadedValue;

       rtx addressMask;

       warn_of_byte_access();

       /* Load the constant 1 into a register. */

       const1 = gen_reg_rtx(HImode);

       emit_insn(gen_rtx_SET(HImode, const1, GEN_INT(1)));

       /* Load the address mask with the bitwise complement of 1. */

       addressMask = gen_reg_rtx(HImode);

       emit_insn(gen_rtx_SET(HImode, addressMask, GEN_INT(-2)));

       /* Handle loads first, in case we are dealing with a mem := mem

        * instruction. */

       if (MEM == GET_CODE(operands[1]))

       {

         /* Loads work as follows. The entire word containing the desired byte

          * is loaded. The bottom bit of the address indicates which

          * byte is required. The desired byte is moved into the most

          * significant byte, and then an arithmetic shift right

          * invoked to achieve sign extension. The desired byte is

          * moved to the MSB by XOR'ing the bottom address bit by 1,

          * multiplying the result by 8, and then shifting left by

          * that amount. Note that shifts only operate on the bottom

          * 4-bits of the source offset, so although the XOR may

          * produce a value which has its upper bits set, only bit 4

          * (i.e., the inverted, shifted bottom address bit) actually

          * gets used.

          */

         /* Ensure the address is in a register. */

         address = gen_reg_rtx(HImode);

         emit_insn(gen_rtx_SET(HImode, address, XEXP(operands[1], 0)));

         /* Compute the word address by masking out the bottom bit. */

         wordAddress = gen_reg_rtx(HImode);

         emit_insn(gen_andhi3(wordAddress, address, addressMask));

         /* Compute the shift value. This is the bottom address bit,

          * inverted, and multiplied by 8. */

         shiftVal = gen_reg_rtx(HImode);

         emit_insn(gen_xorhi3(shiftVal, address, const1));

         emit_insn(gen_ashlhi3(shiftVal, shiftVal, GEN_INT(3)));

         /* Emit the memory load. */

         loadedValue = gen_reg_rtx(HImode);

         emit_insn(gen_rtx_SET(HImode, loadedValue, gen_rtx_MEM(HImode, wordAddress)));

         /* Shift the desired byte to the most significant byte. */

         rtx topByteValue = gen_reg_rtx (HImode);

         emit_insn (gen_ashlhi3 (topByteValue, loadedValue, shiftVal));

         /* Sign extend the top-byte back into the bottom byte. */

         rtx signExtendedValue = gen_reg_rtx(HImode);

         emit_insn(gen_ashrhi3(signExtendedValue, topByteValue, GEN_INT(8)));

         /* Final extraction of QI mode register. */

        operands[1] = gen_rtx_SUBREG(QImode, signExtendedValue, 0);

       }

       if (MEM == GET_CODE(operands[0]) && GET_CODE(operands[1]) != MEM)

       {

         rtx zeroingByteMask;

         rtx temp;

         rtx tempQiMode;

         rtx tempHiMode;

         /* Get the address. */

         address = gen_reg_rtx(HImode);

         emit_insn(gen_rtx_SET(HImode, address, XEXP(operands[0], 0)));

         /* Compute the word aligned address. */

         wordAddress = gen_reg_rtx(HImode);

         emit_insn(gen_andhi3(wordAddress, address, addressMask));

         /* Compute the shift value. */

         shiftVal = gen_reg_rtx(HImode);

         emit_insn(gen_andhi3(shiftVal, address, const1));

         emit_insn(gen_ashlhi3(shiftVal, shiftVal, GEN_INT(3)));

         /* Emit the memory load. */

         loadedValue = gen_reg_rtx(HImode);

         emit_insn(gen_rtx_SET(HImode, loadedValue, gen_rtx_MEM(HImode, wordAddress)));

         /* Zero out the destination bits by AND'ing with 0xFF00

          * shifted appropriately. */

         zeroingByteMask = gen_reg_rtx(HImode);

         emit_insn(gen_rtx_SET(HImode, zeroingByteMask, GEN_INT(-256)));

         emit_insn(gen_lshrhi3(zeroingByteMask, zeroingByteMask, shiftVal));

         emit_insn(gen_andhi3(loadedValue, loadedValue, zeroingByteMask));

         /* Grab the incoming QI register, and ensure that the top bits

          * are zeroed out. This is because the register may be

          * storing a signed value, in which case the top-bits will be

          * sign bits. These must be removed to ensure that the

          * read-modify-write (which uses an OR) doesn't pick up those

          * bits, instead of the original memory value which is being

          * modified.

          */

         /*if (register_operand(operands[1],QImode))

         {

           tempHiMode = XEXP(operands[1], 0);

         }

         else

         {

           tempHiMode = operands[1];

         }*/

         //tempHiMode = force_reg(QImode, operands[1]);

         tempHiMode = simplify_gen_subreg(HImode, operands[1], QImode, 0);

         temp = gen_reg_rtx(HImode);

         emit_insn(gen_rtx_SET(HImode, temp, tempHiMode));

         rtx lsbByteMask = gen_reg_rtx (HImode);

         emit_insn (gen_rtx_SET (HImode, lsbByteMask, GEN_INT (0xFF)));

         emit_insn (gen_andhi3 (temp, temp, lsbByteMask));

         /* Shift the incoming byte value by the appropriate amount,

          * and OR into the load value. */

         emit_insn(gen_ashlhi3(temp, temp, shiftVal));

         emit_insn(gen_iorhi3(loadedValue, loadedValue, temp));

         /* Rewrite the original assignment, to assign the new value

          * to the word address. */

         operands[0] = gen_rtx_MEM(HImode, wordAddress);

         operands[1] = loadedValue;

       }

     }

})

(define_insn "*movqi_sign_extend"

  [(set (match_operand:HI 0 "register_operand" "=r,r")

        (sign_extend:HI (match_operand:QI 1 "memory_operand" "a,m")))]

  "TARGET_HAS_BYTE_ACCESS"

  "@

     LDB (%a1),%0\t\t// %0 = Mem(%a1)

     LDB %a1,%0\t\t// %0 = Mem(%M1{byte})"

  [(set_attr "type" "mem,mem")

   (set_attr "longConstant" "true,false")

   (set_attr "length" "4,4")])

;; movqi instructions for machines with and without byte access.

(define_insn "*movqi_byte"

  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,r,a,m")

        (match_operand:QI 1 "general_operand" "r,a,m,I,i,r,r"))]

  "TARGET_HAS_BYTE_ACCESS"

  "@

     COPY.%# %1, %0\t// %0 := %1

     LDB (%a1),%0\t\t// %0 = Mem(%a1)

     LDB %a1,%0\t\t// %0 = Mem(%M1{byte})

     COPY.%# %1,%0\t\t// %0 := #%1 (QI) (short constant)

     COPY.%# %1,%0\t\t// %0 := #%1 (QI) (long constant)

     STB %1,(%a0)\t\t// Mem(%a0) := %1

     STB %1,%a0\t\t// Mem(%M0{byte}) := %1"

  [(set_attr "type" "basicAlu,mem,mem,basicAlu,basicAlu,mem,mem")

   (set_attr "longConstant" "false,true,false,false,true,true,false")

   (set_attr "length" "2,4,4,2,4,4,4")])

;; Machines which don't have byte access can copy registers, and load

;; constants, but can't access memory.  The define_expand for movqi

;; should already have rewritten memory accesses using word

;; operations.  The exception is qi reloads, which are handled using

;; the reload_? patterns.

(define_insn "*movqi_nobyte"

  [(set (match_operand:QI 0 "register_operand" "=r,r")

        (match_operand:QI 1 "picochip_register_or_immediate_operand" "r,i"))]

  "!TARGET_HAS_BYTE_ACCESS"

  "@

     COPY.%# %1,%0\t// %0 := %1

     COPY.%# %1,%0\t\t// %0 := #%1 (QI)")

(define_insn "movhi"

  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,a,m,r,r")

        (match_operand:HI 1 "general_operand" "r,a,m,r,r,I,i"))]

  ""

  "@

    COPY.%# %1,%0\t\t// %0 := %1

    LDW (%a1),%0\t\t// %0 := Mem(%a1)

    LDW %a1,%0\t\t// %0 = Mem(%M1{byte})

    STW %1,(%a0)\t\t// Mem(%a0) := %1

    STW %1,%a0\t\t// Mem(%M0{byte}) := %1

    COPY.%# %1,%0\t// %0 := %1 (short constant)

    COPY.%# %1,%0\t// %0 := %1 (long constant)"

   [(set_attr "type" "basicAlu,mem,mem,mem,mem,basicAlu,basicAlu")

    (set_attr "longConstant" "false,true,false,true,false,false,true")

    (set_attr "length" "2,4,4,4,4,2,4")])

(define_insn "movsi"

  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,a,m")

        (match_operand:SI 1 "general_operand" "r,a,m,i,r,r"))]

  ""

  "@

    // %R0 := %R1 (SI)\n\tCOPY.%# %L1,%L0 %| COPY.1 %U1,%U0

    LDL (%a1),%R0\t\t// %R0 = Mem(%a1)

    LDL %a1,%R0\t\t// %R0 = Mem(%M1{byte})

    // %R0 := #%1 (SI)\n\tCOPY.%# %L1,%L0 %| COPY.%# %U1,%U0

    STL %R1,(%a0)\t\t// Mem(%a0) := %R1

    STL %R1,%a0\t\t// Mem(%M0{byte}) := %R1"

  [(set_attr "type" "unknown,mem,mem,unknown,mem,mem")

   (set_attr "longConstant" "false,true,false,true,false,false")

   (set_attr "length" "4,4,4,6,4,4")])

; Split an SI mode register copy into separate HI mode copies, which

; can be VLIW'd with other instructions.  Only split the instruction

; when VLIW scheduling is enabled.  Splitting the instruction saves

; some code space.

;

; This is predicated in reload_completed.  This ensures that the

; instructions aren't broken up too early which can result in the

; SImode code being converted into inefficient HI mode code.

(define_split

  [(set (match_operand:SI 0 "register_operand" "")

        (match_operand:SI 1 "register_operand" ""))]

  "reload_completed && picochip_schedule_type == DFA_TYPE_SPEED"

  [(set (match_dup 2) (match_dup 3))

   (set (match_dup 4) (match_dup 5))]

  "{

     operands[2] = gen_lowpart (HImode, operands[0]);

     operands[3] = gen_lowpart (HImode, operands[1]);

     operands[4] = gen_highpart (HImode, operands[0]);

     operands[5] = gen_highpart (HImode, operands[1]);

 }")

; SI Mode split for load constant.

(define_split

  [(set (match_operand:SI 0 "register_operand" "")

        (match_operand:SI 1 "const_int_operand" ""))]

  ""

  [(set (match_dup 2) (match_dup 3))

   (set (match_dup 4) (match_dup 5))]

  "{

     operands[2] = gen_lowpart (HImode, operands[0]);

     operands[3] = picochip_get_low_const(operands[1]);

     operands[4] = gen_highpart (HImode, operands[0]);

     operands[5] = picochip_get_high_const(operands[1]);

 }")

(define_insn "movsf"

  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,m")

        (match_operand:SF 1 "general_operand" "r,m,i,r"))]

  ""

  "@

    // %R0 := %R1 (SF)\n\tCOPY.%# %L1,%L0 %| COPY.1 %U1,%U0

    LDL %a1,%R0\t\t// %R0 :={SF} Mem(%M1{byte})

    // %R0 := #%1 (SF)\n\tCOPY.%# %L1,%L0\n\tCOPY.%# %U1,%U0

    STL %R1,%a0\t\t// Mem(%M0{byte}) :={SF} %R1")

;;===========================================================================

;; NOP

;;===========================================================================

;; No-operation (NOP)

(define_insn "nop"

  [(const_int 0)]

  ""

  "NOP\t// nop"

  [(set_attr "length" "1")])

;;===========================================================================

;; Function Calls.  Define expands are used to ensure that the correct

;; type of pattern is emitted, and then the define_insn's match the

;; pattern using the correct types.

;;

;; Note: The comments output as part of these instructions are detected by

;; the linker. Don't change the comments!

;;===========================================================================

(define_expand "call"

  [(parallel [(call (match_operand:QI 0 "memory_operand" "")

         (match_operand 1 "const_int_operand" ""))

         (clobber (reg:HI LINK_REGNUM))])]

  ""

  "")

(define_insn "call_for_divmod"

  [(call (match_operand:QI 0 "memory_operand" "")

         (match_operand 1 "const_int_operand" ""))]

  ""

  "JL (%M0)\t// fn_call %M0%>"

  [(set_attr "length" "4")

   (set_attr "type" "realBranch")

   (set_attr "longConstant" "true")])

(define_insn "*call_using_symbol"

  [(call (mem:QI (match_operand:HI 0 "immediate_operand" "i"))

         (match_operand 1 "const_int_operand" ""))

         (clobber (reg:HI LINK_REGNUM))]

  ""