OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc2/] [gcc/] [config/] [rs6000/] [rs6000.md] - Blame information for rev 384

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 282 jeremybenn 
;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 
;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 
;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 
;; Free Software Foundation, Inc.
5 
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 
 
7 
;; This file is part of GCC.
8 
 
9 
;; GCC is free software; you can redistribute it and/or modify it
10 
;; under the terms of the GNU General Public License as published
11 
;; by the Free Software Foundation; either version 3, or (at your
12 
;; option) any later version.
13 
 
14 
;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
17 
;; License for more details.
18 
 
19 
;; You should have received a copy of the GNU General Public License
20 
;; along with GCC; see the file COPYING3.  If not see
21 
;; .
22 
 
23 
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 
 
25 
;;
26 
;; REGNOS
27 
;;
28 
 
29 
(define_constants
30 
  [(MQ_REGNO                    64)
31 
   (LR_REGNO                    65)
32 
   (CTR_REGNO                   66)
33 
   (CR0_REGNO                   68)
34 
   (CR1_REGNO                   69)
35 
   (CR2_REGNO                   70)
36 
   (CR3_REGNO                   71)
37 
   (CR4_REGNO                   72)
38 
   (CR5_REGNO                   73)
39 
   (CR6_REGNO                   74)
40 
   (CR7_REGNO                   75)
41 
   (MAX_CR_REGNO                75)
42 
   (XER_REGNO                   76)
43 
   (FIRST_ALTIVEC_REGNO         77)
44 
   (LAST_ALTIVEC_REGNO          108)
45 
   (VRSAVE_REGNO                109)
46 
   (VSCR_REGNO                  110)
47 
   (SPE_ACC_REGNO               111)
48 
   (SPEFSCR_REGNO               112)
49 
   (SFP_REGNO                   113)
50 
  ])
51 
 
52 
;;
53 
;; UNSPEC usage
54 
;;
55 
 
56 
(define_constants
57 
  [(UNSPEC_FRSP                 0)      ; frsp for POWER machines
58 
   (UNSPEC_PROBE_STACK          4)      ; probe stack memory reference
59 
   (UNSPEC_TIE                  5)      ; tie stack contents and stack pointer
60 
   (UNSPEC_TOCPTR               6)      ; address of a word pointing to the TOC
61 
   (UNSPEC_TOC                  7)      ; address of the TOC (more-or-less)
62 
   (UNSPEC_MOVSI_GOT            8)
63 
   (UNSPEC_MV_CR_OV             9)      ; move_from_CR_ov_bit
64 
   (UNSPEC_FCTIWZ               10)
65 
   (UNSPEC_FRIM                 11)
66 
   (UNSPEC_FRIN                 12)
67 
   (UNSPEC_FRIP                 13)
68 
   (UNSPEC_FRIZ                 14)
69 
   (UNSPEC_LD_MPIC              15)     ; load_macho_picbase
70 
   (UNSPEC_MPIC_CORRECT         16)     ; macho_correct_pic
71 
   (UNSPEC_TLSGD                17)
72 
   (UNSPEC_TLSLD                18)
73 
   (UNSPEC_MOVESI_FROM_CR       19)
74 
   (UNSPEC_MOVESI_TO_CR         20)
75 
   (UNSPEC_TLSDTPREL            21)
76 
   (UNSPEC_TLSDTPRELHA          22)
77 
   (UNSPEC_TLSDTPRELLO          23)
78 
   (UNSPEC_TLSGOTDTPREL         24)
79 
   (UNSPEC_TLSTPREL             25)
80 
   (UNSPEC_TLSTPRELHA           26)
81 
   (UNSPEC_TLSTPRELLO           27)
82 
   (UNSPEC_TLSGOTTPREL          28)
83 
   (UNSPEC_TLSTLS               29)
84 
   (UNSPEC_FIX_TRUNC_TF         30)     ; fadd, rounding towards zero
85 
   (UNSPEC_MV_CR_GT             31)     ; move_from_CR_gt_bit
86 
   (UNSPEC_STFIWX               32)
87 
   (UNSPEC_POPCNTB              33)
88 
   (UNSPEC_FRES                 34)
89 
   (UNSPEC_SP_SET               35)
90 
   (UNSPEC_SP_TEST              36)
91 
   (UNSPEC_SYNC                 37)
92 
   (UNSPEC_LWSYNC               38)
93 
   (UNSPEC_ISYNC                39)
94 
   (UNSPEC_SYNC_OP              40)
95 
   (UNSPEC_ATOMIC               41)
96 
   (UNSPEC_CMPXCHG              42)
97 
   (UNSPEC_XCHG                 43)
98 
   (UNSPEC_AND                  44)
99 
   (UNSPEC_DLMZB                45)
100 
   (UNSPEC_DLMZB_CR             46)
101 
   (UNSPEC_DLMZB_STRLEN         47)
102 
   (UNSPEC_RSQRT                48)
103 
   (UNSPEC_TOCREL               49)
104 
   (UNSPEC_MACHOPIC_OFFSET      50)
105 
   (UNSPEC_BPERM                51)
106 
  ])
107 
 
108 
;;
109 
;; UNSPEC_VOLATILE usage
110 
;;
111 
 
112 
(define_constants
113 
  [(UNSPECV_BLOCK               0)
114 
   (UNSPECV_LL                  1)      ; load-locked
115 
   (UNSPECV_SC                  2)      ; store-conditional
116 
   (UNSPECV_EH_RR               9)      ; eh_reg_restore
117 
  ])
118 
 
119 
;; Define an insn type attribute.  This is used in function unit delay
120 
;; computations.
121 
(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
122 
  (const_string "integer"))
123 
 
124 
;; Define floating point instruction sub-types for use with Xfpu.md
125 
(define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
126 
 
127 
;; Length (in bytes).
128 
; '(pc)' in the following doesn't include the instruction itself; it is
129 
; calculated as if the instruction had zero size.
130 
(define_attr "length" ""
131 
  (if_then_else (eq_attr "type" "branch")
132 
                (if_then_else (and (ge (minus (match_dup 0) (pc))
133 
                                       (const_int -32768))
134 
                                   (lt (minus (match_dup 0) (pc))
135 
                                       (const_int 32764)))
136 
                              (const_int 4)
137 
                              (const_int 8))
138 
                (const_int 4)))
139 
 
140 
;; Processor type -- this attribute must exactly match the processor_type
141 
;; enumeration in rs6000.h.
142 
 
143 
(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2"
144 
  (const (symbol_ref "rs6000_cpu_attr")))
145 
 
146 
 
147 
;; If this instruction is microcoded on the CELL processor
148 
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
149 
(define_attr "cell_micro" "not,conditional,always"
150 
  (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
151 
                (const_string "always")
152 
                (const_string "not")))
153 
 
154 
(automata_option "ndfa")
155 
 
156 
(include "rios1.md")
157 
(include "rios2.md")
158 
(include "rs64.md")
159 
(include "mpc.md")
160 
(include "40x.md")
161 
(include "440.md")
162 
(include "476.md")
163 
(include "603.md")
164 
(include "6xx.md")
165 
(include "7xx.md")
166 
(include "7450.md")
167 
(include "8540.md")
168 
(include "e300c2c3.md")
169 
(include "e500mc.md")
170 
(include "e500mc64.md")
171 
(include "power4.md")
172 
(include "power5.md")
173 
(include "power6.md")
174 
(include "power7.md")
175 
(include "cell.md")
176 
(include "xfpu.md")
177 
(include "a2.md")
178 
 
179 
(include "predicates.md")
180 
(include "constraints.md")
181 
 
182 
(include "darwin.md")
183 
 
184 
 
185 
;; Mode iterators
186 
 
187 
; This mode iterator allows :GPR to be used to indicate the allowable size
188 
; of whole values in GPRs.
189 
(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
190 
 
191 
; Any supported integer mode.
192 
(define_mode_iterator INT [QI HI SI DI TI])
193 
 
194 
; Any supported integer mode that fits in one register.
195 
(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
196 
 
197 
; extend modes for DImode
198 
(define_mode_iterator QHSI [QI HI SI])
199 
 
200 
; SImode or DImode, even if DImode doesn't fit in GPRs.
201 
(define_mode_iterator SDI [SI DI])
202 
 
203 
; The size of a pointer.  Also, the size of the value that a record-condition
204 
; (one with a '.') will compare.
205 
(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
206 
 
207 
; Any hardware-supported floating-point mode
208 
(define_mode_iterator FP [
209 
  (SF "TARGET_HARD_FLOAT
210 
   && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
211 
  (DF "TARGET_HARD_FLOAT
212 
   && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
213 
  (TF "!TARGET_IEEEQUAD
214 
   && TARGET_HARD_FLOAT
215 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
216 
   && TARGET_LONG_DOUBLE_128")
217 
  (DD "TARGET_DFP")
218 
  (TD "TARGET_DFP")])
219 
 
220 
; These modes do not fit in integer registers in 32-bit mode.
221 
; but on e500v2, the gpr are 64 bit registers
222 
(define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
223 
 
224 
; Various instructions that come in SI and DI forms.
225 
; A generic w/d attribute, for things like cmpw/cmpd.
226 
(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
227 
 
228 
; DImode bits
229 
(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
230 
 
231 
;; ISEL/ISEL64 target selection
232 
(define_mode_attr sel [(SI "") (DI "64")])
233 
 
234 
;; Suffix for reload patterns
235 
(define_mode_attr ptrsize [(SI "32bit")
236 
                           (DI "64bit")])
237 
 
238 
(define_mode_attr tptrsize [(SI "TARGET_32BIT")
239 
                            (DI "TARGET_64BIT")])
240 
 
241 
(define_mode_attr mptrsize [(SI "si")
242 
                            (DI "di")])
243 
 
244 
 
245 
;; Start with fixed-point load and store insns.  Here we put only the more
246 
;; complex forms.  Basic data transfer is done later.
247 
 
248 
(define_expand "zero_extenddi2"
249 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
250 
        (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
251 
  "TARGET_POWERPC64"
252 
  "")
253 
 
254 
(define_insn "*zero_extenddi2_internal1"
255 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
256 
        (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
257 
  "TARGET_POWERPC64"
258 
  "@
259 
   lz%U1%X1 %0,%1
260 
   rldicl %0,%1,0,"
261 
  [(set_attr "type" "load,*")])
262 
 
263 
(define_insn "*zero_extenddi2_internal2"
264 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
265 
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
266 
                    (const_int 0)))
267 
   (clobber (match_scratch:DI 2 "=r,r"))]
268 
  "TARGET_64BIT"
269 
  "@
270 
   rldicl. %2,%1,0,
271 
   #"
272 
  [(set_attr "type" "compare")
273 
   (set_attr "length" "4,8")])
274 
 
275 
(define_split
276 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
277 
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
278 
                    (const_int 0)))
279 
   (clobber (match_scratch:DI 2 ""))]
280 
  "TARGET_POWERPC64 && reload_completed"
281 
  [(set (match_dup 2)
282 
        (zero_extend:DI (match_dup 1)))
283 
   (set (match_dup 0)
284 
        (compare:CC (match_dup 2)
285 
                    (const_int 0)))]
286 
  "")
287 
 
288 
(define_insn "*zero_extenddi2_internal3"
289 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
290 
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
291 
                    (const_int 0)))
292 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
293 
        (zero_extend:DI (match_dup 1)))]
294 
  "TARGET_64BIT"
295 
  "@
296 
   rldicl. %0,%1,0,
297 
   #"
298 
  [(set_attr "type" "compare")
299 
   (set_attr "length" "4,8")])
300 
 
301 
(define_split
302 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
303 
        (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
304 
                    (const_int 0)))
305 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
306 
        (zero_extend:DI (match_dup 1)))]
307 
  "TARGET_POWERPC64 && reload_completed"
308 
  [(set (match_dup 0)
309 
        (zero_extend:DI (match_dup 1)))
310 
   (set (match_dup 2)
311 
        (compare:CC (match_dup 0)
312 
                    (const_int 0)))]
313 
  "")
314 
 
315 
(define_insn "extendqidi2"
316 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
317 
        (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
318 
  "TARGET_POWERPC64"
319 
  "extsb %0,%1"
320 
  [(set_attr "type" "exts")])
321 
 
322 
(define_insn ""
323 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
324 
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
325 
                    (const_int 0)))
326 
   (clobber (match_scratch:DI 2 "=r,r"))]
327 
  "TARGET_64BIT"
328 
  "@
329 
   extsb. %2,%1
330 
   #"
331 
  [(set_attr "type" "compare")
332 
   (set_attr "length" "4,8")])
333 
 
334 
(define_split
335 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
336 
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
337 
                    (const_int 0)))
338 
   (clobber (match_scratch:DI 2 ""))]
339 
  "TARGET_POWERPC64 && reload_completed"
340 
  [(set (match_dup 2)
341 
        (sign_extend:DI (match_dup 1)))
342 
   (set (match_dup 0)
343 
        (compare:CC (match_dup 2)
344 
                    (const_int 0)))]
345 
  "")
346 
 
347 
(define_insn ""
348 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
349 
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
350 
                    (const_int 0)))
351 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
352 
        (sign_extend:DI (match_dup 1)))]
353 
  "TARGET_64BIT"
354 
  "@
355 
   extsb. %0,%1
356 
   #"
357 
  [(set_attr "type" "compare")
358 
   (set_attr "length" "4,8")])
359 
 
360 
(define_split
361 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
362 
        (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
363 
                    (const_int 0)))
364 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
365 
        (sign_extend:DI (match_dup 1)))]
366 
  "TARGET_POWERPC64 && reload_completed"
367 
  [(set (match_dup 0)
368 
        (sign_extend:DI (match_dup 1)))
369 
   (set (match_dup 2)
370 
        (compare:CC (match_dup 0)
371 
                    (const_int 0)))]
372 
  "")
373 
 
374 
(define_expand "extendhidi2"
375 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
376 
        (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
377 
  "TARGET_POWERPC64"
378 
  "")
379 
 
380 
(define_insn ""
381 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
382 
        (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
383 
  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
384 
  "@
385 
   lha%U1%X1 %0,%1
386 
   extsh %0,%1"
387 
  [(set_attr "type" "load_ext,exts")])
388 
 
389 
(define_insn ""
390 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
391 
        (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
392 
  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
393 
  "extsh %0,%1"
394 
  [(set_attr "type" "exts")])
395 
 
396 
(define_insn ""
397 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
398 
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
399 
                    (const_int 0)))
400 
   (clobber (match_scratch:DI 2 "=r,r"))]
401 
  "TARGET_64BIT"
402 
  "@
403 
   extsh. %2,%1
404 
   #"
405 
  [(set_attr "type" "compare")
406 
   (set_attr "length" "4,8")])
407 
 
408 
(define_split
409 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
410 
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
411 
                    (const_int 0)))
412 
   (clobber (match_scratch:DI 2 ""))]
413 
  "TARGET_POWERPC64 && reload_completed"
414 
  [(set (match_dup 2)
415 
        (sign_extend:DI (match_dup 1)))
416 
   (set (match_dup 0)
417 
        (compare:CC (match_dup 2)
418 
                    (const_int 0)))]
419 
  "")
420 
 
421 
(define_insn ""
422 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
423 
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
424 
                    (const_int 0)))
425 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
426 
        (sign_extend:DI (match_dup 1)))]
427 
  "TARGET_64BIT"
428 
  "@
429 
   extsh. %0,%1
430 
   #"
431 
  [(set_attr "type" "compare")
432 
   (set_attr "length" "4,8")])
433 
 
434 
(define_split
435 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
436 
        (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
437 
                    (const_int 0)))
438 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
439 
        (sign_extend:DI (match_dup 1)))]
440 
  "TARGET_POWERPC64 && reload_completed"
441 
  [(set (match_dup 0)
442 
        (sign_extend:DI (match_dup 1)))
443 
   (set (match_dup 2)
444 
        (compare:CC (match_dup 0)
445 
                    (const_int 0)))]
446 
  "")
447 
 
448 
(define_expand "extendsidi2"
449 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
450 
        (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
451 
  "TARGET_POWERPC64"
452 
  "")
453 
 
454 
(define_insn ""
455 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
456 
        (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
457 
  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
458 
  "@
459 
   lwa%U1%X1 %0,%1
460 
   extsw %0,%1"
461 
  [(set_attr "type" "load_ext,exts")])
462 
 
463 
(define_insn ""
464 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
465 
        (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
466 
  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
467 
  "extsw %0,%1"
468 
  [(set_attr "type" "exts")])
469 
 
470 
(define_insn ""
471 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
472 
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
473 
                    (const_int 0)))
474 
   (clobber (match_scratch:DI 2 "=r,r"))]
475 
  "TARGET_64BIT"
476 
  "@
477 
   extsw. %2,%1
478 
   #"
479 
  [(set_attr "type" "compare")
480 
   (set_attr "length" "4,8")])
481 
 
482 
(define_split
483 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
484 
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
485 
                    (const_int 0)))
486 
   (clobber (match_scratch:DI 2 ""))]
487 
  "TARGET_POWERPC64 && reload_completed"
488 
  [(set (match_dup 2)
489 
        (sign_extend:DI (match_dup 1)))
490 
   (set (match_dup 0)
491 
        (compare:CC (match_dup 2)
492 
                    (const_int 0)))]
493 
  "")
494 
 
495 
(define_insn ""
496 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
497 
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
498 
                    (const_int 0)))
499 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
500 
        (sign_extend:DI (match_dup 1)))]
501 
  "TARGET_64BIT"
502 
  "@
503 
   extsw. %0,%1
504 
   #"
505 
  [(set_attr "type" "compare")
506 
   (set_attr "length" "4,8")])
507 
 
508 
(define_split
509 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
510 
        (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
511 
                    (const_int 0)))
512 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
513 
        (sign_extend:DI (match_dup 1)))]
514 
  "TARGET_POWERPC64 && reload_completed"
515 
  [(set (match_dup 0)
516 
        (sign_extend:DI (match_dup 1)))
517 
   (set (match_dup 2)
518 
        (compare:CC (match_dup 0)
519 
                    (const_int 0)))]
520 
  "")
521 
 
522 
(define_expand "zero_extendqisi2"
523 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
524 
        (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
525 
  ""
526 
  "")
527 
 
528 
(define_insn ""
529 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
530 
        (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
531 
  ""
532 
  "@
533 
   lbz%U1%X1 %0,%1
534 
   {rlinm|rlwinm} %0,%1,0,0xff"
535 
  [(set_attr "type" "load,*")])
536 
 
537 
(define_insn ""
538 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
539 
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
540 
                    (const_int 0)))
541 
   (clobber (match_scratch:SI 2 "=r,r"))]
542 
  ""
543 
  "@
544 
   {andil.|andi.} %2,%1,0xff
545 
   #"
546 
  [(set_attr "type" "fast_compare,compare")
547 
   (set_attr "length" "4,8")])
548 
 
549 
(define_split
550 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
551 
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
552 
                    (const_int 0)))
553 
   (clobber (match_scratch:SI 2 ""))]
554 
  "reload_completed"
555 
  [(set (match_dup 2)
556 
        (zero_extend:SI (match_dup 1)))
557 
   (set (match_dup 0)
558 
        (compare:CC (match_dup 2)
559 
                    (const_int 0)))]
560 
  "")
561 
 
562 
(define_insn ""
563 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
564 
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
565 
                    (const_int 0)))
566 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
567 
        (zero_extend:SI (match_dup 1)))]
568 
  ""
569 
  "@
570 
   {andil.|andi.} %0,%1,0xff
571 
   #"
572 
  [(set_attr "type" "fast_compare,compare")
573 
   (set_attr "length" "4,8")])
574 
 
575 
(define_split
576 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
577 
        (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
578 
                    (const_int 0)))
579 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
580 
        (zero_extend:SI (match_dup 1)))]
581 
  "reload_completed"
582 
  [(set (match_dup 0)
583 
        (zero_extend:SI (match_dup 1)))
584 
   (set (match_dup 2)
585 
        (compare:CC (match_dup 0)
586 
                    (const_int 0)))]
587 
  "")
588 
 
589 
(define_expand "extendqisi2"
590 
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
591 
   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
592 
  ""
593 
  "
594 
{
595 
  if (TARGET_POWERPC)
596 
    emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
597 
  else if (TARGET_POWER)
598 
    emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
599 
  else
600 
    emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
601 
  DONE;
602 
}")
603 
 
604 
(define_insn "extendqisi2_ppc"
605 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
606 
        (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
607 
  "TARGET_POWERPC"
608 
  "extsb %0,%1"
609 
  [(set_attr "type" "exts")])
610 
 
611 
(define_insn ""
612 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
613 
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
614 
                    (const_int 0)))
615 
   (clobber (match_scratch:SI 2 "=r,r"))]
616 
  "TARGET_POWERPC"
617 
  "@
618 
   extsb. %2,%1
619 
   #"
620 
  [(set_attr "type" "compare")
621 
   (set_attr "length" "4,8")])
622 
 
623 
(define_split
624 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
625 
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
626 
                    (const_int 0)))
627 
   (clobber (match_scratch:SI 2 ""))]
628 
  "TARGET_POWERPC && reload_completed"
629 
  [(set (match_dup 2)
630 
        (sign_extend:SI (match_dup 1)))
631 
   (set (match_dup 0)
632 
        (compare:CC (match_dup 2)
633 
                    (const_int 0)))]
634 
  "")
635 
 
636 
(define_insn ""
637 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
638 
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
639 
                    (const_int 0)))
640 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
641 
        (sign_extend:SI (match_dup 1)))]
642 
  "TARGET_POWERPC"
643 
  "@
644 
   extsb. %0,%1
645 
   #"
646 
  [(set_attr "type" "compare")
647 
   (set_attr "length" "4,8")])
648 
 
649 
(define_split
650 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
651 
        (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
652 
                    (const_int 0)))
653 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
654 
        (sign_extend:SI (match_dup 1)))]
655 
  "TARGET_POWERPC && reload_completed"
656 
  [(set (match_dup 0)
657 
        (sign_extend:SI (match_dup 1)))
658 
   (set (match_dup 2)
659 
        (compare:CC (match_dup 0)
660 
                    (const_int 0)))]
661 
  "")
662 
 
663 
(define_expand "extendqisi2_power"
664 
  [(parallel [(set (match_dup 2)
665 
                   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
666 
                              (const_int 24)))
667 
              (clobber (scratch:SI))])
668 
   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
669 
                   (ashiftrt:SI (match_dup 2)
670 
                                (const_int 24)))
671 
              (clobber (scratch:SI))])]
672 
  "TARGET_POWER"
673 
  "
674 
{ operands[1] = gen_lowpart (SImode, operands[1]);
675 
  operands[2] = gen_reg_rtx (SImode); }")
676 
 
677 
(define_expand "extendqisi2_no_power"
678 
  [(set (match_dup 2)
679 
        (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
680 
                   (const_int 24)))
681 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
682 
        (ashiftrt:SI (match_dup 2)
683 
                     (const_int 24)))]
684 
  "! TARGET_POWER && ! TARGET_POWERPC"
685 
  "
686 
{ operands[1] = gen_lowpart (SImode, operands[1]);
687 
  operands[2] = gen_reg_rtx (SImode); }")
688 
 
689 
(define_expand "zero_extendqihi2"
690 
  [(set (match_operand:HI 0 "gpc_reg_operand" "")
691 
        (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
692 
  ""
693 
  "")
694 
 
695 
(define_insn ""
696 
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
697 
        (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
698 
  ""
699 
  "@
700 
   lbz%U1%X1 %0,%1
701 
   {rlinm|rlwinm} %0,%1,0,0xff"
702 
  [(set_attr "type" "load,*")])
703 
 
704 
(define_insn ""
705 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
706 
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
707 
                    (const_int 0)))
708 
   (clobber (match_scratch:HI 2 "=r,r"))]
709 
  ""
710 
  "@
711 
   {andil.|andi.} %2,%1,0xff
712 
   #"
713 
  [(set_attr "type" "fast_compare,compare")
714 
   (set_attr "length" "4,8")])
715 
 
716 
(define_split
717 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
718 
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
719 
                    (const_int 0)))
720 
   (clobber (match_scratch:HI 2 ""))]
721 
  "reload_completed"
722 
  [(set (match_dup 2)
723 
        (zero_extend:HI (match_dup 1)))
724 
   (set (match_dup 0)
725 
        (compare:CC (match_dup 2)
726 
                    (const_int 0)))]
727 
  "")
728 
 
729 
(define_insn ""
730 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
731 
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
732 
                    (const_int 0)))
733 
   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
734 
        (zero_extend:HI (match_dup 1)))]
735 
  ""
736 
  "@
737 
   {andil.|andi.} %0,%1,0xff
738 
   #"
739 
  [(set_attr "type" "fast_compare,compare")
740 
   (set_attr "length" "4,8")])
741 
 
742 
(define_split
743 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
744 
        (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
745 
                    (const_int 0)))
746 
   (set (match_operand:HI 0 "gpc_reg_operand" "")
747 
        (zero_extend:HI (match_dup 1)))]
748 
  "reload_completed"
749 
  [(set (match_dup 0)
750 
        (zero_extend:HI (match_dup 1)))
751 
   (set (match_dup 2)
752 
        (compare:CC (match_dup 0)
753 
                    (const_int 0)))]
754 
  "")
755 
 
756 
(define_expand "extendqihi2"
757 
  [(use (match_operand:HI 0 "gpc_reg_operand" ""))
758 
   (use (match_operand:QI 1 "gpc_reg_operand" ""))]
759 
  ""
760 
  "
761 
{
762 
  if (TARGET_POWERPC)
763 
    emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
764 
  else if (TARGET_POWER)
765 
    emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
766 
  else
767 
    emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
768 
  DONE;
769 
}")
770 
 
771 
(define_insn "extendqihi2_ppc"
772 
  [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
773 
        (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
774 
  "TARGET_POWERPC"
775 
  "extsb %0,%1"
776 
  [(set_attr "type" "exts")])
777 
 
778 
(define_insn ""
779 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
780 
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
781 
                    (const_int 0)))
782 
   (clobber (match_scratch:HI 2 "=r,r"))]
783 
  "TARGET_POWERPC"
784 
  "@
785 
   extsb. %2,%1
786 
   #"
787 
  [(set_attr "type" "compare")
788 
   (set_attr "length" "4,8")])
789 
 
790 
(define_split
791 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
792 
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
793 
                    (const_int 0)))
794 
   (clobber (match_scratch:HI 2 ""))]
795 
  "TARGET_POWERPC && reload_completed"
796 
  [(set (match_dup 2)
797 
        (sign_extend:HI (match_dup 1)))
798 
   (set (match_dup 0)
799 
        (compare:CC (match_dup 2)
800 
                    (const_int 0)))]
801 
  "")
802 
 
803 
(define_insn ""
804 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
805 
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
806 
                    (const_int 0)))
807 
   (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
808 
        (sign_extend:HI (match_dup 1)))]
809 
  "TARGET_POWERPC"
810 
  "@
811 
   extsb. %0,%1
812 
   #"
813 
  [(set_attr "type" "compare")
814 
   (set_attr "length" "4,8")])
815 
 
816 
(define_split
817 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
818 
        (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
819 
                    (const_int 0)))
820 
   (set (match_operand:HI 0 "gpc_reg_operand" "")
821 
        (sign_extend:HI (match_dup 1)))]
822 
  "TARGET_POWERPC && reload_completed"
823 
  [(set (match_dup 0)
824 
        (sign_extend:HI (match_dup 1)))
825 
   (set (match_dup 2)
826 
        (compare:CC (match_dup 0)
827 
                    (const_int 0)))]
828 
  "")
829 
 
830 
(define_expand "extendqihi2_power"
831 
  [(parallel [(set (match_dup 2)
832 
                   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
833 
                              (const_int 24)))
834 
              (clobber (scratch:SI))])
835 
   (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
836 
                   (ashiftrt:SI (match_dup 2)
837 
                                (const_int 24)))
838 
              (clobber (scratch:SI))])]
839 
  "TARGET_POWER"
840 
  "
841 
{ operands[0] = gen_lowpart (SImode, operands[0]);
842 
  operands[1] = gen_lowpart (SImode, operands[1]);
843 
  operands[2] = gen_reg_rtx (SImode); }")
844 
 
845 
(define_expand "extendqihi2_no_power"
846 
  [(set (match_dup 2)
847 
        (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
848 
                   (const_int 24)))
849 
   (set (match_operand:HI 0 "gpc_reg_operand" "")
850 
        (ashiftrt:SI (match_dup 2)
851 
                     (const_int 24)))]
852 
  "! TARGET_POWER && ! TARGET_POWERPC"
853 
  "
854 
{ operands[0] = gen_lowpart (SImode, operands[0]);
855 
  operands[1] = gen_lowpart (SImode, operands[1]);
856 
  operands[2] = gen_reg_rtx (SImode); }")
857 
 
858 
(define_expand "zero_extendhisi2"
859 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
860 
        (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
861 
  ""
862 
  "")
863 
 
864 
(define_insn ""
865 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
866 
        (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
867 
  ""
868 
  "@
869 
   lhz%U1%X1 %0,%1
870 
   {rlinm|rlwinm} %0,%1,0,0xffff"
871 
  [(set_attr "type" "load,*")])
872 
 
873 
(define_insn ""
874 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
875 
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
876 
                    (const_int 0)))
877 
   (clobber (match_scratch:SI 2 "=r,r"))]
878 
  ""
879 
  "@
880 
   {andil.|andi.} %2,%1,0xffff
881 
   #"
882 
  [(set_attr "type" "fast_compare,compare")
883 
   (set_attr "length" "4,8")])
884 
 
885 
(define_split
886 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
887 
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
888 
                    (const_int 0)))
889 
   (clobber (match_scratch:SI 2 ""))]
890 
  "reload_completed"
891 
  [(set (match_dup 2)
892 
        (zero_extend:SI (match_dup 1)))
893 
   (set (match_dup 0)
894 
        (compare:CC (match_dup 2)
895 
                    (const_int 0)))]
896 
  "")
897 
 
898 
(define_insn ""
899 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
900 
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
901 
                    (const_int 0)))
902 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
903 
        (zero_extend:SI (match_dup 1)))]
904 
  ""
905 
  "@
906 
   {andil.|andi.} %0,%1,0xffff
907 
   #"
908 
  [(set_attr "type" "fast_compare,compare")
909 
   (set_attr "length" "4,8")])
910 
 
911 
(define_split
912 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
913 
        (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
914 
                    (const_int 0)))
915 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
916 
        (zero_extend:SI (match_dup 1)))]
917 
  "reload_completed"
918 
  [(set (match_dup 0)
919 
        (zero_extend:SI (match_dup 1)))
920 
   (set (match_dup 2)
921 
        (compare:CC (match_dup 0)
922 
                    (const_int 0)))]
923 
  "")
924 
 
925 
(define_expand "extendhisi2"
926 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
927 
        (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
928 
  ""
929 
  "")
930 
 
931 
(define_insn ""
932 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
933 
        (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
934 
  "rs6000_gen_cell_microcode"
935 
  "@
936 
   lha%U1%X1 %0,%1
937 
   {exts|extsh} %0,%1"
938 
  [(set_attr "type" "load_ext,exts")])
939 
 
940 
(define_insn ""
941 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
942 
        (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
943 
  "!rs6000_gen_cell_microcode"
944 
  "{exts|extsh} %0,%1"
945 
  [(set_attr "type" "exts")])
946 
 
947 
(define_insn ""
948 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
949 
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
950 
                    (const_int 0)))
951 
   (clobber (match_scratch:SI 2 "=r,r"))]
952 
  ""
953 
  "@
954 
   {exts.|extsh.} %2,%1
955 
   #"
956 
  [(set_attr "type" "compare")
957 
   (set_attr "length" "4,8")])
958 
 
959 
(define_split
960 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
961 
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
962 
                    (const_int 0)))
963 
   (clobber (match_scratch:SI 2 ""))]
964 
  "reload_completed"
965 
  [(set (match_dup 2)
966 
        (sign_extend:SI (match_dup 1)))
967 
   (set (match_dup 0)
968 
        (compare:CC (match_dup 2)
969 
                    (const_int 0)))]
970 
  "")
971 
 
972 
(define_insn ""
973 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
974 
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
975 
                    (const_int 0)))
976 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
977 
        (sign_extend:SI (match_dup 1)))]
978 
  ""
979 
  "@
980 
   {exts.|extsh.} %0,%1
981 
   #"
982 
  [(set_attr "type" "compare")
983 
   (set_attr "length" "4,8")])
984 
 
985 
;; IBM 405, 440, 464 and 476 half-word multiplication operations.
986 
 
987 
(define_insn "*macchwc"
988 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
989 
        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
990 
                                       (match_operand:SI 2 "gpc_reg_operand" "r")
991 
                                       (const_int 16))
992 
                                      (sign_extend:SI
993 
                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
994 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
995 
                    (const_int 0)))
996 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
997 
        (plus:SI (mult:SI (ashiftrt:SI
998 
                           (match_dup 2)
999 
                           (const_int 16))
1000 
                          (sign_extend:SI
1001 
                           (match_dup 1)))
1002 
                 (match_dup 4)))]
1003 
  "TARGET_MULHW"
1004 
  "macchw. %0, %1, %2"
1005 
  [(set_attr "type" "imul3")])
1006 
 
1007 
(define_insn "*macchw"
1008 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1009 
        (plus:SI (mult:SI (ashiftrt:SI
1010 
                           (match_operand:SI 2 "gpc_reg_operand" "r")
1011 
                           (const_int 16))
1012 
                          (sign_extend:SI
1013 
                           (match_operand:HI 1 "gpc_reg_operand" "r")))
1014 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1015 
  "TARGET_MULHW"
1016 
  "macchw %0, %1, %2"
1017 
  [(set_attr "type" "imul3")])
1018 
 
1019 
(define_insn "*macchwuc"
1020 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1021 
        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1022 
                                       (match_operand:SI 2 "gpc_reg_operand" "r")
1023 
                                       (const_int 16))
1024 
                                      (zero_extend:SI
1025 
                                       (match_operand:HI 1 "gpc_reg_operand" "r")))
1026 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
1027 
                    (const_int 0)))
1028 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1029 
        (plus:SI (mult:SI (lshiftrt:SI
1030 
                           (match_dup 2)
1031 
                           (const_int 16))
1032 
                          (zero_extend:SI
1033 
                           (match_dup 1)))
1034 
                 (match_dup 4)))]
1035 
  "TARGET_MULHW"
1036 
  "macchwu. %0, %1, %2"
1037 
  [(set_attr "type" "imul3")])
1038 
 
1039 
(define_insn "*macchwu"
1040 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1041 
        (plus:SI (mult:SI (lshiftrt:SI
1042 
                           (match_operand:SI 2 "gpc_reg_operand" "r")
1043 
                           (const_int 16))
1044 
                          (zero_extend:SI
1045 
                           (match_operand:HI 1 "gpc_reg_operand" "r")))
1046 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1047 
  "TARGET_MULHW"
1048 
  "macchwu %0, %1, %2"
1049 
  [(set_attr "type" "imul3")])
1050 
 
1051 
(define_insn "*machhwc"
1052 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1053 
        (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1054 
                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
1055 
                                       (const_int 16))
1056 
                                      (ashiftrt:SI
1057 
                                       (match_operand:SI 2 "gpc_reg_operand" "r")
1058 
                                       (const_int 16)))
1059 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
1060 
                    (const_int 0)))
1061 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1062 
        (plus:SI (mult:SI (ashiftrt:SI
1063 
                           (match_dup 1)
1064 
                           (const_int 16))
1065 
                          (ashiftrt:SI
1066 
                           (match_dup 2)
1067 
                           (const_int 16)))
1068 
                 (match_dup 4)))]
1069 
  "TARGET_MULHW"
1070 
  "machhw. %0, %1, %2"
1071 
  [(set_attr "type" "imul3")])
1072 
 
1073 
(define_insn "*machhw"
1074 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1075 
        (plus:SI (mult:SI (ashiftrt:SI
1076 
                           (match_operand:SI 1 "gpc_reg_operand" "%r")
1077 
                           (const_int 16))
1078 
                          (ashiftrt:SI
1079 
                           (match_operand:SI 2 "gpc_reg_operand" "r")
1080 
                           (const_int 16)))
1081 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1082 
  "TARGET_MULHW"
1083 
  "machhw %0, %1, %2"
1084 
  [(set_attr "type" "imul3")])
1085 
 
1086 
(define_insn "*machhwuc"
1087 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1088 
        (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1089 
                                       (match_operand:SI 1 "gpc_reg_operand" "%r")
1090 
                                       (const_int 16))
1091 
                                      (lshiftrt:SI
1092 
                                       (match_operand:SI 2 "gpc_reg_operand" "r")
1093 
                                       (const_int 16)))
1094 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
1095 
                    (const_int 0)))
1096 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1097 
        (plus:SI (mult:SI (lshiftrt:SI
1098 
                           (match_dup 1)
1099 
                           (const_int 16))
1100 
                          (lshiftrt:SI
1101 
                           (match_dup 2)
1102 
                           (const_int 16)))
1103 
                 (match_dup 4)))]
1104 
  "TARGET_MULHW"
1105 
  "machhwu. %0, %1, %2"
1106 
  [(set_attr "type" "imul3")])
1107 
 
1108 
(define_insn "*machhwu"
1109 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1110 
        (plus:SI (mult:SI (lshiftrt:SI
1111 
                           (match_operand:SI 1 "gpc_reg_operand" "%r")
1112 
                           (const_int 16))
1113 
                          (lshiftrt:SI
1114 
                           (match_operand:SI 2 "gpc_reg_operand" "r")
1115 
                           (const_int 16)))
1116 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1117 
  "TARGET_MULHW"
1118 
  "machhwu %0, %1, %2"
1119 
  [(set_attr "type" "imul3")])
1120 
 
1121 
(define_insn "*maclhwc"
1122 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1123 
        (compare:CC (plus:SI (mult:SI (sign_extend:SI
1124 
                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
1125 
                                      (sign_extend:SI
1126 
                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
1127 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
1128 
                    (const_int 0)))
1129 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1130 
        (plus:SI (mult:SI (sign_extend:SI
1131 
                           (match_dup 1))
1132 
                          (sign_extend:SI
1133 
                           (match_dup 2)))
1134 
                 (match_dup 4)))]
1135 
  "TARGET_MULHW"
1136 
  "maclhw. %0, %1, %2"
1137 
  [(set_attr "type" "imul3")])
1138 
 
1139 
(define_insn "*maclhw"
1140 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1141 
        (plus:SI (mult:SI (sign_extend:SI
1142 
                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
1143 
                          (sign_extend:SI
1144 
                           (match_operand:HI 2 "gpc_reg_operand" "r")))
1145 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1146 
  "TARGET_MULHW"
1147 
  "maclhw %0, %1, %2"
1148 
  [(set_attr "type" "imul3")])
1149 
 
1150 
(define_insn "*maclhwuc"
1151 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1152 
        (compare:CC (plus:SI (mult:SI (zero_extend:SI
1153 
                                       (match_operand:HI 1 "gpc_reg_operand" "%r"))
1154 
                                      (zero_extend:SI
1155 
                                       (match_operand:HI 2 "gpc_reg_operand" "r")))
1156 
                             (match_operand:SI 4 "gpc_reg_operand" "0"))
1157 
                    (const_int 0)))
1158 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1159 
        (plus:SI (mult:SI (zero_extend:SI
1160 
                           (match_dup 1))
1161 
                          (zero_extend:SI
1162 
                           (match_dup 2)))
1163 
                 (match_dup 4)))]
1164 
  "TARGET_MULHW"
1165 
  "maclhwu. %0, %1, %2"
1166 
  [(set_attr "type" "imul3")])
1167 
 
1168 
(define_insn "*maclhwu"
1169 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1170 
        (plus:SI (mult:SI (zero_extend:SI
1171 
                           (match_operand:HI 1 "gpc_reg_operand" "%r"))
1172 
                          (zero_extend:SI
1173 
                           (match_operand:HI 2 "gpc_reg_operand" "r")))
1174 
                 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1175 
  "TARGET_MULHW"
1176 
  "maclhwu %0, %1, %2"
1177 
  [(set_attr "type" "imul3")])
1178 
 
1179 
(define_insn "*nmacchwc"
1180 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1181 
        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1182 
                              (mult:SI (ashiftrt:SI
1183 
                                        (match_operand:SI 2 "gpc_reg_operand" "r")
1184 
                                        (const_int 16))
1185 
                                       (sign_extend:SI
1186 
                                        (match_operand:HI 1 "gpc_reg_operand" "r"))))
1187 
                    (const_int 0)))
1188 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1189 
        (minus:SI (match_dup 4)
1190 
                  (mult:SI (ashiftrt:SI
1191 
                            (match_dup 2)
1192 
                            (const_int 16))
1193 
                           (sign_extend:SI
1194 
                            (match_dup 1)))))]
1195 
  "TARGET_MULHW"
1196 
  "nmacchw. %0, %1, %2"
1197 
  [(set_attr "type" "imul3")])
1198 
 
1199 
(define_insn "*nmacchw"
1200 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1201 
        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1202 
                  (mult:SI (ashiftrt:SI
1203 
                            (match_operand:SI 2 "gpc_reg_operand" "r")
1204 
                            (const_int 16))
1205 
                           (sign_extend:SI
1206 
                            (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1207 
  "TARGET_MULHW"
1208 
  "nmacchw %0, %1, %2"
1209 
  [(set_attr "type" "imul3")])
1210 
 
1211 
(define_insn "*nmachhwc"
1212 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1213 
        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1214 
                              (mult:SI (ashiftrt:SI
1215 
                                        (match_operand:SI 1 "gpc_reg_operand" "%r")
1216 
                                        (const_int 16))
1217 
                                       (ashiftrt:SI
1218 
                                        (match_operand:SI 2 "gpc_reg_operand" "r")
1219 
                                        (const_int 16))))
1220 
                    (const_int 0)))
1221 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1222 
        (minus:SI (match_dup 4)
1223 
                  (mult:SI (ashiftrt:SI
1224 
                            (match_dup 1)
1225 
                            (const_int 16))
1226 
                           (ashiftrt:SI
1227 
                            (match_dup 2)
1228 
                            (const_int 16)))))]
1229 
  "TARGET_MULHW"
1230 
  "nmachhw. %0, %1, %2"
1231 
  [(set_attr "type" "imul3")])
1232 
 
1233 
(define_insn "*nmachhw"
1234 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1235 
        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1236 
                  (mult:SI (ashiftrt:SI
1237 
                            (match_operand:SI 1 "gpc_reg_operand" "%r")
1238 
                            (const_int 16))
1239 
                           (ashiftrt:SI
1240 
                            (match_operand:SI 2 "gpc_reg_operand" "r")
1241 
                            (const_int 16)))))]
1242 
  "TARGET_MULHW"
1243 
  "nmachhw %0, %1, %2"
1244 
  [(set_attr "type" "imul3")])
1245 
 
1246 
(define_insn "*nmaclhwc"
1247 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1248 
        (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1249 
                              (mult:SI (sign_extend:SI
1250 
                                        (match_operand:HI 1 "gpc_reg_operand" "%r"))
1251 
                                       (sign_extend:SI
1252 
                                        (match_operand:HI 2 "gpc_reg_operand" "r"))))
1253 
                    (const_int 0)))
1254 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 
        (minus:SI (match_dup 4)
1256 
                  (mult:SI (sign_extend:SI
1257 
                            (match_dup 1))
1258 
                           (sign_extend:SI
1259 
                            (match_dup 2)))))]
1260 
  "TARGET_MULHW"
1261 
  "nmaclhw. %0, %1, %2"
1262 
  [(set_attr "type" "imul3")])
1263 
 
1264 
(define_insn "*nmaclhw"
1265 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 
        (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1267 
                  (mult:SI (sign_extend:SI
1268 
                            (match_operand:HI 1 "gpc_reg_operand" "%r"))
1269 
                           (sign_extend:SI
1270 
                            (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1271 
  "TARGET_MULHW"
1272 
  "nmaclhw %0, %1, %2"
1273 
  [(set_attr "type" "imul3")])
1274 
 
1275 
(define_insn "*mulchwc"
1276 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1277 
        (compare:CC (mult:SI (ashiftrt:SI
1278 
                              (match_operand:SI 2 "gpc_reg_operand" "r")
1279 
                              (const_int 16))
1280 
                             (sign_extend:SI
1281 
                              (match_operand:HI 1 "gpc_reg_operand" "r")))
1282 
                    (const_int 0)))
1283 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1284 
        (mult:SI (ashiftrt:SI
1285 
                  (match_dup 2)
1286 
                  (const_int 16))
1287 
                 (sign_extend:SI
1288 
                  (match_dup 1))))]
1289 
  "TARGET_MULHW"
1290 
  "mulchw. %0, %1, %2"
1291 
  [(set_attr "type" "imul3")])
1292 
 
1293 
(define_insn "*mulchw"
1294 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1295 
        (mult:SI (ashiftrt:SI
1296 
                  (match_operand:SI 2 "gpc_reg_operand" "r")
1297 
                  (const_int 16))
1298 
                 (sign_extend:SI
1299 
                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1300 
  "TARGET_MULHW"
1301 
  "mulchw %0, %1, %2"
1302 
  [(set_attr "type" "imul3")])
1303 
 
1304 
(define_insn "*mulchwuc"
1305 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1306 
        (compare:CC (mult:SI (lshiftrt:SI
1307 
                              (match_operand:SI 2 "gpc_reg_operand" "r")
1308 
                              (const_int 16))
1309 
                             (zero_extend:SI
1310 
                              (match_operand:HI 1 "gpc_reg_operand" "r")))
1311 
                    (const_int 0)))
1312 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1313 
        (mult:SI (lshiftrt:SI
1314 
                  (match_dup 2)
1315 
                  (const_int 16))
1316 
                 (zero_extend:SI
1317 
                  (match_dup 1))))]
1318 
  "TARGET_MULHW"
1319 
  "mulchwu. %0, %1, %2"
1320 
  [(set_attr "type" "imul3")])
1321 
 
1322 
(define_insn "*mulchwu"
1323 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1324 
        (mult:SI (lshiftrt:SI
1325 
                  (match_operand:SI 2 "gpc_reg_operand" "r")
1326 
                  (const_int 16))
1327 
                 (zero_extend:SI
1328 
                  (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1329 
  "TARGET_MULHW"
1330 
  "mulchwu %0, %1, %2"
1331 
  [(set_attr "type" "imul3")])
1332 
 
1333 
(define_insn "*mulhhwc"
1334 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1335 
        (compare:CC (mult:SI (ashiftrt:SI
1336 
                              (match_operand:SI 1 "gpc_reg_operand" "%r")
1337 
                              (const_int 16))
1338 
                             (ashiftrt:SI
1339 
                              (match_operand:SI 2 "gpc_reg_operand" "r")
1340 
                              (const_int 16)))
1341 
                    (const_int 0)))
1342 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1343 
        (mult:SI (ashiftrt:SI
1344 
                  (match_dup 1)
1345 
                  (const_int 16))
1346 
                 (ashiftrt:SI
1347 
                  (match_dup 2)
1348 
                  (const_int 16))))]
1349 
  "TARGET_MULHW"
1350 
  "mulhhw. %0, %1, %2"
1351 
  [(set_attr "type" "imul3")])
1352 
 
1353 
(define_insn "*mulhhw"
1354 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1355 
        (mult:SI (ashiftrt:SI
1356 
                  (match_operand:SI 1 "gpc_reg_operand" "%r")
1357 
                  (const_int 16))
1358 
                 (ashiftrt:SI
1359 
                  (match_operand:SI 2 "gpc_reg_operand" "r")
1360 
                  (const_int 16))))]
1361 
  "TARGET_MULHW"
1362 
  "mulhhw %0, %1, %2"
1363 
  [(set_attr "type" "imul3")])
1364 
 
1365 
(define_insn "*mulhhwuc"
1366 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1367 
        (compare:CC (mult:SI (lshiftrt:SI
1368 
                              (match_operand:SI 1 "gpc_reg_operand" "%r")
1369 
                              (const_int 16))
1370 
                             (lshiftrt:SI
1371 
                              (match_operand:SI 2 "gpc_reg_operand" "r")
1372 
                              (const_int 16)))
1373 
                    (const_int 0)))
1374 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1375 
        (mult:SI (lshiftrt:SI
1376 
                  (match_dup 1)
1377 
                  (const_int 16))
1378 
                 (lshiftrt:SI
1379 
                  (match_dup 2)
1380 
                  (const_int 16))))]
1381 
  "TARGET_MULHW"
1382 
  "mulhhwu. %0, %1, %2"
1383 
  [(set_attr "type" "imul3")])
1384 
 
1385 
(define_insn "*mulhhwu"
1386 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1387 
        (mult:SI (lshiftrt:SI
1388 
                  (match_operand:SI 1 "gpc_reg_operand" "%r")
1389 
                  (const_int 16))
1390 
                 (lshiftrt:SI
1391 
                  (match_operand:SI 2 "gpc_reg_operand" "r")
1392 
                  (const_int 16))))]
1393 
  "TARGET_MULHW"
1394 
  "mulhhwu %0, %1, %2"
1395 
  [(set_attr "type" "imul3")])
1396 
 
1397 
(define_insn "*mullhwc"
1398 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1399 
        (compare:CC (mult:SI (sign_extend:SI
1400 
                              (match_operand:HI 1 "gpc_reg_operand" "%r"))
1401 
                             (sign_extend:SI
1402 
                              (match_operand:HI 2 "gpc_reg_operand" "r")))
1403 
                    (const_int 0)))
1404 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 
        (mult:SI (sign_extend:SI
1406 
                  (match_dup 1))
1407 
                 (sign_extend:SI
1408 
                  (match_dup 2))))]
1409 
  "TARGET_MULHW"
1410 
  "mullhw. %0, %1, %2"
1411 
  [(set_attr "type" "imul3")])
1412 
 
1413 
(define_insn "*mullhw"
1414 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1415 
        (mult:SI (sign_extend:SI
1416 
                  (match_operand:HI 1 "gpc_reg_operand" "%r"))
1417 
                 (sign_extend:SI
1418 
                  (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1419 
  "TARGET_MULHW"
1420 
  "mullhw %0, %1, %2"
1421 
  [(set_attr "type" "imul3")])
1422 
 
1423 
(define_insn "*mullhwuc"
1424 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1425 
        (compare:CC (mult:SI (zero_extend:SI
1426 
                              (match_operand:HI 1 "gpc_reg_operand" "%r"))
1427 
                             (zero_extend:SI
1428 
                              (match_operand:HI 2 "gpc_reg_operand" "r")))
1429 
                    (const_int 0)))
1430 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1431 
        (mult:SI (zero_extend:SI
1432 
                  (match_dup 1))
1433 
                 (zero_extend:SI
1434 
                  (match_dup 2))))]
1435 
  "TARGET_MULHW"
1436 
  "mullhwu. %0, %1, %2"
1437 
  [(set_attr "type" "imul3")])
1438 
 
1439 
(define_insn "*mullhwu"
1440 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1441 
        (mult:SI (zero_extend:SI
1442 
                  (match_operand:HI 1 "gpc_reg_operand" "%r"))
1443 
                 (zero_extend:SI
1444 
                  (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1445 
  "TARGET_MULHW"
1446 
  "mullhwu %0, %1, %2"
1447 
  [(set_attr "type" "imul3")])
1448 
 
1449 
;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1450 
(define_insn "dlmzb"
1451 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1452 
        (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1453 
                    (match_operand:SI 2 "gpc_reg_operand" "r")]
1454 
                   UNSPEC_DLMZB_CR))
1455 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1456 
        (unspec:SI [(match_dup 1)
1457 
                    (match_dup 2)]
1458 
                   UNSPEC_DLMZB))]
1459 
  "TARGET_DLMZB"
1460 
  "dlmzb. %0, %1, %2")
1461 
 
1462 
(define_expand "strlensi"
1463 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
1464 
        (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1465 
                    (match_operand:QI 2 "const_int_operand" "")
1466 
                    (match_operand 3 "const_int_operand" "")]
1467 
                   UNSPEC_DLMZB_STRLEN))
1468 
   (clobber (match_scratch:CC 4 "=x"))]
1469 
  "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1470 
{
1471 
  rtx result = operands[0];
1472 
  rtx src = operands[1];
1473 
  rtx search_char = operands[2];
1474 
  rtx align = operands[3];
1475 
  rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1476 
  rtx loop_label, end_label, mem, cr0, cond;
1477 
  if (search_char != const0_rtx
1478 
      || GET_CODE (align) != CONST_INT
1479 
      || INTVAL (align) < 8)
1480 
        FAIL;
1481 
  word1 = gen_reg_rtx (SImode);
1482 
  word2 = gen_reg_rtx (SImode);
1483 
  scratch_dlmzb = gen_reg_rtx (SImode);
1484 
  scratch_string = gen_reg_rtx (Pmode);
1485 
  loop_label = gen_label_rtx ();
1486 
  end_label = gen_label_rtx ();
1487 
  addr = force_reg (Pmode, XEXP (src, 0));
1488 
  emit_move_insn (scratch_string, addr);
1489 
  emit_label (loop_label);
1490 
  mem = change_address (src, SImode, scratch_string);
1491 
  emit_move_insn (word1, mem);
1492 
  emit_move_insn (word2, adjust_address (mem, SImode, 4));
1493 
  cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1494 
  emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1495 
  cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1496 
  emit_jump_insn (gen_rtx_SET (VOIDmode,
1497 
                               pc_rtx,
1498 
                               gen_rtx_IF_THEN_ELSE (VOIDmode,
1499 
                                                     cond,
1500 
                                                     gen_rtx_LABEL_REF
1501 
                                                       (VOIDmode,
1502 
                                                        end_label),
1503 
                                                     pc_rtx)));
1504 
  emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1505 
  emit_jump_insn (gen_rtx_SET (VOIDmode,
1506 
                               pc_rtx,
1507 
                               gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1508 
  emit_barrier ();
1509 
  emit_label (end_label);
1510 
  emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1511 
  emit_insn (gen_subsi3 (result, scratch_string, addr));
1512 
  emit_insn (gen_subsi3 (result, result, const1_rtx));
1513 
  DONE;
1514 
})
1515 
 
1516 
(define_split
1517 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1518 
        (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1519 
                    (const_int 0)))
1520 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1521 
        (sign_extend:SI (match_dup 1)))]
1522 
  "reload_completed"
1523 
  [(set (match_dup 0)
1524 
        (sign_extend:SI (match_dup 1)))
1525 
   (set (match_dup 2)
1526 
        (compare:CC (match_dup 0)
1527 
                    (const_int 0)))]
1528 
  "")
1529 
 
1530 
;; Fixed-point arithmetic insns.
1531 
 
1532 
(define_expand "add3"
1533 
  [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1534 
        (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1535 
                  (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1536 
  ""
1537 
{
1538 
  if (mode == DImode && ! TARGET_POWERPC64)
1539 
    {
1540 
      if (non_short_cint_operand (operands[2], DImode))
1541 
        FAIL;
1542 
    }
1543 
  else if (GET_CODE (operands[2]) == CONST_INT
1544 
           && ! add_operand (operands[2], mode))
1545 
    {
1546 
      rtx tmp = ((!can_create_pseudo_p ()
1547 
                  || rtx_equal_p (operands[0], operands[1]))
1548 
                 ? operands[0] : gen_reg_rtx (mode));
1549 
 
1550 
      HOST_WIDE_INT val = INTVAL (operands[2]);
1551 
      HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1552 
      HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode);
1553 
 
1554 
      if (mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1555 
        FAIL;
1556 
 
1557 
      /* The ordering here is important for the prolog expander.
1558 
         When space is allocated from the stack, adding 'low' first may
1559 
         produce a temporary deallocation (which would be bad).  */
1560 
      emit_insn (gen_add3 (tmp, operands[1], GEN_INT (rest)));
1561 
      emit_insn (gen_add3 (operands[0], tmp, GEN_INT (low)));
1562 
      DONE;
1563 
    }
1564 
})
1565 
 
1566 
;; Discourage ai/addic because of carry but provide it in an alternative
1567 
;; allowing register zero as source.
1568 
(define_insn "*add3_internal1"
1569 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1570 
        (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1571 
                  (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1572 
  "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1573 
  "@
1574 
   {cax|add} %0,%1,%2
1575 
   {cal %0,%2(%1)|addi %0,%1,%2}
1576 
   {ai|addic} %0,%1,%2
1577 
   {cau|addis} %0,%1,%v2"
1578 
  [(set_attr "length" "4,4,4,4")])
1579 
 
1580 
(define_insn "addsi3_high"
1581 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1582 
        (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1583 
                 (high:SI (match_operand 2 "" ""))))]
1584 
  "TARGET_MACHO && !TARGET_64BIT"
1585 
  "{cau|addis} %0,%1,ha16(%2)"
1586 
  [(set_attr "length" "4")])
1587 
 
1588 
(define_insn "*add3_internal2"
1589 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1590 
        (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1591 
                            (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1592 
                    (const_int 0)))
1593 
   (clobber (match_scratch:P 3 "=r,r,r,r"))]
1594 
  ""
1595 
  "@
1596 
   {cax.|add.} %3,%1,%2
1597 
   {ai.|addic.} %3,%1,%2
1598 
   #
1599 
   #"
1600 
  [(set_attr "type" "fast_compare,compare,compare,compare")
1601 
   (set_attr "length" "4,4,8,8")])
1602 
 
1603 
(define_split
1604 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1605 
        (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1606 
                              (match_operand:GPR 2 "reg_or_short_operand" ""))
1607 
                    (const_int 0)))
1608 
   (clobber (match_scratch:GPR 3 ""))]
1609 
  "reload_completed"
1610 
  [(set (match_dup 3)
1611 
        (plus:GPR (match_dup 1)
1612 
                 (match_dup 2)))
1613 
   (set (match_dup 0)
1614 
        (compare:CC (match_dup 3)
1615 
                    (const_int 0)))]
1616 
  "")
1617 
 
1618 
(define_insn "*add3_internal3"
1619 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1620 
        (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1621 
                            (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1622 
                    (const_int 0)))
1623 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1624 
        (plus:P (match_dup 1)
1625 
                (match_dup 2)))]
1626 
  ""
1627 
  "@
1628 
   {cax.|add.} %0,%1,%2
1629 
   {ai.|addic.} %0,%1,%2
1630 
   #
1631 
   #"
1632 
  [(set_attr "type" "fast_compare,compare,compare,compare")
1633 
   (set_attr "length" "4,4,8,8")])
1634 
 
1635 
(define_split
1636 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1637 
        (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1638 
                            (match_operand:P 2 "reg_or_short_operand" ""))
1639 
                    (const_int 0)))
1640 
   (set (match_operand:P 0 "gpc_reg_operand" "")
1641 
        (plus:P (match_dup 1) (match_dup 2)))]
1642 
  "reload_completed"
1643 
  [(set (match_dup 0)
1644 
        (plus:P (match_dup 1)
1645 
                (match_dup 2)))
1646 
   (set (match_dup 3)
1647 
        (compare:CC (match_dup 0)
1648 
                    (const_int 0)))]
1649 
  "")
1650 
 
1651 
;; Split an add that we can't do in one insn into two insns, each of which
1652 
;; does one 16-bit part.  This is used by combine.  Note that the low-order
1653 
;; add should be last in case the result gets used in an address.
1654 
 
1655 
(define_split
1656 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1657 
        (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1658 
                  (match_operand:GPR 2 "non_add_cint_operand" "")))]
1659 
  ""
1660 
  [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1661 
   (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1662 
{
1663 
  HOST_WIDE_INT val = INTVAL (operands[2]);
1664 
  HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1665 
  HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode);
1666 
 
1667 
  operands[4] = GEN_INT (low);
1668 
  if (mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1669 
    operands[3] = GEN_INT (rest);
1670 
  else if (can_create_pseudo_p ())
1671 
    {
1672 
      operands[3] = gen_reg_rtx (DImode);
1673 
      emit_move_insn (operands[3], operands[2]);
1674 
      emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1675 
      DONE;
1676 
    }
1677 
  else
1678 
    FAIL;
1679 
})
1680 
 
1681 
(define_insn "one_cmpl2"
1682 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1683 
        (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1684 
  ""
1685 
  "nor %0,%1,%1")
1686 
 
1687 
(define_insn ""
1688 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1689 
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1690 
                    (const_int 0)))
1691 
   (clobber (match_scratch:P 2 "=r,r"))]
1692 
  ""
1693 
  "@
1694 
   nor. %2,%1,%1
1695 
   #"
1696 
  [(set_attr "type" "fast_compare,compare")
1697 
   (set_attr "length" "4,8")])
1698 
 
1699 
(define_split
1700 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1701 
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1702 
                    (const_int 0)))
1703 
   (clobber (match_scratch:P 2 ""))]
1704 
  "reload_completed"
1705 
  [(set (match_dup 2)
1706 
        (not:P (match_dup 1)))
1707 
   (set (match_dup 0)
1708 
        (compare:CC (match_dup 2)
1709 
                    (const_int 0)))]
1710 
  "")
1711 
 
1712 
(define_insn ""
1713 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1714 
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1715 
                    (const_int 0)))
1716 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1717 
        (not:P (match_dup 1)))]
1718 
  ""
1719 
  "@
1720 
   nor. %0,%1,%1
1721 
   #"
1722 
  [(set_attr "type" "fast_compare,compare")
1723 
   (set_attr "length" "4,8")])
1724 
 
1725 
(define_split
1726 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1727 
        (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1728 
                    (const_int 0)))
1729 
   (set (match_operand:P 0 "gpc_reg_operand" "")
1730 
        (not:P (match_dup 1)))]
1731 
  "reload_completed"
1732 
  [(set (match_dup 0)
1733 
        (not:P (match_dup 1)))
1734 
   (set (match_dup 2)
1735 
        (compare:CC (match_dup 0)
1736 
                    (const_int 0)))]
1737 
  "")
1738 
 
1739 
(define_insn ""
1740 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1741 
        (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1742 
                  (match_operand:SI 2 "gpc_reg_operand" "r")))]
1743 
  "! TARGET_POWERPC"
1744 
  "{sf%I1|subf%I1c} %0,%2,%1")
1745 
 
1746 
(define_insn ""
1747 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1748 
        (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1749 
                   (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1750 
  "TARGET_POWERPC"
1751 
  "@
1752 
   subf %0,%2,%1
1753 
   subfic %0,%2,%1")
1754 
 
1755 
(define_insn ""
1756 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1757 
        (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1758 
                              (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1759 
                    (const_int 0)))
1760 
   (clobber (match_scratch:SI 3 "=r,r"))]
1761 
  "! TARGET_POWERPC"
1762 
  "@
1763 
   {sf.|subfc.} %3,%2,%1
1764 
   #"
1765 
  [(set_attr "type" "compare")
1766 
   (set_attr "length" "4,8")])
1767 
 
1768 
(define_insn ""
1769 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1770 
        (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1771 
                             (match_operand:P 2 "gpc_reg_operand" "r,r"))
1772 
                    (const_int 0)))
1773 
   (clobber (match_scratch:P 3 "=r,r"))]
1774 
  "TARGET_POWERPC"
1775 
  "@
1776 
   subf. %3,%2,%1
1777 
   #"
1778 
  [(set_attr "type" "fast_compare")
1779 
   (set_attr "length" "4,8")])
1780 
 
1781 
(define_split
1782 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1783 
        (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1784 
                             (match_operand:P 2 "gpc_reg_operand" ""))
1785 
                    (const_int 0)))
1786 
   (clobber (match_scratch:P 3 ""))]
1787 
  "reload_completed"
1788 
  [(set (match_dup 3)
1789 
        (minus:P (match_dup 1)
1790 
                  (match_dup 2)))
1791 
   (set (match_dup 0)
1792 
        (compare:CC (match_dup 3)
1793 
                    (const_int 0)))]
1794 
  "")
1795 
 
1796 
(define_insn ""
1797 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1798 
        (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1799 
                              (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1800 
                    (const_int 0)))
1801 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1802 
        (minus:SI (match_dup 1) (match_dup 2)))]
1803 
  "! TARGET_POWERPC"
1804 
  "@
1805 
   {sf.|subfc.} %0,%2,%1
1806 
   #"
1807 
  [(set_attr "type" "compare")
1808 
   (set_attr "length" "4,8")])
1809 
 
1810 
(define_insn ""
1811 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1812 
        (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1813 
                             (match_operand:P 2 "gpc_reg_operand" "r,r"))
1814 
                    (const_int 0)))
1815 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1816 
        (minus:P (match_dup 1)
1817 
                  (match_dup 2)))]
1818 
  "TARGET_POWERPC"
1819 
  "@
1820 
   subf. %0,%2,%1
1821 
   #"
1822 
  [(set_attr "type" "fast_compare")
1823 
   (set_attr "length" "4,8")])
1824 
 
1825 
(define_split
1826 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1827 
        (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1828 
                             (match_operand:P 2 "gpc_reg_operand" ""))
1829 
                    (const_int 0)))
1830 
   (set (match_operand:P 0 "gpc_reg_operand" "")
1831 
        (minus:P (match_dup 1)
1832 
                  (match_dup 2)))]
1833 
  "reload_completed"
1834 
  [(set (match_dup 0)
1835 
        (minus:P (match_dup 1)
1836 
                  (match_dup 2)))
1837 
   (set (match_dup 3)
1838 
        (compare:CC (match_dup 0)
1839 
                    (const_int 0)))]
1840 
  "")
1841 
 
1842 
(define_expand "sub3"
1843 
  [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1844 
        (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1845 
                   (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1846 
  ""
1847 
  "
1848 
{
1849 
  if (GET_CODE (operands[2]) == CONST_INT)
1850 
    {
1851 
      emit_insn (gen_add3 (operands[0], operands[1],
1852 
                                 negate_rtx (mode, operands[2])));
1853 
      DONE;
1854 
    }
1855 
}")
1856 
 
1857 
;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1858 
;; instruction and some auxiliary computations.  Then we just have a single
1859 
;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1860 
;; combine.
1861 
 
1862 
(define_expand "sminsi3"
1863 
  [(set (match_dup 3)
1864 
        (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1865 
                                (match_operand:SI 2 "reg_or_short_operand" ""))
1866 
                         (const_int 0)
1867 
                         (minus:SI (match_dup 2) (match_dup 1))))
1868 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1869 
        (minus:SI (match_dup 2) (match_dup 3)))]
1870 
  "TARGET_POWER || TARGET_ISEL"
1871 
  "
1872 
{
1873 
  if (TARGET_ISEL)
1874 
    {
1875 
      operands[2] = force_reg (SImode, operands[2]);
1876 
      rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1877 
      DONE;
1878 
    }
1879 
 
1880 
  operands[3] = gen_reg_rtx (SImode);
1881 
}")
1882 
 
1883 
(define_split
1884 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
1885 
        (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1886 
                 (match_operand:SI 2 "reg_or_short_operand" "")))
1887 
   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1888 
  "TARGET_POWER"
1889 
  [(set (match_dup 3)
1890 
        (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1891 
                         (const_int 0)
1892 
                         (minus:SI (match_dup 2) (match_dup 1))))
1893 
   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1894 
  "")
1895 
 
1896 
(define_expand "smaxsi3"
1897 
  [(set (match_dup 3)
1898 
        (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1899 
                                (match_operand:SI 2 "reg_or_short_operand" ""))
1900 
                         (const_int 0)
1901 
                         (minus:SI (match_dup 2) (match_dup 1))))
1902 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1903 
        (plus:SI (match_dup 3) (match_dup 1)))]
1904 
  "TARGET_POWER || TARGET_ISEL"
1905 
  "
1906 
{
1907 
  if (TARGET_ISEL)
1908 
    {
1909 
      operands[2] = force_reg (SImode, operands[2]);
1910 
      rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1911 
      DONE;
1912 
    }
1913 
  operands[3] = gen_reg_rtx (SImode);
1914 
}")
1915 
 
1916 
(define_split
1917 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
1918 
        (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1919 
                 (match_operand:SI 2 "reg_or_short_operand" "")))
1920 
   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1921 
  "TARGET_POWER"
1922 
  [(set (match_dup 3)
1923 
        (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1924 
                         (const_int 0)
1925 
                         (minus:SI (match_dup 2) (match_dup 1))))
1926 
   (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1927 
  "")
1928 
 
1929 
(define_expand "uminsi3"
1930 
  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1931 
                              (match_dup 5)))
1932 
   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1933 
                              (match_dup 5)))
1934 
   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1935 
                                       (const_int 0)
1936 
                                       (minus:SI (match_dup 4) (match_dup 3))))
1937 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1938 
        (minus:SI (match_dup 2) (match_dup 3)))]
1939 
  "TARGET_POWER || TARGET_ISEL"
1940 
  "
1941 
{
1942 
  if (TARGET_ISEL)
1943 
    {
1944 
      rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1945 
      DONE;
1946 
    }
1947 
  operands[3] = gen_reg_rtx (SImode);
1948 
  operands[4] = gen_reg_rtx (SImode);
1949 
  operands[5] = GEN_INT (-2147483647 - 1);
1950 
}")
1951 
 
1952 
(define_expand "umaxsi3"
1953 
  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1954 
                              (match_dup 5)))
1955 
   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1956 
                              (match_dup 5)))
1957 
   (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1958 
                                       (const_int 0)
1959 
                                       (minus:SI (match_dup 4) (match_dup 3))))
1960 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
1961 
        (plus:SI (match_dup 3) (match_dup 1)))]
1962 
  "TARGET_POWER || TARGET_ISEL"
1963 
  "
1964 
{
1965 
  if (TARGET_ISEL)
1966 
    {
1967 
      rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1968 
      DONE;
1969 
    }
1970 
  operands[3] = gen_reg_rtx (SImode);
1971 
  operands[4] = gen_reg_rtx (SImode);
1972 
  operands[5] = GEN_INT (-2147483647 - 1);
1973 
}")
1974 
 
1975 
(define_insn ""
1976 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1977 
        (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1978 
                             (match_operand:SI 2 "reg_or_short_operand" "rI"))
1979 
                         (const_int 0)
1980 
                         (minus:SI (match_dup 2) (match_dup 1))))]
1981 
  "TARGET_POWER"
1982 
  "doz%I2 %0,%1,%2")
1983 
 
1984 
(define_insn ""
1985 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1986 
        (compare:CC
1987 
         (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1988 
                              (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1989 
                          (const_int 0)
1990 
                          (minus:SI (match_dup 2) (match_dup 1)))
1991 
         (const_int 0)))
1992 
   (clobber (match_scratch:SI 3 "=r,r"))]
1993 
  "TARGET_POWER"
1994 
  "@
1995 
   doz%I2. %3,%1,%2
1996 
   #"
1997 
  [(set_attr "type" "delayed_compare")
1998 
   (set_attr "length" "4,8")])
1999 
 
2000 
(define_split
2001 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2002 
        (compare:CC
2003 
         (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2004 
                              (match_operand:SI 2 "reg_or_short_operand" ""))
2005 
                          (const_int 0)
2006 
                          (minus:SI (match_dup 2) (match_dup 1)))
2007 
         (const_int 0)))
2008 
   (clobber (match_scratch:SI 3 ""))]
2009 
  "TARGET_POWER && reload_completed"
2010 
  [(set (match_dup 3)
2011 
        (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2012 
                          (const_int 0)
2013 
                          (minus:SI (match_dup 2) (match_dup 1))))
2014 
   (set (match_dup 0)
2015 
        (compare:CC (match_dup 3)
2016 
                    (const_int 0)))]
2017 
  "")
2018 
 
2019 
(define_insn ""
2020 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2021 
        (compare:CC
2022 
         (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2023 
                              (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2024 
                          (const_int 0)
2025 
                          (minus:SI (match_dup 2) (match_dup 1)))
2026 
         (const_int 0)))
2027 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2028 
        (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2029 
                         (const_int 0)
2030 
                         (minus:SI (match_dup 2) (match_dup 1))))]
2031 
  "TARGET_POWER"
2032 
  "@
2033 
   doz%I2. %0,%1,%2
2034 
   #"
2035 
  [(set_attr "type" "delayed_compare")
2036 
   (set_attr "length" "4,8")])
2037 
 
2038 
(define_split
2039 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2040 
        (compare:CC
2041 
         (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2042 
                              (match_operand:SI 2 "reg_or_short_operand" ""))
2043 
                          (const_int 0)
2044 
                          (minus:SI (match_dup 2) (match_dup 1)))
2045 
         (const_int 0)))
2046 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
2047 
        (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2048 
                         (const_int 0)
2049 
                         (minus:SI (match_dup 2) (match_dup 1))))]
2050 
  "TARGET_POWER && reload_completed"
2051 
  [(set (match_dup 0)
2052 
        (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2053 
                         (const_int 0)
2054 
                         (minus:SI (match_dup 2) (match_dup 1))))
2055 
   (set (match_dup 3)
2056 
        (compare:CC (match_dup 0)
2057 
                    (const_int 0)))]
2058 
  "")
2059 
 
2060 
;; We don't need abs with condition code because such comparisons should
2061 
;; never be done.
2062 
(define_expand "abssi2"
2063 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
2064 
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2065 
  ""
2066 
  "
2067 
{
2068 
  if (TARGET_ISEL)
2069 
    {
2070 
      emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2071 
      DONE;
2072 
    }
2073 
  else if (! TARGET_POWER)
2074 
    {
2075 
      emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2076 
      DONE;
2077 
    }
2078 
}")
2079 
 
2080 
(define_insn "*abssi2_power"
2081 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2082 
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2083 
  "TARGET_POWER"
2084 
  "abs %0,%1")
2085 
 
2086 
(define_insn_and_split "abs2_isel"
2087 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2088 
        (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2089 
   (clobber (match_scratch:GPR 2 "=&b"))
2090 
   (clobber (match_scratch:CC 3 "=y"))]
2091 
  "TARGET_ISEL"
2092 
  "#"
2093 
  "&& reload_completed"
2094 
  [(set (match_dup 2) (neg:GPR (match_dup 1)))
2095 
   (set (match_dup 3)
2096 
        (compare:CC (match_dup 1)
2097 
                    (const_int 0)))
2098 
   (set (match_dup 0)
2099 
        (if_then_else:GPR (ge (match_dup 3)
2100 
                              (const_int 0))
2101 
                          (match_dup 1)
2102 
                          (match_dup 2)))]
2103 
  "")
2104 
 
2105 
(define_insn_and_split "nabs2_isel"
2106 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2107 
        (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2108 
   (clobber (match_scratch:GPR 2 "=&b"))
2109 
   (clobber (match_scratch:CC 3 "=y"))]
2110 
  "TARGET_ISEL"
2111 
  "#"
2112 
  "&& reload_completed"
2113 
  [(set (match_dup 2) (neg:GPR (match_dup 1)))
2114 
   (set (match_dup 3)
2115 
        (compare:CC (match_dup 1)
2116 
                    (const_int 0)))
2117 
   (set (match_dup 0)
2118 
        (if_then_else:GPR (ge (match_dup 3)
2119 
                              (const_int 0))
2120 
                          (match_dup 2)
2121 
                          (match_dup 1)))]
2122 
  "")
2123 
 
2124 
(define_insn_and_split "abssi2_nopower"
2125 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2126 
        (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2127 
   (clobber (match_scratch:SI 2 "=&r,&r"))]
2128 
  "! TARGET_POWER && ! TARGET_ISEL"
2129 
  "#"
2130 
  "&& reload_completed"
2131 
  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2132 
   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2133 
   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2134 
  "")
2135 
 
2136 
(define_insn "*nabs_power"
2137 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2138 
        (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2139 
  "TARGET_POWER"
2140 
  "nabs %0,%1")
2141 
 
2142 
(define_insn_and_split "*nabs_nopower"
2143 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2144 
        (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2145 
   (clobber (match_scratch:SI 2 "=&r,&r"))]
2146 
  "! TARGET_POWER"
2147 
  "#"
2148 
  "&& reload_completed"
2149 
  [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2150 
   (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2151 
   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2152 
  "")
2153 
 
2154 
(define_expand "neg2"
2155 
  [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2156 
        (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2157 
  ""
2158 
  "")
2159 
 
2160 
(define_insn "*neg2_internal"
2161 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2162 
        (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2163 
  ""
2164 
  "neg %0,%1")
2165 
 
2166 
(define_insn ""
2167 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2168 
        (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2169 
                    (const_int 0)))
2170 
   (clobber (match_scratch:P 2 "=r,r"))]
2171 
  ""
2172 
  "@
2173 
   neg. %2,%1
2174 
   #"
2175 
  [(set_attr "type" "fast_compare")
2176 
   (set_attr "length" "4,8")])
2177 
 
2178 
(define_split
2179 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2180 
        (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2181 
                    (const_int 0)))
2182 
   (clobber (match_scratch:P 2 ""))]
2183 
  "reload_completed"
2184 
  [(set (match_dup 2)
2185 
        (neg:P (match_dup 1)))
2186 
   (set (match_dup 0)
2187 
        (compare:CC (match_dup 2)
2188 
                    (const_int 0)))]
2189 
  "")
2190 
 
2191 
(define_insn ""
2192 
  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2193 
        (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2194 
                    (const_int 0)))
2195 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2196 
        (neg:P (match_dup 1)))]
2197 
  ""
2198 
  "@
2199 
   neg. %0,%1
2200 
   #"
2201 
  [(set_attr "type" "fast_compare")
2202 
   (set_attr "length" "4,8")])
2203 
 
2204 
(define_split
2205 
  [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2206 
        (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2207 
                    (const_int 0)))
2208 
   (set (match_operand:P 0 "gpc_reg_operand" "")
2209 
        (neg:P (match_dup 1)))]
2210 
  "reload_completed"
2211 
  [(set (match_dup 0)
2212 
        (neg:P (match_dup 1)))
2213 
   (set (match_dup 2)
2214 
        (compare:CC (match_dup 0)
2215 
                    (const_int 0)))]
2216 
  "")
2217 
 
2218 
(define_insn "clz2"
2219 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2220 
        (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2221 
  ""
2222 
  "{cntlz|cntlz} %0,%1"
2223 
  [(set_attr "type" "cntlz")])
2224 
 
2225 
(define_expand "ctz2"
2226 
  [(set (match_dup 2)
2227 
        (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2228 
   (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2229 
                                          (match_dup 2)))
2230 
              (clobber (scratch:CC))])
2231 
   (set (match_dup 4) (clz:GPR (match_dup 3)))
2232 
   (set (match_operand:GPR 0 "gpc_reg_operand" "")
2233 
        (minus:GPR (match_dup 5) (match_dup 4)))]
2234 
  ""
2235 
  {
2236 
     operands[2] = gen_reg_rtx (mode);
2237 
     operands[3] = gen_reg_rtx (mode);
2238 
     operands[4] = gen_reg_rtx (mode);
2239 
     operands[5] = GEN_INT (GET_MODE_BITSIZE (mode) - 1);
2240 
  })
2241 
 
2242 
(define_expand "ffs2"
2243 
  [(set (match_dup 2)
2244 
        (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2245 
   (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2246 
                                          (match_dup 2)))
2247 
              (clobber (scratch:CC))])
2248 
   (set (match_dup 4) (clz:GPR (match_dup 3)))
2249 
   (set (match_operand:GPR 0 "gpc_reg_operand" "")
2250 
        (minus:GPR (match_dup 5) (match_dup 4)))]
2251 
  ""
2252 
  {
2253 
     operands[2] = gen_reg_rtx (mode);
2254 
     operands[3] = gen_reg_rtx (mode);
2255 
     operands[4] = gen_reg_rtx (mode);
2256 
     operands[5] = GEN_INT (GET_MODE_BITSIZE (mode));
2257 
  })
2258 
 
2259 
(define_insn "popcntb2"
2260 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2261 
        (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2262 
                     UNSPEC_POPCNTB))]
2263 
  "TARGET_POPCNTB"
2264 
  "popcntb %0,%1")
2265 
 
2266 
(define_insn "popcntwsi2"
2267 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2268 
        (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2269 
  "TARGET_POPCNTD"
2270 
  "popcntw %0,%1")
2271 
 
2272 
(define_insn "popcntddi2"
2273 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2274 
        (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2275 
  "TARGET_POPCNTD && TARGET_POWERPC64"
2276 
  "popcntd %0,%1")
2277 
 
2278 
(define_expand "popcount2"
2279 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2280 
        (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2281 
  "TARGET_POPCNTB || TARGET_POPCNTD"
2282 
  {
2283 
    rs6000_emit_popcount (operands[0], operands[1]);
2284 
    DONE;
2285 
  })
2286 
 
2287 
(define_expand "parity2"
2288 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2289 
        (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2290 
  "TARGET_POPCNTB"
2291 
  {
2292 
    rs6000_emit_parity (operands[0], operands[1]);
2293 
    DONE;
2294 
  })
2295 
 
2296 
;; Since the hardware zeros the upper part of the register, save generating the
2297 
;; AND immediate if we are converting to unsigned
2298 
(define_insn "*bswaphi2_extenddi"
2299 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2300 
        (zero_extend:DI
2301 
         (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2302 
  "TARGET_POWERPC64"
2303 
  "lhbrx %0,%y1"
2304 
  [(set_attr "length" "4")
2305 
   (set_attr "type" "load")])
2306 
 
2307 
(define_insn "*bswaphi2_extendsi"
2308 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2309 
        (zero_extend:SI
2310 
         (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2311 
  "TARGET_POWERPC"
2312 
  "lhbrx %0,%y1"
2313 
  [(set_attr "length" "4")
2314 
   (set_attr "type" "load")])
2315 
 
2316 
(define_expand "bswaphi2"
2317 
  [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2318 
                   (bswap:HI
2319 
                    (match_operand:HI 1 "reg_or_mem_operand" "")))
2320 
              (clobber (match_scratch:SI 2 ""))])]
2321 
  ""
2322 
{
2323 
  if (!REG_P (operands[0]) && !REG_P (operands[1]))
2324 
    operands[1] = force_reg (HImode, operands[1]);
2325 
})
2326 
 
2327 
(define_insn "bswaphi2_internal"
2328 
  [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2329 
        (bswap:HI
2330 
         (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2331 
   (clobber (match_scratch:SI 2 "=X,X,&r"))]
2332 
  "TARGET_POWERPC"
2333 
  "@
2334 
   lhbrx %0,%y1
2335 
   sthbrx %1,%y0
2336 
   #"
2337 
  [(set_attr "length" "4,4,12")
2338 
   (set_attr "type" "load,store,*")])
2339 
 
2340 
(define_split
2341 
  [(set (match_operand:HI 0 "gpc_reg_operand" "")
2342 
        (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2343 
   (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2344 
  "TARGET_POWERPC && reload_completed"
2345 
  [(set (match_dup 3)
2346 
        (zero_extract:SI (match_dup 4)
2347 
                         (const_int 8)
2348 
                         (const_int 16)))
2349 
   (set (match_dup 2)
2350 
        (and:SI (ashift:SI (match_dup 4)
2351 
                           (const_int 8))
2352 
                (const_int 65280)))             ;; 0xff00
2353 
   (set (match_dup 3)
2354 
        (ior:SI (match_dup 3)
2355 
                (match_dup 2)))]
2356 
  "
2357 
{
2358 
  operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2359 
  operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2360 
}")
2361 
 
2362 
(define_insn "*bswapsi2_extenddi"
2363 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2364 
        (zero_extend:DI
2365 
         (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2366 
  "TARGET_POWERPC64"
2367 
  "lwbrx %0,%y1"
2368 
  [(set_attr "length" "4")
2369 
   (set_attr "type" "load")])
2370 
 
2371 
(define_expand "bswapsi2"
2372 
  [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2373 
        (bswap:SI
2374 
         (match_operand:SI 1 "reg_or_mem_operand" "")))]
2375 
  ""
2376 
{
2377 
  if (!REG_P (operands[0]) && !REG_P (operands[1]))
2378 
    operands[1] = force_reg (SImode, operands[1]);
2379 
})
2380 
 
2381 
(define_insn "*bswapsi2_internal"
2382 
  [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2383 
        (bswap:SI
2384 
         (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2385 
  ""
2386 
  "@
2387 
   {lbrx|lwbrx} %0,%y1
2388 
   {stbrx|stwbrx} %1,%y0
2389 
   #"
2390 
  [(set_attr "length" "4,4,12")
2391 
   (set_attr "type" "load,store,*")])
2392 
 
2393 
(define_split
2394 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
2395 
        (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2396 
  "reload_completed"
2397 
  [(set (match_dup 0)
2398 
        (rotate:SI (match_dup 1) (const_int 8)))
2399 
   (set (zero_extract:SI (match_dup 0)
2400 
                         (const_int 8)
2401 
                         (const_int 0))
2402 
        (match_dup 1))
2403 
   (set (zero_extract:SI (match_dup 0)
2404 
                         (const_int 8)
2405 
                         (const_int 16))
2406 
        (rotate:SI (match_dup 1)
2407 
                   (const_int 16)))]
2408 
  "")
2409 
 
2410 
(define_expand "bswapdi2"
2411 
  [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2412 
                   (bswap:DI
2413 
                    (match_operand:DI 1 "reg_or_mem_operand" "")))
2414 
              (clobber (match_scratch:DI 2 ""))
2415 
              (clobber (match_scratch:DI 3 ""))
2416 
              (clobber (match_scratch:DI 4 ""))])]
2417 
  ""
2418 
{
2419 
  if (!REG_P (operands[0]) && !REG_P (operands[1]))
2420 
    operands[1] = force_reg (DImode, operands[1]);
2421 
 
2422 
  if (!TARGET_POWERPC64)
2423 
    {
2424 
      /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2425 
         that uses 64-bit registers needs the same scratch registers as 64-bit
2426 
         mode.  */
2427 
      emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2428 
      DONE;
2429 
    }
2430 
})
2431 
 
2432 
;; Power7/cell has ldbrx/stdbrx, so use it directly
2433 
(define_insn "*bswapdi2_ldbrx"
2434 
  [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2435 
        (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2436 
   (clobber (match_scratch:DI 2 "=X,X,&r"))
2437 
   (clobber (match_scratch:DI 3 "=X,X,&r"))
2438 
   (clobber (match_scratch:DI 4 "=X,X,&r"))]
2439 
  "TARGET_POWERPC64 && TARGET_LDBRX
2440 
   && (REG_P (operands[0]) || REG_P (operands[1]))"
2441 
  "@
2442 
   ldbrx %0,%y1
2443 
   stdbrx %1,%y0
2444 
   #"
2445 
  [(set_attr "length" "4,4,36")
2446 
   (set_attr "type" "load,store,*")])
2447 
 
2448 
;; Non-power7/cell, fall back to use lwbrx/stwbrx
2449 
(define_insn "*bswapdi2_64bit"
2450 
  [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2451 
        (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2452 
   (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2453 
   (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2454 
   (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2455 
  "TARGET_POWERPC64 && !TARGET_LDBRX
2456 
   && (REG_P (operands[0]) || REG_P (operands[1]))"
2457 
  "#"
2458 
  [(set_attr "length" "16,12,36")])
2459 
 
2460 
(define_split
2461 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
2462 
        (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2463 
   (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2464 
   (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2465 
   (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2466 
  "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2467 
  [(const_int 0)]
2468 
  "
2469 
{
2470 
  rtx dest   = operands[0];
2471 
  rtx src    = operands[1];
2472 
  rtx op2    = operands[2];
2473 
  rtx op3    = operands[3];
2474 
  rtx op4    = operands[4];
2475 
  rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2476 
  rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2477 
  rtx addr1;
2478 
  rtx addr2;
2479 
  rtx word_high;
2480 
  rtx word_low;
2481 
 
2482 
  addr1 = XEXP (src, 0);
2483 
  if (GET_CODE (addr1) == PLUS)
2484 
    {
2485 
      emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2486 
      addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2487 
    }
2488 
  else
2489 
    {
2490 
      emit_move_insn (op2, GEN_INT (4));
2491 
      addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2492 
    }
2493 
 
2494 
  if (BYTES_BIG_ENDIAN)
2495 
    {
2496 
      word_high = change_address (src, SImode, addr1);
2497 
      word_low  = change_address (src, SImode, addr2);
2498 
    }
2499 
  else
2500 
    {
2501 
      word_high = change_address (src, SImode, addr2);
2502 
      word_low  = change_address (src, SImode, addr1);
2503 
    }
2504 
 
2505 
  emit_insn (gen_bswapsi2 (op3_32, word_low));
2506 
  emit_insn (gen_bswapsi2 (op4_32, word_high));
2507 
  emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2508 
  emit_insn (gen_iordi3 (dest, dest, op4));
2509 
}")
2510 
 
2511 
(define_split
2512 
  [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2513 
        (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2514 
   (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2515 
   (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2516 
   (clobber (match_operand:DI 4 "" ""))]
2517 
  "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2518 
  [(const_int 0)]
2519 
  "
2520 
{
2521 
  rtx dest   = operands[0];
2522 
  rtx src    = operands[1];
2523 
  rtx op2    = operands[2];
2524 
  rtx op3    = operands[3];
2525 
  rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2526 
  rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2527 
  rtx addr1;
2528 
  rtx addr2;
2529 
  rtx word_high;
2530 
  rtx word_low;
2531 
 
2532 
  addr1 = XEXP (dest, 0);
2533 
  if (GET_CODE (addr1) == PLUS)
2534 
    {
2535 
      emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2536 
      addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2537 
    }
2538 
  else
2539 
    {
2540 
      emit_move_insn (op2, GEN_INT (4));
2541 
      addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2542 
    }
2543 
 
2544 
  emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2545 
  if (BYTES_BIG_ENDIAN)
2546 
    {
2547 
      word_high = change_address (dest, SImode, addr1);
2548 
      word_low  = change_address (dest, SImode, addr2);
2549 
      emit_insn (gen_bswapsi2 (word_high, src_si));
2550 
      emit_insn (gen_bswapsi2 (word_low, op3_si));
2551 
    }
2552 
  else
2553 
    {
2554 
      word_high = change_address (dest, SImode, addr2);
2555 
      word_low  = change_address (dest, SImode, addr1);
2556 
      emit_insn (gen_bswapsi2 (word_low, src_si));
2557 
      emit_insn (gen_bswapsi2 (word_high, op3_si));
2558 
    }
2559 
}")
2560 
 
2561 
(define_split
2562 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
2563 
        (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2564 
   (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2565 
   (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2566 
   (clobber (match_operand:DI 4 "" ""))]
2567 
  "TARGET_POWERPC64 && reload_completed"
2568 
  [(const_int 0)]
2569 
  "
2570 
{
2571 
  rtx dest    = operands[0];
2572 
  rtx src     = operands[1];
2573 
  rtx op2     = operands[2];
2574 
  rtx op3     = operands[3];
2575 
  rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2576 
  rtx src_si  = simplify_gen_subreg (SImode, src, DImode, 4);
2577 
  rtx op2_si  = simplify_gen_subreg (SImode, op2, DImode, 4);
2578 
  rtx op3_si  = simplify_gen_subreg (SImode, op3, DImode, 4);
2579 
 
2580 
  emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2581 
  emit_insn (gen_bswapsi2 (dest_si, src_si));
2582 
  emit_insn (gen_bswapsi2 (op3_si, op2_si));
2583 
  emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2584 
  emit_insn (gen_iordi3 (dest, dest, op3));
2585 
}")
2586 
 
2587 
(define_insn "bswapdi2_32bit"
2588 
  [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2589 
        (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2590 
   (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2591 
  "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2592 
  "#"
2593 
  [(set_attr "length" "16,12,36")])
2594 
 
2595 
(define_split
2596 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
2597 
        (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2598 
   (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2599 
  "!TARGET_POWERPC64 && reload_completed"
2600 
  [(const_int 0)]
2601 
  "
2602 
{
2603 
  rtx dest   = operands[0];
2604 
  rtx src    = operands[1];
2605 
  rtx op2    = operands[2];
2606 
  rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2607 
  rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2608 
  rtx addr1;
2609 
  rtx addr2;
2610 
  rtx word_high;
2611 
  rtx word_low;
2612 
 
2613 
  addr1 = XEXP (src, 0);
2614 
  if (GET_CODE (addr1) == PLUS)
2615 
    {
2616 
      emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2617 
      addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2618 
    }
2619 
  else
2620 
    {
2621 
      emit_move_insn (op2, GEN_INT (4));
2622 
      addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2623 
    }
2624 
 
2625 
  if (BYTES_BIG_ENDIAN)
2626 
    {
2627 
      word_high = change_address (src, SImode, addr1);
2628 
      word_low  = change_address (src, SImode, addr2);
2629 
    }
2630 
  else
2631 
    {
2632 
      word_high = change_address (src, SImode, addr2);
2633 
      word_low  = change_address (src, SImode, addr1);
2634 
    }
2635 
 
2636 
  emit_insn (gen_bswapsi2 (dest_hi, word_low));
2637 
  emit_insn (gen_bswapsi2 (dest_lo, word_high));
2638 
}")
2639 
 
2640 
(define_split
2641 
  [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2642 
        (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2643 
   (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2644 
  "!TARGET_POWERPC64 && reload_completed"
2645 
  [(const_int 0)]
2646 
  "
2647 
{
2648 
  rtx dest     = operands[0];
2649 
  rtx src      = operands[1];
2650 
  rtx op2      = operands[2];
2651 
  rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2652 
  rtx src_low  = simplify_gen_subreg (SImode, src, DImode, 4);
2653 
  rtx addr1;
2654 
  rtx addr2;
2655 
  rtx word_high;
2656 
  rtx word_low;
2657 
 
2658 
  addr1 = XEXP (dest, 0);
2659 
  if (GET_CODE (addr1) == PLUS)
2660 
    {
2661 
      emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2662 
      addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2663 
    }
2664 
  else
2665 
    {
2666 
      emit_move_insn (op2, GEN_INT (4));
2667 
      addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2668 
    }
2669 
 
2670 
  if (BYTES_BIG_ENDIAN)
2671 
    {
2672 
      word_high = change_address (dest, SImode, addr1);
2673 
      word_low  = change_address (dest, SImode, addr2);
2674 
    }
2675 
  else
2676 
    {
2677 
      word_high = change_address (dest, SImode, addr2);
2678 
      word_low  = change_address (dest, SImode, addr1);
2679 
    }
2680 
 
2681 
  emit_insn (gen_bswapsi2 (word_high, src_low));
2682 
  emit_insn (gen_bswapsi2 (word_low, src_high));
2683 
}")
2684 
 
2685 
(define_split
2686 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
2687 
        (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2688 
   (clobber (match_operand:SI 2 "" ""))]
2689 
  "!TARGET_POWERPC64 && reload_completed"
2690 
  [(const_int 0)]
2691 
  "
2692 
{
2693 
  rtx dest      = operands[0];
2694 
  rtx src       = operands[1];
2695 
  rtx src_high  = simplify_gen_subreg (SImode, src, DImode, 0);
2696 
  rtx src_low   = simplify_gen_subreg (SImode, src, DImode, 4);
2697 
  rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2698 
  rtx dest_low  = simplify_gen_subreg (SImode, dest, DImode, 4);
2699 
 
2700 
  emit_insn (gen_bswapsi2 (dest_high, src_low));
2701 
  emit_insn (gen_bswapsi2 (dest_low, src_high));
2702 
}")
2703 
 
2704 
(define_expand "mulsi3"
2705 
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2706 
   (use (match_operand:SI 1 "gpc_reg_operand" ""))
2707 
   (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2708 
  ""
2709 
  "
2710 
{
2711 
  if (TARGET_POWER)
2712 
    emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2713 
  else
2714 
    emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2715 
  DONE;
2716 
}")
2717 
 
2718 
(define_insn "mulsi3_mq"
2719 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2720 
        (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2721 
                 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2722 
   (clobber (match_scratch:SI 3 "=q,q"))]
2723 
  "TARGET_POWER"
2724 
  "@
2725 
   {muls|mullw} %0,%1,%2
2726 
   {muli|mulli} %0,%1,%2"
2727 
   [(set (attr "type")
2728 
      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2729 
                (const_string "imul3")
2730 
             (match_operand:SI 2 "short_cint_operand" "")
2731 
                (const_string "imul2")]
2732 
        (const_string "imul")))])
2733 
 
2734 
(define_insn "mulsi3_no_mq"
2735 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2736 
        (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2737 
                 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2738 
  "! TARGET_POWER"
2739 
  "@
2740 
   {muls|mullw} %0,%1,%2
2741 
   {muli|mulli} %0,%1,%2"
2742 
   [(set (attr "type")
2743 
      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2744 
                (const_string "imul3")
2745 
             (match_operand:SI 2 "short_cint_operand" "")
2746 
                (const_string "imul2")]
2747 
        (const_string "imul")))])
2748 
 
2749 
(define_insn "*mulsi3_mq_internal1"
2750 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2751 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2752 
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2753 
                    (const_int 0)))
2754 
   (clobber (match_scratch:SI 3 "=r,r"))
2755 
   (clobber (match_scratch:SI 4 "=q,q"))]
2756 
  "TARGET_POWER"
2757 
  "@
2758 
   {muls.|mullw.} %3,%1,%2
2759 
   #"
2760 
  [(set_attr "type" "imul_compare")
2761 
   (set_attr "length" "4,8")])
2762 
 
2763 
(define_split
2764 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2765 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2766 
                             (match_operand:SI 2 "gpc_reg_operand" ""))
2767 
                    (const_int 0)))
2768 
   (clobber (match_scratch:SI 3 ""))
2769 
   (clobber (match_scratch:SI 4 ""))]
2770 
  "TARGET_POWER && reload_completed"
2771 
  [(parallel [(set (match_dup 3)
2772 
        (mult:SI (match_dup 1) (match_dup 2)))
2773 
   (clobber (match_dup 4))])
2774 
   (set (match_dup 0)
2775 
        (compare:CC (match_dup 3)
2776 
                    (const_int 0)))]
2777 
  "")
2778 
 
2779 
(define_insn "*mulsi3_no_mq_internal1"
2780 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2781 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2782 
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2783 
                    (const_int 0)))
2784 
   (clobber (match_scratch:SI 3 "=r,r"))]
2785 
  "! TARGET_POWER"
2786 
  "@
2787 
   {muls.|mullw.} %3,%1,%2
2788 
   #"
2789 
  [(set_attr "type" "imul_compare")
2790 
   (set_attr "length" "4,8")])
2791 
 
2792 
(define_split
2793 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2794 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2795 
                             (match_operand:SI 2 "gpc_reg_operand" ""))
2796 
                    (const_int 0)))
2797 
   (clobber (match_scratch:SI 3 ""))]
2798 
  "! TARGET_POWER && reload_completed"
2799 
  [(set (match_dup 3)
2800 
        (mult:SI (match_dup 1) (match_dup 2)))
2801 
   (set (match_dup 0)
2802 
        (compare:CC (match_dup 3)
2803 
                    (const_int 0)))]
2804 
  "")
2805 
 
2806 
(define_insn "*mulsi3_mq_internal2"
2807 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2808 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2809 
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2810 
                    (const_int 0)))
2811 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2812 
        (mult:SI (match_dup 1) (match_dup 2)))
2813 
   (clobber (match_scratch:SI 4 "=q,q"))]
2814 
  "TARGET_POWER"
2815 
  "@
2816 
   {muls.|mullw.} %0,%1,%2
2817 
   #"
2818 
  [(set_attr "type" "imul_compare")
2819 
   (set_attr "length" "4,8")])
2820 
 
2821 
(define_split
2822 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2823 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2824 
                             (match_operand:SI 2 "gpc_reg_operand" ""))
2825 
                    (const_int 0)))
2826 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
2827 
        (mult:SI (match_dup 1) (match_dup 2)))
2828 
   (clobber (match_scratch:SI 4 ""))]
2829 
  "TARGET_POWER && reload_completed"
2830 
  [(parallel [(set (match_dup 0)
2831 
        (mult:SI (match_dup 1) (match_dup 2)))
2832 
   (clobber (match_dup 4))])
2833 
   (set (match_dup 3)
2834 
        (compare:CC (match_dup 0)
2835 
                    (const_int 0)))]
2836 
  "")
2837 
 
2838 
(define_insn "*mulsi3_no_mq_internal2"
2839 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2840 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2841 
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2842 
                    (const_int 0)))
2843 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2844 
        (mult:SI (match_dup 1) (match_dup 2)))]
2845 
  "! TARGET_POWER"
2846 
  "@
2847 
   {muls.|mullw.} %0,%1,%2
2848 
   #"
2849 
  [(set_attr "type" "imul_compare")
2850 
   (set_attr "length" "4,8")])
2851 
 
2852 
(define_split
2853 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2854 
        (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2855 
                             (match_operand:SI 2 "gpc_reg_operand" ""))
2856 
                    (const_int 0)))
2857 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
2858 
        (mult:SI (match_dup 1) (match_dup 2)))]
2859 
  "! TARGET_POWER && reload_completed"
2860 
  [(set (match_dup 0)
2861 
        (mult:SI (match_dup 1) (match_dup 2)))
2862 
   (set (match_dup 3)
2863 
        (compare:CC (match_dup 0)
2864 
                    (const_int 0)))]
2865 
  "")
2866 
 
2867 
;; Operand 1 is divided by operand 2; quotient goes to operand
2868 
;; 0 and remainder to operand 3.
2869 
;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2870 
 
2871 
(define_expand "divmodsi4"
2872 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2873 
                   (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2874 
                           (match_operand:SI 2 "gpc_reg_operand" "")))
2875 
              (set (match_operand:SI 3 "register_operand" "")
2876 
                   (mod:SI (match_dup 1) (match_dup 2)))])]
2877 
  "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2878 
  "
2879 
{
2880 
  if (! TARGET_POWER && ! TARGET_POWERPC)
2881 
    {
2882 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2883 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2884 
      emit_insn (gen_divss_call ());
2885 
      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2886 
      emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2887 
      DONE;
2888 
    }
2889 
}")
2890 
 
2891 
(define_insn "*divmodsi4_internal"
2892 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2893 
        (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2894 
                (match_operand:SI 2 "gpc_reg_operand" "r")))
2895 
   (set (match_operand:SI 3 "register_operand" "=q")
2896 
        (mod:SI (match_dup 1) (match_dup 2)))]
2897 
  "TARGET_POWER"
2898 
  "divs %0,%1,%2"
2899 
  [(set_attr "type" "idiv")])
2900 
 
2901 
(define_expand "udiv3"
2902 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2903 
        (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2904 
                  (match_operand:GPR 2 "gpc_reg_operand" "")))]
2905 
  "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2906 
  "
2907 
{
2908 
  if (! TARGET_POWER && ! TARGET_POWERPC)
2909 
    {
2910 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2911 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2912 
      emit_insn (gen_quous_call ());
2913 
      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2914 
      DONE;
2915 
    }
2916 
  else if (TARGET_POWER)
2917 
    {
2918 
      emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2919 
      DONE;
2920 
    }
2921 
}")
2922 
 
2923 
(define_insn "udivsi3_mq"
2924 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2925 
        (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2926 
                 (match_operand:SI 2 "gpc_reg_operand" "r")))
2927 
   (clobber (match_scratch:SI 3 "=q"))]
2928 
  "TARGET_POWERPC && TARGET_POWER"
2929 
  "divwu %0,%1,%2"
2930 
  [(set_attr "type" "idiv")])
2931 
 
2932 
(define_insn "*udivsi3_no_mq"
2933 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2934 
        (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2935 
                  (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2936 
  "TARGET_POWERPC && ! TARGET_POWER"
2937 
  "divu %0,%1,%2"
2938 
   [(set (attr "type")
2939 
      (cond [(match_operand:SI 0 "" "")
2940 
                (const_string "idiv")]
2941 
        (const_string "ldiv")))])
2942 
 
2943 
 
2944 
;; For powers of two we can do srai/aze for divide and then adjust for
2945 
;; modulus.  If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2946 
;; used; for PowerPC, force operands into register and do a normal divide;
2947 
;; for AIX common-mode, use quoss call on register operands.
2948 
(define_expand "div3"
2949 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2950 
        (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2951 
                 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2952 
  ""
2953 
  "
2954 
{
2955 
  if (GET_CODE (operands[2]) == CONST_INT
2956 
      && INTVAL (operands[2]) > 0
2957 
      && exact_log2 (INTVAL (operands[2])) >= 0)
2958 
    ;
2959 
  else if (TARGET_POWERPC)
2960 
    {
2961 
      operands[2] = force_reg (mode, operands[2]);
2962 
      if (TARGET_POWER)
2963 
        {
2964 
          emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2965 
          DONE;
2966 
        }
2967 
    }
2968 
  else if (TARGET_POWER)
2969 
    FAIL;
2970 
  else
2971 
    {
2972 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2973 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2974 
      emit_insn (gen_quoss_call ());
2975 
      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2976 
      DONE;
2977 
    }
2978 
}")
2979 
 
2980 
(define_insn "divsi3_mq"
2981 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2982 
        (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2983 
                (match_operand:SI 2 "gpc_reg_operand" "r")))
2984 
   (clobber (match_scratch:SI 3 "=q"))]
2985 
  "TARGET_POWERPC && TARGET_POWER"
2986 
  "divw %0,%1,%2"
2987 
  [(set_attr "type" "idiv")])
2988 
 
2989 
(define_insn "*div3_no_mq"
2990 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2991 
        (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2992 
                 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2993 
  "TARGET_POWERPC && ! TARGET_POWER"
2994 
  "div %0,%1,%2"
2995 
  [(set (attr "type")
2996 
     (cond [(match_operand:SI 0 "" "")
2997 
                (const_string "idiv")]
2998 
        (const_string "ldiv")))])
2999 
 
3000 
(define_expand "mod3"
3001 
  [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3002 
   (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3003 
   (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3004 
  ""
3005 
  "
3006 
{
3007 
  int i;
3008 
  rtx temp1;
3009 
  rtx temp2;
3010 
 
3011 
  if (GET_CODE (operands[2]) != CONST_INT
3012 
      || INTVAL (operands[2]) <= 0
3013 
      || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3014 
    FAIL;
3015 
 
3016 
  temp1 = gen_reg_rtx (mode);
3017 
  temp2 = gen_reg_rtx (mode);
3018 
 
3019 
  emit_insn (gen_div3 (temp1, operands[1], operands[2]));
3020 
  emit_insn (gen_ashl3 (temp2, temp1, GEN_INT (i)));
3021 
  emit_insn (gen_sub3 (operands[0], operands[1], temp2));
3022 
  DONE;
3023 
}")
3024 
 
3025 
(define_insn ""
3026 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3027 
        (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3028 
                 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3029 
  ""
3030 
  "{srai|srai} %0,%1,%p2\;{aze|addze} %0,%0"
3031 
  [(set_attr "type" "two")
3032 
   (set_attr "length" "8")])
3033 
 
3034 
(define_insn ""
3035 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3036 
        (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3037 
                           (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3038 
                    (const_int 0)))
3039 
   (clobber (match_scratch:P 3 "=r,r"))]
3040 
  ""
3041 
  "@
3042 
   {srai|srai} %3,%1,%p2\;{aze.|addze.} %3,%3
3043 
   #"
3044 
  [(set_attr "type" "compare")
3045 
   (set_attr "length" "8,12")
3046 
   (set_attr "cell_micro" "not")])
3047 
 
3048 
(define_split
3049 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3050 
        (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3051 
                             (match_operand:GPR 2 "exact_log2_cint_operand"
3052 
                              ""))
3053 
                    (const_int 0)))
3054 
   (clobber (match_scratch:GPR 3 ""))]
3055 
  "reload_completed"
3056 
  [(set (match_dup 3)
3057 
        (div: (match_dup 1) (match_dup 2)))
3058 
   (set (match_dup 0)
3059 
        (compare:CC (match_dup 3)
3060 
                    (const_int 0)))]
3061 
  "")
3062 
 
3063 
(define_insn ""
3064 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3065 
        (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3066 
                           (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3067 
                    (const_int 0)))
3068 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3069 
        (div:P (match_dup 1) (match_dup 2)))]
3070 
  ""
3071 
  "@
3072 
   {srai|srai} %0,%1,%p2\;{aze.|addze.} %0,%0
3073 
   #"
3074 
  [(set_attr "type" "compare")
3075 
   (set_attr "length" "8,12")
3076 
   (set_attr "cell_micro" "not")])
3077 
 
3078 
(define_split
3079 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3080 
        (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3081 
                             (match_operand:GPR 2 "exact_log2_cint_operand"
3082 
                              ""))
3083 
                    (const_int 0)))
3084 
   (set (match_operand:GPR 0 "gpc_reg_operand" "")
3085 
        (div:GPR (match_dup 1) (match_dup 2)))]
3086 
  "reload_completed"
3087 
  [(set (match_dup 0)
3088 
        (div: (match_dup 1) (match_dup 2)))
3089 
   (set (match_dup 3)
3090 
        (compare:CC (match_dup 0)
3091 
                    (const_int 0)))]
3092 
  "")
3093 
 
3094 
(define_insn ""
3095 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3096 
        (udiv:SI
3097 
         (plus:DI (ashift:DI
3098 
                   (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3099 
                   (const_int 32))
3100 
                  (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3101 
         (match_operand:SI 3 "gpc_reg_operand" "r")))
3102 
   (set (match_operand:SI 2 "register_operand" "=*q")
3103 
        (umod:SI
3104 
         (plus:DI (ashift:DI
3105 
                   (zero_extend:DI (match_dup 1)) (const_int 32))
3106 
                  (zero_extend:DI (match_dup 4)))
3107 
         (match_dup 3)))]
3108 
  "TARGET_POWER"
3109 
  "div %0,%1,%3"
3110 
  [(set_attr "type" "idiv")])
3111 
 
3112 
;; To do unsigned divide we handle the cases of the divisor looking like a
3113 
;; negative number.  If it is a constant that is less than 2**31, we don't
3114 
;; have to worry about the branches.  So make a few subroutines here.
3115 
;;
3116 
;; First comes the normal case.
3117 
(define_expand "udivmodsi4_normal"
3118 
  [(set (match_dup 4) (const_int 0))
3119 
   (parallel [(set (match_operand:SI 0 "" "")
3120 
                   (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3121 
                                                (const_int 32))
3122 
                                     (zero_extend:DI (match_operand:SI 1 "" "")))
3123 
                            (match_operand:SI 2 "" "")))
3124 
              (set (match_operand:SI 3 "" "")
3125 
                   (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3126 
                                                (const_int 32))
3127 
                                     (zero_extend:DI (match_dup 1)))
3128 
                            (match_dup 2)))])]
3129 
  "TARGET_POWER"
3130 
  "
3131 
{ operands[4] = gen_reg_rtx (SImode); }")
3132 
 
3133 
;; This handles the branches.
3134 
(define_expand "udivmodsi4_tests"
3135 
  [(set (match_operand:SI 0 "" "") (const_int 0))
3136 
   (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3137 
   (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3138 
   (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3139 
                           (label_ref (match_operand:SI 4 "" "")) (pc)))
3140 
   (set (match_dup 0) (const_int 1))
3141 
   (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3142 
   (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3143 
   (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3144 
                           (label_ref (match_dup 4)) (pc)))]
3145 
  "TARGET_POWER"
3146 
  "
3147 
{ operands[5] = gen_reg_rtx (CCUNSmode);
3148 
  operands[6] = gen_reg_rtx (CCmode);
3149 
}")
3150 
 
3151 
(define_expand "udivmodsi4"
3152 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3153 
                   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3154 
                            (match_operand:SI 2 "reg_or_cint_operand" "")))
3155 
              (set (match_operand:SI 3 "gpc_reg_operand" "")
3156 
                   (umod:SI (match_dup 1) (match_dup 2)))])]
3157 
  ""
3158 
  "
3159 
{
3160 
  rtx label = 0;
3161 
 
3162 
  if (! TARGET_POWER)
3163 
    {
3164 
      if (! TARGET_POWERPC)
3165 
        {
3166 
          emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3167 
          emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3168 
          emit_insn (gen_divus_call ());
3169 
          emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3170 
          emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3171 
          DONE;
3172 
        }
3173 
      else
3174 
        FAIL;
3175 
    }
3176 
 
3177 
  if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3178 
    {
3179 
      operands[2] = force_reg (SImode, operands[2]);
3180 
      label = gen_label_rtx ();
3181 
      emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3182 
                                  operands[3], label));
3183 
    }
3184 
  else
3185 
    operands[2] = force_reg (SImode, operands[2]);
3186 
 
3187 
  emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3188 
                               operands[3]));
3189 
  if (label)
3190 
    emit_label (label);
3191 
 
3192 
  DONE;
3193 
}")
3194 
 
3195 
;; AIX architecture-independent common-mode multiply (DImode),
3196 
;; divide/modulus, and quotient subroutine calls.  Input operands in R3 and
3197 
;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3198 
;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3199 
;; assumed unused if generating common-mode, so ignore.
3200 
(define_insn "mulh_call"
3201 
  [(set (reg:SI 3)
3202 
        (truncate:SI
3203 
         (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3204 
                               (sign_extend:DI (reg:SI 4)))
3205 
                      (const_int 32))))
3206 
   (clobber (reg:SI LR_REGNO))]
3207 
  "! TARGET_POWER && ! TARGET_POWERPC"
3208 
  "bla __mulh"
3209 
  [(set_attr "type" "imul")])
3210 
 
3211 
(define_insn "mull_call"
3212 
  [(set (reg:DI 3)
3213 
        (mult:DI (sign_extend:DI (reg:SI 3))
3214 
                 (sign_extend:DI (reg:SI 4))))
3215 
   (clobber (reg:SI LR_REGNO))
3216 
   (clobber (reg:SI 0))]
3217 
  "! TARGET_POWER && ! TARGET_POWERPC"
3218 
  "bla __mull"
3219 
  [(set_attr "type" "imul")])
3220 
 
3221 
(define_insn "divss_call"
3222 
  [(set (reg:SI 3)
3223 
        (div:SI (reg:SI 3) (reg:SI 4)))
3224 
   (set (reg:SI 4)
3225 
        (mod:SI (reg:SI 3) (reg:SI 4)))
3226 
   (clobber (reg:SI LR_REGNO))
3227 
   (clobber (reg:SI 0))]
3228 
  "! TARGET_POWER && ! TARGET_POWERPC"
3229 
  "bla __divss"
3230 
  [(set_attr "type" "idiv")])
3231 
 
3232 
(define_insn "divus_call"
3233 
  [(set (reg:SI 3)
3234 
        (udiv:SI (reg:SI 3) (reg:SI 4)))
3235 
   (set (reg:SI 4)
3236 
        (umod:SI (reg:SI 3) (reg:SI 4)))
3237 
   (clobber (reg:SI LR_REGNO))
3238 
   (clobber (reg:SI 0))
3239 
   (clobber (match_scratch:CC 0 "=x"))
3240 
   (clobber (reg:CC CR1_REGNO))]
3241 
  "! TARGET_POWER && ! TARGET_POWERPC"
3242 
  "bla __divus"
3243 
  [(set_attr "type" "idiv")])
3244 
 
3245 
(define_insn "quoss_call"
3246 
  [(set (reg:SI 3)
3247 
        (div:SI (reg:SI 3) (reg:SI 4)))
3248 
   (clobber (reg:SI LR_REGNO))]
3249 
  "! TARGET_POWER && ! TARGET_POWERPC"
3250 
  "bla __quoss"
3251 
  [(set_attr "type" "idiv")])
3252 
 
3253 
(define_insn "quous_call"
3254 
  [(set (reg:SI 3)
3255 
        (udiv:SI (reg:SI 3) (reg:SI 4)))
3256 
   (clobber (reg:SI LR_REGNO))
3257 
   (clobber (reg:SI 0))
3258 
   (clobber (match_scratch:CC 0 "=x"))
3259 
   (clobber (reg:CC CR1_REGNO))]
3260 
  "! TARGET_POWER && ! TARGET_POWERPC"
3261 
  "bla __quous"
3262 
  [(set_attr "type" "idiv")])
3263 
 
3264 
;; Logical instructions
3265 
;; The logical instructions are mostly combined by using match_operator,
3266 
;; but the plain AND insns are somewhat different because there is no
3267 
;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3268 
;; those rotate-and-mask operations.  Thus, the AND insns come first.
3269 
 
3270 
(define_expand "andsi3"
3271 
  [(parallel
3272 
    [(set (match_operand:SI 0 "gpc_reg_operand" "")
3273 
          (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3274 
                  (match_operand:SI 2 "and_operand" "")))
3275 
     (clobber (match_scratch:CC 3 ""))])]
3276 
  ""
3277 
  "")
3278 
 
3279 
(define_insn "andsi3_mc"
3280 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3281 
        (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3282 
                (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3283 
   (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3284 
  "rs6000_gen_cell_microcode"
3285 
  "@
3286 
   and %0,%1,%2
3287 
   {rlinm|rlwinm} %0,%1,0,%m2,%M2
3288 
   {andil.|andi.} %0,%1,%b2
3289 
   {andiu.|andis.} %0,%1,%u2"
3290 
  [(set_attr "type" "*,*,fast_compare,fast_compare")])
3291 
 
3292 
(define_insn "andsi3_nomc"
3293 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3294 
        (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3295 
                (match_operand:SI 2 "and_operand" "?r,T")))
3296 
   (clobber (match_scratch:CC 3 "=X,X"))]
3297 
  "!rs6000_gen_cell_microcode"
3298 
  "@
3299 
   and %0,%1,%2
3300 
   {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3301 
 
3302 
(define_insn "andsi3_internal0_nomc"
3303 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3304 
        (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3305 
                (match_operand:SI 2 "and_operand" "?r,T")))]
3306 
  "!rs6000_gen_cell_microcode"
3307 
  "@
3308 
   and %0,%1,%2
3309 
   {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3310 
 
3311 
 
3312 
;; Note to set cr's other than cr0 we do the and immediate and then
3313 
;; the test again -- this avoids a mfcr which on the higher end
3314 
;; machines causes an execution serialization
3315 
 
3316 
(define_insn "*andsi3_internal2_mc"
3317 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3318 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3319 
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3320 
                    (const_int 0)))
3321 
   (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3322 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3323 
  "TARGET_32BIT && rs6000_gen_cell_microcode"
3324 
  "@
3325 
   and. %3,%1,%2
3326 
   {andil.|andi.} %3,%1,%b2
3327 
   {andiu.|andis.} %3,%1,%u2
3328 
   {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3329 
   #
3330 
   #
3331 
   #
3332 
   #"
3333 
  [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3334 
                     compare,compare,compare,compare")
3335 
   (set_attr "length" "4,4,4,4,8,8,8,8")])
3336 
 
3337 
(define_insn "*andsi3_internal3_mc"
3338 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3339 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3340 
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3341 
                    (const_int 0)))
3342 
   (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3343 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3344 
  "TARGET_64BIT && rs6000_gen_cell_microcode"
3345 
  "@
3346 
   #
3347 
   {andil.|andi.} %3,%1,%b2
3348 
   {andiu.|andis.} %3,%1,%u2
3349 
   {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3350 
   #
3351 
   #
3352 
   #
3353 
   #"
3354 
  [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3355 
                     compare,compare,compare")
3356 
   (set_attr "length" "8,4,4,4,8,8,8,8")])
3357 
 
3358 
(define_split
3359 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3360 
        (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3361 
                             (match_operand:GPR 2 "and_operand" ""))
3362 
                    (const_int 0)))
3363 
   (clobber (match_scratch:GPR 3 ""))
3364 
   (clobber (match_scratch:CC 4 ""))]
3365 
  "reload_completed"
3366 
  [(parallel [(set (match_dup 3)
3367 
                   (and: (match_dup 1)
3368 
                               (match_dup 2)))
3369 
              (clobber (match_dup 4))])
3370 
   (set (match_dup 0)
3371 
        (compare:CC (match_dup 3)
3372 
                    (const_int 0)))]
3373 
  "")
3374 
 
3375 
;; We don't have a 32 bit "and. rt,ra,rb" for ppc64.  cr is set from the
3376 
;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3377 
 
3378 
(define_split
3379 
  [(set (match_operand:CC 0 "cc_reg_operand" "")
3380 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3381 
                            (match_operand:SI 2 "gpc_reg_operand" ""))
3382 
                    (const_int 0)))
3383 
   (clobber (match_scratch:SI 3 ""))
3384 
   (clobber (match_scratch:CC 4 ""))]
3385 
  "TARGET_POWERPC64 && reload_completed"
3386 
  [(parallel [(set (match_dup 3)
3387 
                   (and:SI (match_dup 1)
3388 
                           (match_dup 2)))
3389 
              (clobber (match_dup 4))])
3390 
   (set (match_dup 0)
3391 
        (compare:CC (match_dup 3)
3392 
                    (const_int 0)))]
3393 
  "")
3394 
 
3395 
(define_insn "*andsi3_internal4"
3396 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3397 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3398 
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3399 
                    (const_int 0)))
3400 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3401 
        (and:SI (match_dup 1)
3402 
                (match_dup 2)))
3403 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3404 
  "TARGET_32BIT && rs6000_gen_cell_microcode"
3405 
  "@
3406 
   and. %0,%1,%2
3407 
   {andil.|andi.} %0,%1,%b2
3408 
   {andiu.|andis.} %0,%1,%u2
3409 
   {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3410 
   #
3411 
   #
3412 
   #
3413 
   #"
3414 
  [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3415 
                     compare,compare,compare,compare")
3416 
   (set_attr "length" "4,4,4,4,8,8,8,8")])
3417 
 
3418 
(define_insn "*andsi3_internal5_mc"
3419 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3420 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3421 
                            (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3422 
                    (const_int 0)))
3423 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3424 
        (and:SI (match_dup 1)
3425 
                (match_dup 2)))
3426 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3427 
  "TARGET_64BIT && rs6000_gen_cell_microcode"
3428 
  "@
3429 
   #
3430 
   {andil.|andi.} %0,%1,%b2
3431 
   {andiu.|andis.} %0,%1,%u2
3432 
   {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3433 
   #
3434 
   #
3435 
   #
3436 
   #"
3437 
  [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3438 
                     compare,compare,compare")
3439 
   (set_attr "length" "8,4,4,4,8,8,8,8")])
3440 
 
3441 
(define_split
3442 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3443 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3444 
                            (match_operand:SI 2 "and_operand" ""))
3445 
                    (const_int 0)))
3446 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3447 
        (and:SI (match_dup 1)
3448 
                (match_dup 2)))
3449 
   (clobber (match_scratch:CC 4 ""))]
3450 
  "reload_completed"
3451 
  [(parallel [(set (match_dup 0)
3452 
                   (and:SI (match_dup 1)
3453 
                           (match_dup 2)))
3454 
              (clobber (match_dup 4))])
3455 
   (set (match_dup 3)
3456 
        (compare:CC (match_dup 0)
3457 
                    (const_int 0)))]
3458 
  "")
3459 
 
3460 
(define_split
3461 
  [(set (match_operand:CC 3 "cc_reg_operand" "")
3462 
        (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3463 
                            (match_operand:SI 2 "gpc_reg_operand" ""))
3464 
                    (const_int 0)))
3465 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3466 
        (and:SI (match_dup 1)
3467 
                (match_dup 2)))
3468 
   (clobber (match_scratch:CC 4 ""))]
3469 
  "TARGET_POWERPC64 && reload_completed"
3470 
  [(parallel [(set (match_dup 0)
3471 
                   (and:SI (match_dup 1)
3472 
                           (match_dup 2)))
3473 
              (clobber (match_dup 4))])
3474 
   (set (match_dup 3)
3475 
        (compare:CC (match_dup 0)
3476 
                    (const_int 0)))]
3477 
  "")
3478 
 
3479 
;; Handle the PowerPC64 rlwinm corner case
3480 
 
3481 
(define_insn_and_split "*andsi3_internal6"
3482 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3483 
        (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3484 
                (match_operand:SI 2 "mask_operand_wrap" "i")))]
3485 
  "TARGET_POWERPC64"
3486 
  "#"
3487 
  "TARGET_POWERPC64"
3488 
  [(set (match_dup 0)
3489 
        (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3490 
                (match_dup 4)))
3491 
   (set (match_dup 0)
3492 
        (rotate:SI (match_dup 0) (match_dup 5)))]
3493 
  "
3494 
{
3495 
  int mb = extract_MB (operands[2]);
3496 
  int me = extract_ME (operands[2]);
3497 
  operands[3] = GEN_INT (me + 1);
3498 
  operands[5] = GEN_INT (32 - (me + 1));
3499 
  operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3500 
}"
3501 
  [(set_attr "length" "8")])
3502 
 
3503 
(define_expand "iorsi3"
3504 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
3505 
        (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3506 
                (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3507 
  ""
3508 
  "
3509 
{
3510 
  if (GET_CODE (operands[2]) == CONST_INT
3511 
      && ! logical_operand (operands[2], SImode))
3512 
    {
3513 
      HOST_WIDE_INT value = INTVAL (operands[2]);
3514 
      rtx tmp = ((!can_create_pseudo_p ()
3515 
                  || rtx_equal_p (operands[0], operands[1]))
3516 
                 ? operands[0] : gen_reg_rtx (SImode));
3517 
 
3518 
      emit_insn (gen_iorsi3 (tmp, operands[1],
3519 
                             GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3520 
      emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3521 
      DONE;
3522 
    }
3523 
}")
3524 
 
3525 
(define_expand "xorsi3"
3526 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
3527 
        (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3528 
                (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3529 
  ""
3530 
  "
3531 
{
3532 
  if (GET_CODE (operands[2]) == CONST_INT
3533 
      && ! logical_operand (operands[2], SImode))
3534 
    {
3535 
      HOST_WIDE_INT value = INTVAL (operands[2]);
3536 
      rtx tmp = ((!can_create_pseudo_p ()
3537 
                  || rtx_equal_p (operands[0], operands[1]))
3538 
                 ? operands[0] : gen_reg_rtx (SImode));
3539 
 
3540 
      emit_insn (gen_xorsi3 (tmp, operands[1],
3541 
                             GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3542 
      emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3543 
      DONE;
3544 
    }
3545 
}")
3546 
 
3547 
(define_insn "*boolsi3_internal1"
3548 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3549 
        (match_operator:SI 3 "boolean_or_operator"
3550 
         [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3551 
          (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3552 
  ""
3553 
  "@
3554 
   %q3 %0,%1,%2
3555 
   {%q3il|%q3i} %0,%1,%b2
3556 
   {%q3iu|%q3is} %0,%1,%u2")
3557 
 
3558 
(define_insn "*boolsi3_internal2"
3559 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3560 
        (compare:CC (match_operator:SI 4 "boolean_or_operator"
3561 
         [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3562 
          (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3563 
         (const_int 0)))
3564 
   (clobber (match_scratch:SI 3 "=r,r"))]
3565 
  "TARGET_32BIT"
3566 
  "@
3567 
   %q4. %3,%1,%2
3568 
   #"
3569 
  [(set_attr "type" "fast_compare,compare")
3570 
   (set_attr "length" "4,8")])
3571 
 
3572 
(define_split
3573 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3574 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3575 
         [(match_operand:SI 1 "gpc_reg_operand" "")
3576 
          (match_operand:SI 2 "gpc_reg_operand" "")])
3577 
         (const_int 0)))
3578 
   (clobber (match_scratch:SI 3 ""))]
3579 
  "TARGET_32BIT && reload_completed"
3580 
  [(set (match_dup 3) (match_dup 4))
3581 
   (set (match_dup 0)
3582 
        (compare:CC (match_dup 3)
3583 
                    (const_int 0)))]
3584 
  "")
3585 
 
3586 
(define_insn "*boolsi3_internal3"
3587 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3588 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3589 
         [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3590 
          (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3591 
         (const_int 0)))
3592 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3593 
        (match_dup 4))]
3594 
  "TARGET_32BIT"
3595 
  "@
3596 
   %q4. %0,%1,%2
3597 
   #"
3598 
  [(set_attr "type" "fast_compare,compare")
3599 
   (set_attr "length" "4,8")])
3600 
 
3601 
(define_split
3602 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3603 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3604 
         [(match_operand:SI 1 "gpc_reg_operand" "")
3605 
          (match_operand:SI 2 "gpc_reg_operand" "")])
3606 
         (const_int 0)))
3607 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3608 
        (match_dup 4))]
3609 
  "TARGET_32BIT && reload_completed"
3610 
  [(set (match_dup 0) (match_dup 4))
3611 
   (set (match_dup 3)
3612 
        (compare:CC (match_dup 0)
3613 
                    (const_int 0)))]
3614 
  "")
3615 
 
3616 
;; Split a logical operation that we can't do in one insn into two insns,
3617 
;; each of which does one 16-bit part.  This is used by combine.
3618 
 
3619 
(define_split
3620 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
3621 
        (match_operator:SI 3 "boolean_or_operator"
3622 
         [(match_operand:SI 1 "gpc_reg_operand" "")
3623 
          (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3624 
  ""
3625 
  [(set (match_dup 0) (match_dup 4))
3626 
   (set (match_dup 0) (match_dup 5))]
3627 
"
3628 
{
3629 
  rtx i;
3630 
  i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3631 
  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3632 
                                operands[1], i);
3633 
  i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3634 
  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3635 
                                operands[0], i);
3636 
}")
3637 
 
3638 
(define_insn "*boolcsi3_internal1"
3639 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3640 
        (match_operator:SI 3 "boolean_operator"
3641 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3642 
          (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3643 
  ""
3644 
  "%q3 %0,%2,%1")
3645 
 
3646 
(define_insn "*boolcsi3_internal2"
3647 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3648 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3649 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3650 
          (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3651 
         (const_int 0)))
3652 
   (clobber (match_scratch:SI 3 "=r,r"))]
3653 
  "TARGET_32BIT"
3654 
  "@
3655 
   %q4. %3,%2,%1
3656 
   #"
3657 
  [(set_attr "type" "compare")
3658 
   (set_attr "length" "4,8")])
3659 
 
3660 
(define_split
3661 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3662 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3663 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3664 
          (match_operand:SI 2 "gpc_reg_operand" "")])
3665 
         (const_int 0)))
3666 
   (clobber (match_scratch:SI 3 ""))]
3667 
  "TARGET_32BIT && reload_completed"
3668 
  [(set (match_dup 3) (match_dup 4))
3669 
   (set (match_dup 0)
3670 
        (compare:CC (match_dup 3)
3671 
                    (const_int 0)))]
3672 
  "")
3673 
 
3674 
(define_insn "*boolcsi3_internal3"
3675 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3676 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3677 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3678 
          (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3679 
         (const_int 0)))
3680 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3681 
        (match_dup 4))]
3682 
  "TARGET_32BIT"
3683 
  "@
3684 
   %q4. %0,%2,%1
3685 
   #"
3686 
  [(set_attr "type" "compare")
3687 
   (set_attr "length" "4,8")])
3688 
 
3689 
(define_split
3690 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3691 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3692 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3693 
          (match_operand:SI 2 "gpc_reg_operand" "")])
3694 
         (const_int 0)))
3695 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3696 
        (match_dup 4))]
3697 
  "TARGET_32BIT && reload_completed"
3698 
  [(set (match_dup 0) (match_dup 4))
3699 
   (set (match_dup 3)
3700 
        (compare:CC (match_dup 0)
3701 
                    (const_int 0)))]
3702 
  "")
3703 
 
3704 
(define_insn "*boolccsi3_internal1"
3705 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3706 
        (match_operator:SI 3 "boolean_operator"
3707 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3708 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3709 
  ""
3710 
  "%q3 %0,%1,%2")
3711 
 
3712 
(define_insn "*boolccsi3_internal2"
3713 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3714 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3715 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3716 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3717 
         (const_int 0)))
3718 
   (clobber (match_scratch:SI 3 "=r,r"))]
3719 
  "TARGET_32BIT"
3720 
  "@
3721 
   %q4. %3,%1,%2
3722 
   #"
3723 
  [(set_attr "type" "fast_compare,compare")
3724 
   (set_attr "length" "4,8")])
3725 
 
3726 
(define_split
3727 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3728 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3729 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3730 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3731 
         (const_int 0)))
3732 
   (clobber (match_scratch:SI 3 ""))]
3733 
  "TARGET_32BIT && reload_completed"
3734 
  [(set (match_dup 3) (match_dup 4))
3735 
   (set (match_dup 0)
3736 
        (compare:CC (match_dup 3)
3737 
                    (const_int 0)))]
3738 
  "")
3739 
 
3740 
(define_insn "*boolccsi3_internal3"
3741 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3742 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3743 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3744 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3745 
         (const_int 0)))
3746 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3747 
        (match_dup 4))]
3748 
  "TARGET_32BIT"
3749 
  "@
3750 
   %q4. %0,%1,%2
3751 
   #"
3752 
  [(set_attr "type" "fast_compare,compare")
3753 
   (set_attr "length" "4,8")])
3754 
 
3755 
(define_split
3756 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3757 
        (compare:CC (match_operator:SI 4 "boolean_operator"
3758 
         [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3759 
          (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3760 
         (const_int 0)))
3761 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3762 
        (match_dup 4))]
3763 
  "TARGET_32BIT && reload_completed"
3764 
  [(set (match_dup 0) (match_dup 4))
3765 
   (set (match_dup 3)
3766 
        (compare:CC (match_dup 0)
3767 
                    (const_int 0)))]
3768 
  "")
3769 
 
3770 
;; maskir insn.  We need four forms because things might be in arbitrary
3771 
;; orders.  Don't define forms that only set CR fields because these
3772 
;; would modify an input register.
3773 
 
3774 
(define_insn "*maskir_internal1"
3775 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3776 
        (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3777 
                        (match_operand:SI 1 "gpc_reg_operand" "0"))
3778 
                (and:SI (match_dup 2)
3779 
                        (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3780 
  "TARGET_POWER"
3781 
  "maskir %0,%3,%2")
3782 
 
3783 
(define_insn "*maskir_internal2"
3784 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3785 
        (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3786 
                        (match_operand:SI 1 "gpc_reg_operand" "0"))
3787 
                (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3788 
                        (match_dup 2))))]
3789 
  "TARGET_POWER"
3790 
  "maskir %0,%3,%2")
3791 
 
3792 
(define_insn "*maskir_internal3"
3793 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3794 
        (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3795 
                        (match_operand:SI 3 "gpc_reg_operand" "r"))
3796 
                (and:SI (not:SI (match_dup 2))
3797 
                        (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3798 
  "TARGET_POWER"
3799 
  "maskir %0,%3,%2")
3800 
 
3801 
(define_insn "*maskir_internal4"
3802 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3803 
        (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3804 
                        (match_operand:SI 2 "gpc_reg_operand" "r"))
3805 
                (and:SI (not:SI (match_dup 2))
3806 
                        (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3807 
  "TARGET_POWER"
3808 
  "maskir %0,%3,%2")
3809 
 
3810 
(define_insn "*maskir_internal5"
3811 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3812 
        (compare:CC
3813 
         (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3814 
                         (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3815 
                 (and:SI (match_dup 2)
3816 
                         (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3817 
         (const_int 0)))
3818 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3819 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3820 
                (and:SI (match_dup 2) (match_dup 3))))]
3821 
  "TARGET_POWER"
3822 
  "@
3823 
   maskir. %0,%3,%2
3824 
   #"
3825 
  [(set_attr "type" "compare")
3826 
   (set_attr "length" "4,8")])
3827 
 
3828 
(define_split
3829 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3830 
        (compare:CC
3831 
         (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3832 
                         (match_operand:SI 1 "gpc_reg_operand" ""))
3833 
                 (and:SI (match_dup 2)
3834 
                         (match_operand:SI 3 "gpc_reg_operand" "")))
3835 
         (const_int 0)))
3836 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3837 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3838 
                (and:SI (match_dup 2) (match_dup 3))))]
3839 
  "TARGET_POWER && reload_completed"
3840 
  [(set (match_dup 0)
3841 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3842 
                (and:SI (match_dup 2) (match_dup 3))))
3843 
   (set (match_dup 4)
3844 
        (compare:CC (match_dup 0)
3845 
                    (const_int 0)))]
3846 
  "")
3847 
 
3848 
(define_insn "*maskir_internal6"
3849 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3850 
        (compare:CC
3851 
         (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3852 
                         (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3853 
                 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3854 
                         (match_dup 2)))
3855 
         (const_int 0)))
3856 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3857 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3858 
                (and:SI (match_dup 3) (match_dup 2))))]
3859 
  "TARGET_POWER"
3860 
  "@
3861 
   maskir. %0,%3,%2
3862 
   #"
3863 
  [(set_attr "type" "compare")
3864 
   (set_attr "length" "4,8")])
3865 
 
3866 
(define_split
3867 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3868 
        (compare:CC
3869 
         (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3870 
                         (match_operand:SI 1 "gpc_reg_operand" ""))
3871 
                 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3872 
                         (match_dup 2)))
3873 
         (const_int 0)))
3874 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3875 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3876 
                (and:SI (match_dup 3) (match_dup 2))))]
3877 
  "TARGET_POWER && reload_completed"
3878 
  [(set (match_dup 0)
3879 
        (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3880 
                (and:SI (match_dup 3) (match_dup 2))))
3881 
   (set (match_dup 4)
3882 
        (compare:CC (match_dup 0)
3883 
                    (const_int 0)))]
3884 
  "")
3885 
 
3886 
(define_insn "*maskir_internal7"
3887 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3888 
        (compare:CC
3889 
         (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3890 
                         (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3891 
                 (and:SI (not:SI (match_dup 2))
3892 
                         (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3893 
         (const_int 0)))
3894 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3895 
        (ior:SI (and:SI (match_dup 2) (match_dup 3))
3896 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3897 
  "TARGET_POWER"
3898 
  "@
3899 
   maskir. %0,%3,%2
3900 
   #"
3901 
  [(set_attr "type" "compare")
3902 
   (set_attr "length" "4,8")])
3903 
 
3904 
(define_split
3905 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3906 
        (compare:CC
3907 
         (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3908 
                         (match_operand:SI 3 "gpc_reg_operand" ""))
3909 
                 (and:SI (not:SI (match_dup 2))
3910 
                         (match_operand:SI 1 "gpc_reg_operand" "")))
3911 
         (const_int 0)))
3912 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3913 
        (ior:SI (and:SI (match_dup 2) (match_dup 3))
3914 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3915 
  "TARGET_POWER && reload_completed"
3916 
  [(set (match_dup 0)
3917 
        (ior:SI (and:SI (match_dup 2) (match_dup 3))
3918 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3919 
   (set (match_dup 4)
3920 
        (compare:CC (match_dup 0)
3921 
                    (const_int 0)))]
3922 
  "")
3923 
 
3924 
(define_insn "*maskir_internal8"
3925 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3926 
        (compare:CC
3927 
         (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3928 
                         (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3929 
                 (and:SI (not:SI (match_dup 2))
3930 
                         (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3931 
         (const_int 0)))
3932 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3933 
        (ior:SI (and:SI (match_dup 3) (match_dup 2))
3934 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3935 
  "TARGET_POWER"
3936 
  "@
3937 
   maskir. %0,%3,%2
3938 
   #"
3939 
  [(set_attr "type" "compare")
3940 
   (set_attr "length" "4,8")])
3941 
 
3942 
(define_split
3943 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3944 
        (compare:CC
3945 
         (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3946 
                         (match_operand:SI 2 "gpc_reg_operand" ""))
3947 
                 (and:SI (not:SI (match_dup 2))
3948 
                         (match_operand:SI 1 "gpc_reg_operand" "")))
3949 
         (const_int 0)))
3950 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
3951 
        (ior:SI (and:SI (match_dup 3) (match_dup 2))
3952 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3953 
  "TARGET_POWER && reload_completed"
3954 
  [(set (match_dup 0)
3955 
        (ior:SI (and:SI (match_dup 3) (match_dup 2))
3956 
                (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3957 
   (set (match_dup 4)
3958 
        (compare:CC (match_dup 0)
3959 
                    (const_int 0)))]
3960 
  "")
3961 
 
3962 
;; Rotate and shift insns, in all their variants.  These support shifts,
3963 
;; field inserts and extracts, and various combinations thereof.
3964 
(define_expand "insv"
3965 
  [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3966 
                       (match_operand:SI 1 "const_int_operand" "")
3967 
                       (match_operand:SI 2 "const_int_operand" ""))
3968 
        (match_operand 3 "gpc_reg_operand" ""))]
3969 
  ""
3970 
  "
3971 
{
3972 
  /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3973 
     the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3974 
     compiler if the address of the structure is taken later.  Likewise, do
3975 
     not handle invalid E500 subregs.  */
3976 
  if (GET_CODE (operands[0]) == SUBREG
3977 
      && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3978 
          || ((TARGET_E500_DOUBLE || TARGET_SPE)
3979 
              && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3980 
    FAIL;
3981 
 
3982 
  if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3983 
    emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3984 
  else
3985 
    emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3986 
  DONE;
3987 
}")
3988 
 
3989 
(define_insn "insvsi"
3990 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3991 
                         (match_operand:SI 1 "const_int_operand" "i")
3992 
                         (match_operand:SI 2 "const_int_operand" "i"))
3993 
        (match_operand:SI 3 "gpc_reg_operand" "r"))]
3994 
  ""
3995 
  "*
3996 
{
3997 
  int start = INTVAL (operands[2]) & 31;
3998 
  int size = INTVAL (operands[1]) & 31;
3999 
 
4000 
  operands[4] = GEN_INT (32 - start - size);
4001 
  operands[1] = GEN_INT (start + size - 1);
4002 
  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4003 
}"
4004 
  [(set_attr "type" "insert_word")])
4005 
 
4006 
(define_insn "*insvsi_internal1"
4007 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4008 
                         (match_operand:SI 1 "const_int_operand" "i")
4009 
                         (match_operand:SI 2 "const_int_operand" "i"))
4010 
        (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4011 
                   (match_operand:SI 4 "const_int_operand" "i")))]
4012 
  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4013 
  "*
4014 
{
4015 
  int shift = INTVAL (operands[4]) & 31;
4016 
  int start = INTVAL (operands[2]) & 31;
4017 
  int size = INTVAL (operands[1]) & 31;
4018 
 
4019 
  operands[4] = GEN_INT (shift - start - size);
4020 
  operands[1] = GEN_INT (start + size - 1);
4021 
  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4022 
}"
4023 
  [(set_attr "type" "insert_word")])
4024 
 
4025 
(define_insn "*insvsi_internal2"
4026 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4027 
                         (match_operand:SI 1 "const_int_operand" "i")
4028 
                         (match_operand:SI 2 "const_int_operand" "i"))
4029 
        (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4030 
                     (match_operand:SI 4 "const_int_operand" "i")))]
4031 
  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4032 
  "*
4033 
{
4034 
  int shift = INTVAL (operands[4]) & 31;
4035 
  int start = INTVAL (operands[2]) & 31;
4036 
  int size = INTVAL (operands[1]) & 31;
4037 
 
4038 
  operands[4] = GEN_INT (32 - shift - start - size);
4039 
  operands[1] = GEN_INT (start + size - 1);
4040 
  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4041 
}"
4042 
  [(set_attr "type" "insert_word")])
4043 
 
4044 
(define_insn "*insvsi_internal3"
4045 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4046 
                         (match_operand:SI 1 "const_int_operand" "i")
4047 
                         (match_operand:SI 2 "const_int_operand" "i"))
4048 
        (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4049 
                     (match_operand:SI 4 "const_int_operand" "i")))]
4050 
  "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4051 
  "*
4052 
{
4053 
  int shift = INTVAL (operands[4]) & 31;
4054 
  int start = INTVAL (operands[2]) & 31;
4055 
  int size = INTVAL (operands[1]) & 31;
4056 
 
4057 
  operands[4] = GEN_INT (32 - shift - start - size);
4058 
  operands[1] = GEN_INT (start + size - 1);
4059 
  return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4060 
}"
4061 
  [(set_attr "type" "insert_word")])
4062 
 
4063 
(define_insn "*insvsi_internal4"
4064 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4065 
                         (match_operand:SI 1 "const_int_operand" "i")
4066 
                         (match_operand:SI 2 "const_int_operand" "i"))
4067 
        (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4068 
                         (match_operand:SI 4 "const_int_operand" "i")
4069 
                         (match_operand:SI 5 "const_int_operand" "i")))]
4070 
  "INTVAL (operands[4]) >= INTVAL (operands[1])"
4071 
  "*
4072 
{
4073 
  int extract_start = INTVAL (operands[5]) & 31;
4074 
  int extract_size = INTVAL (operands[4]) & 31;
4075 
  int insert_start = INTVAL (operands[2]) & 31;
4076 
  int insert_size = INTVAL (operands[1]) & 31;
4077 
 
4078 
/* Align extract field with insert field */
4079 
  operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4080 
  operands[1] = GEN_INT (insert_start + insert_size - 1);
4081 
  return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4082 
}"
4083 
  [(set_attr "type" "insert_word")])
4084 
 
4085 
;; combine patterns for rlwimi
4086 
(define_insn "*insvsi_internal5"
4087 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4088 
        (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4089 
                        (match_operand:SI 1 "mask_operand" "i"))
4090 
                (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4091 
                                     (match_operand:SI 2 "const_int_operand" "i"))
4092 
                        (match_operand:SI 5 "mask_operand" "i"))))]
4093 
  "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4094 
  "*
4095 
{
4096 
 int me = extract_ME(operands[5]);
4097 
 int mb = extract_MB(operands[5]);
4098 
 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4099 
 operands[2] = GEN_INT(mb);
4100 
 operands[1] = GEN_INT(me);
4101 
 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4102 
}"
4103 
  [(set_attr "type" "insert_word")])
4104 
 
4105 
(define_insn "*insvsi_internal6"
4106 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4107 
        (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4108 
                                     (match_operand:SI 2 "const_int_operand" "i"))
4109 
                        (match_operand:SI 5 "mask_operand" "i"))
4110 
                (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4111 
                        (match_operand:SI 1 "mask_operand" "i"))))]
4112 
  "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4113 
  "*
4114 
{
4115 
 int me = extract_ME(operands[5]);
4116 
 int mb = extract_MB(operands[5]);
4117 
 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4118 
 operands[2] = GEN_INT(mb);
4119 
 operands[1] = GEN_INT(me);
4120 
 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4121 
}"
4122 
  [(set_attr "type" "insert_word")])
4123 
 
4124 
(define_insn "insvdi"
4125 
  [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4126 
                         (match_operand:SI 1 "const_int_operand" "i")
4127 
                         (match_operand:SI 2 "const_int_operand" "i"))
4128 
        (match_operand:DI 3 "gpc_reg_operand" "r"))]
4129 
  "TARGET_POWERPC64"
4130 
  "*
4131 
{
4132 
  int start = INTVAL (operands[2]) & 63;
4133 
  int size = INTVAL (operands[1]) & 63;
4134 
 
4135 
  operands[1] = GEN_INT (64 - start - size);
4136 
  return \"rldimi %0,%3,%H1,%H2\";
4137 
}"
4138 
  [(set_attr "type" "insert_dword")])
4139 
 
4140 
(define_insn "*insvdi_internal2"
4141 
  [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4142 
                         (match_operand:SI 1 "const_int_operand" "i")
4143 
                         (match_operand:SI 2 "const_int_operand" "i"))
4144 
        (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4145 
                     (match_operand:SI 4 "const_int_operand" "i")))]
4146 
  "TARGET_POWERPC64
4147 
   && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4148 
  "*
4149 
{
4150 
  int shift = INTVAL (operands[4]) & 63;
4151 
  int start = (INTVAL (operands[2]) & 63) - 32;
4152 
  int size = INTVAL (operands[1]) & 63;
4153 
 
4154 
  operands[4] = GEN_INT (64 - shift - start - size);
4155 
  operands[2] = GEN_INT (start);
4156 
  operands[1] = GEN_INT (start + size - 1);
4157 
  return \"rlwimi %0,%3,%h4,%h2,%h1\";
4158 
}")
4159 
 
4160 
(define_insn "*insvdi_internal3"
4161 
  [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4162 
                         (match_operand:SI 1 "const_int_operand" "i")
4163 
                         (match_operand:SI 2 "const_int_operand" "i"))
4164 
        (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4165 
                     (match_operand:SI 4 "const_int_operand" "i")))]
4166 
  "TARGET_POWERPC64
4167 
   && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4168 
  "*
4169 
{
4170 
  int shift = INTVAL (operands[4]) & 63;
4171 
  int start = (INTVAL (operands[2]) & 63) - 32;
4172 
  int size = INTVAL (operands[1]) & 63;
4173 
 
4174 
  operands[4] = GEN_INT (64 - shift - start - size);
4175 
  operands[2] = GEN_INT (start);
4176 
  operands[1] = GEN_INT (start + size - 1);
4177 
  return \"rlwimi %0,%3,%h4,%h2,%h1\";
4178 
}")
4179 
 
4180 
(define_expand "extzv"
4181 
  [(set (match_operand 0 "gpc_reg_operand" "")
4182 
        (zero_extract (match_operand 1 "gpc_reg_operand" "")
4183 
                       (match_operand:SI 2 "const_int_operand" "")
4184 
                       (match_operand:SI 3 "const_int_operand" "")))]
4185 
  ""
4186 
  "
4187 
{
4188 
  /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4189 
     the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4190 
     compiler if the address of the structure is taken later.  */
4191 
  if (GET_CODE (operands[0]) == SUBREG
4192 
      && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4193 
    FAIL;
4194 
 
4195 
  if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4196 
    emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4197 
  else
4198 
    emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4199 
  DONE;
4200 
}")
4201 
 
4202 
(define_insn "extzvsi"
4203 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4204 
        (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4205 
                         (match_operand:SI 2 "const_int_operand" "i")
4206 
                         (match_operand:SI 3 "const_int_operand" "i")))]
4207 
  ""
4208 
  "*
4209 
{
4210 
  int start = INTVAL (operands[3]) & 31;
4211 
  int size = INTVAL (operands[2]) & 31;
4212 
 
4213 
  if (start + size >= 32)
4214 
    operands[3] = const0_rtx;
4215 
  else
4216 
    operands[3] = GEN_INT (start + size);
4217 
  return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4218 
}")
4219 
 
4220 
(define_insn "*extzvsi_internal1"
4221 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4222 
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4223 
                         (match_operand:SI 2 "const_int_operand" "i,i")
4224 
                         (match_operand:SI 3 "const_int_operand" "i,i"))
4225 
                    (const_int 0)))
4226 
   (clobber (match_scratch:SI 4 "=r,r"))]
4227 
  ""
4228 
  "*
4229 
{
4230 
  int start = INTVAL (operands[3]) & 31;
4231 
  int size = INTVAL (operands[2]) & 31;
4232 
 
4233 
  /* Force split for non-cc0 compare.  */
4234 
  if (which_alternative == 1)
4235 
     return \"#\";
4236 
 
4237 
  /* If the bit-field being tested fits in the upper or lower half of a
4238 
     word, it is possible to use andiu. or andil. to test it.  This is
4239 
     useful because the condition register set-use delay is smaller for
4240 
     andi[ul]. than for rlinm.  This doesn't work when the starting bit
4241 
     position is 0 because the LT and GT bits may be set wrong.  */
4242 
 
4243 
  if ((start > 0 && start + size <= 16) || start >= 16)
4244 
    {
4245 
      operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4246 
                              - (1 << (16 - (start & 15) - size))));
4247 
      if (start < 16)
4248 
        return \"{andiu.|andis.} %4,%1,%3\";
4249 
      else
4250 
        return \"{andil.|andi.} %4,%1,%3\";
4251 
    }
4252 
 
4253 
  if (start + size >= 32)
4254 
    operands[3] = const0_rtx;
4255 
  else
4256 
    operands[3] = GEN_INT (start + size);
4257 
  return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4258 
}"
4259 
  [(set_attr "type" "delayed_compare")
4260 
   (set_attr "length" "4,8")])
4261 
 
4262 
(define_split
4263 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4264 
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4265 
                         (match_operand:SI 2 "const_int_operand" "")
4266 
                         (match_operand:SI 3 "const_int_operand" ""))
4267 
                    (const_int 0)))
4268 
   (clobber (match_scratch:SI 4 ""))]
4269 
  "reload_completed"
4270 
  [(set (match_dup 4)
4271 
        (zero_extract:SI (match_dup 1) (match_dup 2)
4272 
                         (match_dup 3)))
4273 
   (set (match_dup 0)
4274 
        (compare:CC (match_dup 4)
4275 
                    (const_int 0)))]
4276 
  "")
4277 
 
4278 
(define_insn "*extzvsi_internal2"
4279 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4280 
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4281 
                         (match_operand:SI 2 "const_int_operand" "i,i")
4282 
                         (match_operand:SI 3 "const_int_operand" "i,i"))
4283 
                    (const_int 0)))
4284 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4285 
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4286 
  ""
4287 
  "*
4288 
{
4289 
  int start = INTVAL (operands[3]) & 31;
4290 
  int size = INTVAL (operands[2]) & 31;
4291 
 
4292 
  /* Force split for non-cc0 compare.  */
4293 
  if (which_alternative == 1)
4294 
     return \"#\";
4295 
 
4296 
  /* Since we are using the output value, we can't ignore any need for
4297 
     a shift.  The bit-field must end at the LSB.  */
4298 
  if (start >= 16 && start + size == 32)
4299 
    {
4300 
      operands[3] = GEN_INT ((1 << size) - 1);
4301 
      return \"{andil.|andi.} %0,%1,%3\";
4302 
    }
4303 
 
4304 
  if (start + size >= 32)
4305 
    operands[3] = const0_rtx;
4306 
  else
4307 
    operands[3] = GEN_INT (start + size);
4308 
  return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4309 
}"
4310 
  [(set_attr "type" "delayed_compare")
4311 
   (set_attr "length" "4,8")])
4312 
 
4313 
(define_split
4314 
  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4315 
        (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4316 
                         (match_operand:SI 2 "const_int_operand" "")
4317 
                         (match_operand:SI 3 "const_int_operand" ""))
4318 
                    (const_int 0)))
4319 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4320 
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4321 
  "reload_completed"
4322 
  [(set (match_dup 0)
4323 
        (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4324 
   (set (match_dup 4)
4325 
        (compare:CC (match_dup 0)
4326 
                    (const_int 0)))]
4327 
  "")
4328 
 
4329 
(define_insn "extzvdi"
4330 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4331 
        (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4332 
                         (match_operand:SI 2 "const_int_operand" "i")
4333 
                         (match_operand:SI 3 "const_int_operand" "i")))]
4334 
  "TARGET_POWERPC64"
4335 
  "*
4336 
{
4337 
  int start = INTVAL (operands[3]) & 63;
4338 
  int size = INTVAL (operands[2]) & 63;
4339 
 
4340 
  if (start + size >= 64)
4341 
    operands[3] = const0_rtx;
4342 
  else
4343 
    operands[3] = GEN_INT (start + size);
4344 
  operands[2] = GEN_INT (64 - size);
4345 
  return \"rldicl %0,%1,%3,%2\";
4346 
}")
4347 
 
4348 
(define_insn "*extzvdi_internal1"
4349 
  [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4350 
        (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4351 
                         (match_operand:SI 2 "const_int_operand" "i")
4352 
                         (match_operand:SI 3 "const_int_operand" "i"))
4353 
                    (const_int 0)))
4354 
   (clobber (match_scratch:DI 4 "=r"))]
4355 
  "TARGET_64BIT && rs6000_gen_cell_microcode"
4356 
  "*
4357 
{
4358 
  int start = INTVAL (operands[3]) & 63;
4359 
  int size = INTVAL (operands[2]) & 63;
4360 
 
4361 
  if (start + size >= 64)
4362 
    operands[3] = const0_rtx;
4363 
  else
4364 
    operands[3] = GEN_INT (start + size);
4365 
  operands[2] = GEN_INT (64 - size);
4366 
  return \"rldicl. %4,%1,%3,%2\";
4367 
}"
4368 
  [(set_attr "type" "compare")])
4369 
 
4370 
(define_insn "*extzvdi_internal2"
4371 
  [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4372 
        (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4373 
                         (match_operand:SI 2 "const_int_operand" "i")
4374 
                         (match_operand:SI 3 "const_int_operand" "i"))
4375 
                    (const_int 0)))
4376 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4377 
        (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4378 
  "TARGET_64BIT && rs6000_gen_cell_microcode"
4379 
  "*
4380 
{
4381 
  int start = INTVAL (operands[3]) & 63;
4382 
  int size = INTVAL (operands[2]) & 63;
4383 
 
4384 
  if (start + size >= 64)
4385 
    operands[3] = const0_rtx;
4386 
  else
4387 
    operands[3] = GEN_INT (start + size);
4388 
  operands[2] = GEN_INT (64 - size);
4389 
  return \"rldicl. %0,%1,%3,%2\";
4390 
}"
4391 
  [(set_attr "type" "compare")])
4392 
 
4393 
(define_insn "rotlsi3"
4394 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4395 
        (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4396 
                   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4397 
  ""
4398 
  "@
4399 
   {rlnm|rlwnm} %0,%1,%2,0xffffffff
4400 
   {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4401 
  [(set_attr "type" "var_shift_rotate,integer")])
4402 
 
4403 
(define_insn "*rotlsi3_64"
4404 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4405 
        (zero_extend:DI
4406 
            (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4407 
                       (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4408 
  "TARGET_64BIT"
4409 
  "@
4410 
   {rlnm|rlwnm} %0,%1,%2,0xffffffff
4411 
   {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4412 
  [(set_attr "type" "var_shift_rotate,integer")])
4413 
 
4414 
(define_insn "*rotlsi3_internal2"
4415 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4416 
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4417 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4418 
                    (const_int 0)))
4419 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4420 
  ""
4421 
  "@
4422 
   {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4423 
   {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4424 
   #
4425 
   #"
4426 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4427 
   (set_attr "length" "4,4,8,8")])
4428 
 
4429 
(define_split
4430 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4431 
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4432 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4433 
                    (const_int 0)))
4434 
   (clobber (match_scratch:SI 3 ""))]
4435 
  "reload_completed"
4436 
  [(set (match_dup 3)
4437 
        (rotate:SI (match_dup 1) (match_dup 2)))
4438 
   (set (match_dup 0)
4439 
        (compare:CC (match_dup 3)
4440 
                    (const_int 0)))]
4441 
  "")
4442 
 
4443 
(define_insn "*rotlsi3_internal3"
4444 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4445 
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4446 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4447 
                    (const_int 0)))
4448 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4449 
        (rotate:SI (match_dup 1) (match_dup 2)))]
4450 
  ""
4451 
  "@
4452 
   {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4453 
   {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4454 
   #
4455 
   #"
4456 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4457 
   (set_attr "length" "4,4,8,8")])
4458 
 
4459 
(define_split
4460 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4461 
        (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4462 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4463 
                    (const_int 0)))
4464 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4465 
        (rotate:SI (match_dup 1) (match_dup 2)))]
4466 
  "reload_completed"
4467 
  [(set (match_dup 0)
4468 
        (rotate:SI (match_dup 1) (match_dup 2)))
4469 
   (set (match_dup 3)
4470 
        (compare:CC (match_dup 0)
4471 
                    (const_int 0)))]
4472 
  "")
4473 
 
4474 
(define_insn "*rotlsi3_internal4"
4475 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4476 
        (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4477 
                           (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4478 
                (match_operand:SI 3 "mask_operand" "n,n")))]
4479 
  ""
4480 
  "@
4481 
   {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4482 
   {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4483 
  [(set_attr "type" "var_shift_rotate,integer")])
4484 
 
4485 
(define_insn "*rotlsi3_internal5"
4486 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4487 
        (compare:CC (and:SI
4488 
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4489 
                                (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4490 
                     (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4491 
                    (const_int 0)))
4492 
   (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4493 
  ""
4494 
  "@
4495 
   {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4496 
   {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4497 
   #
4498 
   #"
4499 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4500 
   (set_attr "length" "4,4,8,8")])
4501 
 
4502 
(define_split
4503 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4504 
        (compare:CC (and:SI
4505 
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4506 
                                (match_operand:SI 2 "reg_or_cint_operand" ""))
4507 
                     (match_operand:SI 3 "mask_operand" ""))
4508 
                    (const_int 0)))
4509 
   (clobber (match_scratch:SI 4 ""))]
4510 
  "reload_completed"
4511 
  [(set (match_dup 4)
4512 
        (and:SI (rotate:SI (match_dup 1)
4513 
                                (match_dup 2))
4514 
                     (match_dup 3)))
4515 
   (set (match_dup 0)
4516 
        (compare:CC (match_dup 4)
4517 
                    (const_int 0)))]
4518 
  "")
4519 
 
4520 
(define_insn "*rotlsi3_internal6"
4521 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4522 
        (compare:CC (and:SI
4523 
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4524 
                                (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4525 
                     (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4526 
                    (const_int 0)))
4527 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4528 
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4529 
  ""
4530 
  "@
4531 
   {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4532 
   {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4533 
   #
4534 
   #"
4535 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4536 
   (set_attr "length" "4,4,8,8")])
4537 
 
4538 
(define_split
4539 
  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4540 
        (compare:CC (and:SI
4541 
                     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4542 
                                (match_operand:SI 2 "reg_or_cint_operand" ""))
4543 
                     (match_operand:SI 3 "mask_operand" ""))
4544 
                    (const_int 0)))
4545 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4546 
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4547 
  "reload_completed"
4548 
  [(set (match_dup 0)
4549 
        (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4550 
   (set (match_dup 4)
4551 
        (compare:CC (match_dup 0)
4552 
                    (const_int 0)))]
4553 
  "")
4554 
 
4555 
(define_insn "*rotlsi3_internal7"
4556 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4557 
        (zero_extend:SI
4558 
         (subreg:QI
4559 
          (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4560 
                     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4561 
  ""
4562 
  "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4563 
  [(set (attr "cell_micro")
4564 
     (if_then_else (match_operand:SI 2 "const_int_operand" "")
4565 
        (const_string "not")
4566 
        (const_string "always")))])
4567 
 
4568 
(define_insn "*rotlsi3_internal8"
4569 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4570 
        (compare:CC (zero_extend:SI
4571 
                     (subreg:QI
4572 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4573 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4574 
                    (const_int 0)))
4575 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4576 
  ""
4577 
  "@
4578 
   {rlnm.|rlwnm.} %3,%1,%2,0xff
4579 
   {rlinm.|rlwinm.} %3,%1,%h2,0xff
4580 
   #
4581 
   #"
4582 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4583 
   (set_attr "length" "4,4,8,8")])
4584 
 
4585 
(define_split
4586 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4587 
        (compare:CC (zero_extend:SI
4588 
                     (subreg:QI
4589 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4590 
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4591 
                    (const_int 0)))
4592 
   (clobber (match_scratch:SI 3 ""))]
4593 
  "reload_completed"
4594 
  [(set (match_dup 3)
4595 
        (zero_extend:SI (subreg:QI
4596 
                      (rotate:SI (match_dup 1)
4597 
                                 (match_dup 2)) 0)))
4598 
   (set (match_dup 0)
4599 
        (compare:CC (match_dup 3)
4600 
                    (const_int 0)))]
4601 
  "")
4602 
 
4603 
(define_insn "*rotlsi3_internal9"
4604 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4605 
        (compare:CC (zero_extend:SI
4606 
                     (subreg:QI
4607 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4608 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4609 
                    (const_int 0)))
4610 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4611 
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4612 
  ""
4613 
  "@
4614 
   {rlnm.|rlwnm.} %0,%1,%2,0xff
4615 
   {rlinm.|rlwinm.} %0,%1,%h2,0xff
4616 
   #
4617 
   #"
4618 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4619 
   (set_attr "length" "4,4,8,8")])
4620 
 
4621 
(define_split
4622 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4623 
        (compare:CC (zero_extend:SI
4624 
                     (subreg:QI
4625 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4626 
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4627 
                    (const_int 0)))
4628 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4629 
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4630 
  "reload_completed"
4631 
  [(set (match_dup 0)
4632 
        (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4633 
   (set (match_dup 3)
4634 
        (compare:CC (match_dup 0)
4635 
                    (const_int 0)))]
4636 
  "")
4637 
 
4638 
(define_insn "*rotlsi3_internal10"
4639 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4640 
        (zero_extend:SI
4641 
         (subreg:HI
4642 
          (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4643 
                     (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4644 
  ""
4645 
  "@
4646 
   {rlnm|rlwnm} %0,%1,%2,0xffff
4647 
   {rlinm|rlwinm} %0,%1,%h2,0xffff"
4648 
  [(set_attr "type" "var_shift_rotate,integer")])
4649 
 
4650 
 
4651 
(define_insn "*rotlsi3_internal11"
4652 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4653 
        (compare:CC (zero_extend:SI
4654 
                     (subreg:HI
4655 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4656 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4657 
                    (const_int 0)))
4658 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4659 
  ""
4660 
  "@
4661 
   {rlnm.|rlwnm.} %3,%1,%2,0xffff
4662 
   {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4663 
   #
4664 
   #"
4665 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4666 
   (set_attr "length" "4,4,8,8")])
4667 
 
4668 
(define_split
4669 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4670 
        (compare:CC (zero_extend:SI
4671 
                     (subreg:HI
4672 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4673 
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4674 
                    (const_int 0)))
4675 
   (clobber (match_scratch:SI 3 ""))]
4676 
  "reload_completed"
4677 
  [(set (match_dup 3)
4678 
        (zero_extend:SI (subreg:HI
4679 
                      (rotate:SI (match_dup 1)
4680 
                                 (match_dup 2)) 0)))
4681 
   (set (match_dup 0)
4682 
        (compare:CC (match_dup 3)
4683 
                    (const_int 0)))]
4684 
  "")
4685 
 
4686 
(define_insn "*rotlsi3_internal12"
4687 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4688 
        (compare:CC (zero_extend:SI
4689 
                     (subreg:HI
4690 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4691 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4692 
                    (const_int 0)))
4693 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4694 
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4695 
  ""
4696 
  "@
4697 
   {rlnm.|rlwnm.} %0,%1,%2,0xffff
4698 
   {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4699 
   #
4700 
   #"
4701 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4702 
   (set_attr "length" "4,4,8,8")])
4703 
 
4704 
(define_split
4705 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4706 
        (compare:CC (zero_extend:SI
4707 
                     (subreg:HI
4708 
                      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4709 
                                 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4710 
                    (const_int 0)))
4711 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4712 
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4713 
  "reload_completed"
4714 
  [(set (match_dup 0)
4715 
        (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4716 
   (set (match_dup 3)
4717 
        (compare:CC (match_dup 0)
4718 
                    (const_int 0)))]
4719 
  "")
4720 
 
4721 
;; Note that we use "sle." instead of "sl." so that we can set
4722 
;; SHIFT_COUNT_TRUNCATED.
4723 
 
4724 
(define_expand "ashlsi3"
4725 
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4726 
   (use (match_operand:SI 1 "gpc_reg_operand" ""))
4727 
   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4728 
  ""
4729 
  "
4730 
{
4731 
  if (TARGET_POWER)
4732 
    emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4733 
  else
4734 
    emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4735 
  DONE;
4736 
}")
4737 
 
4738 
(define_insn "ashlsi3_power"
4739 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4740 
        (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4741 
                   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4742 
   (clobber (match_scratch:SI 3 "=q,X"))]
4743 
  "TARGET_POWER"
4744 
  "@
4745 
   sle %0,%1,%2
4746 
   {sli|slwi} %0,%1,%h2")
4747 
 
4748 
(define_insn "ashlsi3_no_power"
4749 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4750 
        (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4751 
                   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4752 
  "! TARGET_POWER"
4753 
  "@
4754 
   {sl|slw} %0,%1,%2
4755 
   {sli|slwi} %0,%1,%h2"
4756 
  [(set_attr "type" "var_shift_rotate,shift")])
4757 
 
4758 
(define_insn "*ashlsi3_64"
4759 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4760 
        (zero_extend:DI
4761 
            (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4762 
                       (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4763 
  "TARGET_POWERPC64"
4764 
  "@
4765 
   {sl|slw} %0,%1,%2
4766 
   {sli|slwi} %0,%1,%h2"
4767 
  [(set_attr "type" "var_shift_rotate,shift")])
4768 
 
4769 
(define_insn ""
4770 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4771 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4772 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4773 
                    (const_int 0)))
4774 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))
4775 
   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4776 
  "TARGET_POWER"
4777 
  "@
4778 
   sle. %3,%1,%2
4779 
   {sli.|slwi.} %3,%1,%h2
4780 
   #
4781 
   #"
4782 
  [(set_attr "type" "delayed_compare")
4783 
   (set_attr "length" "4,4,8,8")])
4784 
 
4785 
(define_split
4786 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4787 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4788 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4789 
                    (const_int 0)))
4790 
   (clobber (match_scratch:SI 3 ""))
4791 
   (clobber (match_scratch:SI 4 ""))]
4792 
  "TARGET_POWER && reload_completed"
4793 
  [(parallel [(set (match_dup 3)
4794 
        (ashift:SI (match_dup 1) (match_dup 2)))
4795 
   (clobber (match_dup 4))])
4796 
   (set (match_dup 0)
4797 
        (compare:CC (match_dup 3)
4798 
                    (const_int 0)))]
4799 
  "")
4800 
 
4801 
(define_insn ""
4802 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4803 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4804 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4805 
                    (const_int 0)))
4806 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4807 
  "! TARGET_POWER && TARGET_32BIT"
4808 
  "@
4809 
   {sl.|slw.} %3,%1,%2
4810 
   {sli.|slwi.} %3,%1,%h2
4811 
   #
4812 
   #"
4813 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4814 
   (set_attr "length" "4,4,8,8")])
4815 
 
4816 
(define_split
4817 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4818 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4819 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4820 
                    (const_int 0)))
4821 
   (clobber (match_scratch:SI 3 ""))]
4822 
  "! TARGET_POWER && TARGET_32BIT && reload_completed"
4823 
  [(set (match_dup 3)
4824 
        (ashift:SI (match_dup 1) (match_dup 2)))
4825 
   (set (match_dup 0)
4826 
        (compare:CC (match_dup 3)
4827 
                    (const_int 0)))]
4828 
  "")
4829 
 
4830 
(define_insn ""
4831 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4832 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4833 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4834 
                    (const_int 0)))
4835 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4836 
        (ashift:SI (match_dup 1) (match_dup 2)))
4837 
   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4838 
  "TARGET_POWER"
4839 
  "@
4840 
   sle. %0,%1,%2
4841 
   {sli.|slwi.} %0,%1,%h2
4842 
   #
4843 
   #"
4844 
  [(set_attr "type" "delayed_compare")
4845 
   (set_attr "length" "4,4,8,8")])
4846 
 
4847 
(define_split
4848 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4849 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4850 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4851 
                    (const_int 0)))
4852 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4853 
        (ashift:SI (match_dup 1) (match_dup 2)))
4854 
   (clobber (match_scratch:SI 4 ""))]
4855 
  "TARGET_POWER && reload_completed"
4856 
  [(parallel [(set (match_dup 0)
4857 
        (ashift:SI (match_dup 1) (match_dup 2)))
4858 
   (clobber (match_dup 4))])
4859 
   (set (match_dup 3)
4860 
        (compare:CC (match_dup 0)
4861 
                    (const_int 0)))]
4862 
  "")
4863 
 
4864 
(define_insn ""
4865 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4866 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4867 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4868 
                    (const_int 0)))
4869 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4870 
        (ashift:SI (match_dup 1) (match_dup 2)))]
4871 
  "! TARGET_POWER && TARGET_32BIT"
4872 
  "@
4873 
   {sl.|slw.} %0,%1,%2
4874 
   {sli.|slwi.} %0,%1,%h2
4875 
   #
4876 
   #"
4877 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4878 
   (set_attr "length" "4,4,8,8")])
4879 
 
4880 
(define_split
4881 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4882 
        (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4883 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
4884 
                    (const_int 0)))
4885 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4886 
        (ashift:SI (match_dup 1) (match_dup 2)))]
4887 
  "! TARGET_POWER && TARGET_32BIT && reload_completed"
4888 
  [(set (match_dup 0)
4889 
        (ashift:SI (match_dup 1) (match_dup 2)))
4890 
   (set (match_dup 3)
4891 
        (compare:CC (match_dup 0)
4892 
                    (const_int 0)))]
4893 
  "")
4894 
 
4895 
(define_insn "rlwinm"
4896 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4897 
        (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4898 
                           (match_operand:SI 2 "const_int_operand" "i"))
4899 
                (match_operand:SI 3 "mask_operand" "n")))]
4900 
  "includes_lshift_p (operands[2], operands[3])"
4901 
  "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4902 
 
4903 
(define_insn ""
4904 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4905 
        (compare:CC
4906 
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4907 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
4908 
                 (match_operand:SI 3 "mask_operand" "n,n"))
4909 
         (const_int 0)))
4910 
   (clobber (match_scratch:SI 4 "=r,r"))]
4911 
  "includes_lshift_p (operands[2], operands[3])"
4912 
  "@
4913 
   {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4914 
   #"
4915 
  [(set_attr "type" "delayed_compare")
4916 
   (set_attr "length" "4,8")])
4917 
 
4918 
(define_split
4919 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4920 
        (compare:CC
4921 
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4922 
                            (match_operand:SI 2 "const_int_operand" ""))
4923 
                 (match_operand:SI 3 "mask_operand" ""))
4924 
         (const_int 0)))
4925 
   (clobber (match_scratch:SI 4 ""))]
4926 
  "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4927 
  [(set (match_dup 4)
4928 
        (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4929 
                 (match_dup 3)))
4930 
   (set (match_dup 0)
4931 
        (compare:CC (match_dup 4)
4932 
                    (const_int 0)))]
4933 
  "")
4934 
 
4935 
(define_insn ""
4936 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4937 
        (compare:CC
4938 
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4939 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
4940 
                 (match_operand:SI 3 "mask_operand" "n,n"))
4941 
         (const_int 0)))
4942 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4943 
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4944 
  "includes_lshift_p (operands[2], operands[3])"
4945 
  "@
4946 
   {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4947 
   #"
4948 
  [(set_attr "type" "delayed_compare")
4949 
   (set_attr "length" "4,8")])
4950 
 
4951 
(define_split
4952 
  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4953 
        (compare:CC
4954 
         (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4955 
                            (match_operand:SI 2 "const_int_operand" ""))
4956 
                 (match_operand:SI 3 "mask_operand" ""))
4957 
         (const_int 0)))
4958 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
4959 
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4960 
  "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4961 
  [(set (match_dup 0)
4962 
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4963 
   (set (match_dup 4)
4964 
        (compare:CC (match_dup 0)
4965 
                    (const_int 0)))]
4966 
  "")
4967 
 
4968 
;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4969 
;; "sli x,x,0".
4970 
(define_expand "lshrsi3"
4971 
  [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4972 
   (use (match_operand:SI 1 "gpc_reg_operand" ""))
4973 
   (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4974 
  ""
4975 
  "
4976 
{
4977 
  if (TARGET_POWER)
4978 
    emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4979 
  else
4980 
    emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4981 
  DONE;
4982 
}")
4983 
 
4984 
(define_insn "lshrsi3_power"
4985 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4986 
        (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4987 
                     (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4988 
   (clobber (match_scratch:SI 3 "=q,X,X"))]
4989 
  "TARGET_POWER"
4990 
  "@
4991 
  sre %0,%1,%2
4992 
  mr %0,%1
4993 
  {s%A2i|s%A2wi} %0,%1,%h2")
4994 
 
4995 
(define_insn "lshrsi3_no_power"
4996 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4997 
        (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4998 
                     (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4999 
  "! TARGET_POWER"
5000 
  "@
5001 
  mr %0,%1
5002 
  {sr|srw} %0,%1,%2
5003 
  {sri|srwi} %0,%1,%h2"
5004 
  [(set_attr "type" "integer,var_shift_rotate,shift")])
5005 
 
5006 
(define_insn "*lshrsi3_64"
5007 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5008 
        (zero_extend:DI
5009 
            (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5010 
                         (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5011 
  "TARGET_POWERPC64"
5012 
  "@
5013 
  {sr|srw} %0,%1,%2
5014 
  {sri|srwi} %0,%1,%h2"
5015 
  [(set_attr "type" "var_shift_rotate,shift")])
5016 
 
5017 
(define_insn ""
5018 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5019 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5020 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5021 
                    (const_int 0)))
5022 
   (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5023 
   (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5024 
  "TARGET_POWER"
5025 
  "@
5026 
  sre. %3,%1,%2
5027 
  mr. %1,%1
5028 
  {s%A2i.|s%A2wi.} %3,%1,%h2
5029 
  #
5030 
  #
5031 
  #"
5032 
  [(set_attr "type" "delayed_compare")
5033 
   (set_attr "length" "4,4,4,8,8,8")])
5034 
 
5035 
(define_split
5036 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5037 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5038 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
5039 
                    (const_int 0)))
5040 
   (clobber (match_scratch:SI 3 ""))
5041 
   (clobber (match_scratch:SI 4 ""))]
5042 
  "TARGET_POWER && reload_completed"
5043 
  [(parallel [(set (match_dup 3)
5044 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
5045 
   (clobber (match_dup 4))])
5046 
   (set (match_dup 0)
5047 
        (compare:CC (match_dup 3)
5048 
                    (const_int 0)))]
5049 
  "")
5050 
 
5051 
(define_insn ""
5052 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5053 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5054 
                                 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5055 
                    (const_int 0)))
5056 
   (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5057 
  "! TARGET_POWER && TARGET_32BIT"
5058 
  "@
5059 
   mr. %1,%1
5060 
   {sr.|srw.} %3,%1,%2
5061 
   {sri.|srwi.} %3,%1,%h2
5062 
   #
5063 
   #
5064 
   #"
5065 
  [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5066 
   (set_attr "length" "4,4,4,8,8,8")])
5067 
 
5068 
(define_split
5069 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5070 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5071 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
5072 
                    (const_int 0)))
5073 
   (clobber (match_scratch:SI 3 ""))]
5074 
  "! TARGET_POWER && TARGET_32BIT && reload_completed"
5075 
  [(set (match_dup 3)
5076 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
5077 
   (set (match_dup 0)
5078 
        (compare:CC (match_dup 3)
5079 
                    (const_int 0)))]
5080 
  "")
5081 
 
5082 
(define_insn ""
5083 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5084 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5085 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5086 
                    (const_int 0)))
5087 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5088 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
5089 
   (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5090 
  "TARGET_POWER"
5091 
  "@
5092 
  sre. %0,%1,%2
5093 
  mr. %0,%1
5094 
  {s%A2i.|s%A2wi.} %0,%1,%h2
5095 
  #
5096 
  #
5097 
  #"
5098 
  [(set_attr "type" "delayed_compare")
5099 
   (set_attr "length" "4,4,4,8,8,8")])
5100 
 
5101 
(define_split
5102 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5103 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5104 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
5105 
                    (const_int 0)))
5106 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
5107 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
5108 
   (clobber (match_scratch:SI 4 ""))]
5109 
  "TARGET_POWER && reload_completed"
5110 
  [(parallel [(set (match_dup 0)
5111 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
5112 
   (clobber (match_dup 4))])
5113 
   (set (match_dup 3)
5114 
        (compare:CC (match_dup 0)
5115 
                    (const_int 0)))]
5116 
  "")
5117 
 
5118 
(define_insn ""
5119 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5120 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5121 
                                 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5122 
                    (const_int 0)))
5123 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5124 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5125 
  "! TARGET_POWER && TARGET_32BIT"
5126 
  "@
5127 
   mr. %0,%1
5128 
   {sr.|srw.} %0,%1,%2
5129 
   {sri.|srwi.} %0,%1,%h2
5130 
   #
5131 
   #
5132 
   #"
5133 
  [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5134 
   (set_attr "length" "4,4,4,8,8,8")])
5135 
 
5136 
(define_split
5137 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5138 
        (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5139 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
5140 
                    (const_int 0)))
5141 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
5142 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5143 
  "! TARGET_POWER && TARGET_32BIT && reload_completed"
5144 
  [(set (match_dup 0)
5145 
        (lshiftrt:SI (match_dup 1) (match_dup 2)))
5146 
   (set (match_dup 3)
5147 
        (compare:CC (match_dup 0)
5148 
                    (const_int 0)))]
5149 
  "")
5150 
 
5151 
(define_insn ""
5152 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5153 
        (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5154 
                             (match_operand:SI 2 "const_int_operand" "i"))
5155 
                (match_operand:SI 3 "mask_operand" "n")))]
5156 
  "includes_rshift_p (operands[2], operands[3])"
5157 
  "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5158 
 
5159 
(define_insn ""
5160 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5161 
        (compare:CC
5162 
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5163 
                              (match_operand:SI 2 "const_int_operand" "i,i"))
5164 
                 (match_operand:SI 3 "mask_operand" "n,n"))
5165 
         (const_int 0)))
5166 
   (clobber (match_scratch:SI 4 "=r,r"))]
5167 
  "includes_rshift_p (operands[2], operands[3])"
5168 
  "@
5169 
   {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5170 
   #"
5171 
  [(set_attr "type" "delayed_compare")
5172 
   (set_attr "length" "4,8")])
5173 
 
5174 
(define_split
5175 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5176 
        (compare:CC
5177 
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5178 
                              (match_operand:SI 2 "const_int_operand" ""))
5179 
                 (match_operand:SI 3 "mask_operand" ""))
5180 
         (const_int 0)))
5181 
   (clobber (match_scratch:SI 4 ""))]
5182 
  "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5183 
  [(set (match_dup 4)
5184 
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5185 
                 (match_dup 3)))
5186 
   (set (match_dup 0)
5187 
        (compare:CC (match_dup 4)
5188 
                    (const_int 0)))]
5189 
  "")
5190 
 
5191 
(define_insn ""
5192 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5193 
        (compare:CC
5194 
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5195 
                              (match_operand:SI 2 "const_int_operand" "i,i"))
5196 
                 (match_operand:SI 3 "mask_operand" "n,n"))
5197 
         (const_int 0)))
5198 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5199 
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5200 
  "includes_rshift_p (operands[2], operands[3])"
5201 
  "@
5202 
   {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5203 
   #"
5204 
  [(set_attr "type" "delayed_compare")
5205 
   (set_attr "length" "4,8")])
5206 
 
5207 
(define_split
5208 
  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5209 
        (compare:CC
5210 
         (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5211 
                              (match_operand:SI 2 "const_int_operand" ""))
5212 
                 (match_operand:SI 3 "mask_operand" ""))
5213 
         (const_int 0)))
5214 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
5215 
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5216 
  "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5217 
  [(set (match_dup 0)
5218 
        (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5219 
   (set (match_dup 4)
5220 
        (compare:CC (match_dup 0)
5221 
                    (const_int 0)))]
5222 
  "")
5223 
 
5224 
(define_insn ""
5225 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5226 
        (zero_extend:SI
5227 
         (subreg:QI
5228 
          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5229 
                       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5230 
  "includes_rshift_p (operands[2], GEN_INT (255))"
5231 
  "{rlinm|rlwinm} %0,%1,%s2,0xff")
5232 
 
5233 
(define_insn ""
5234 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5235 
        (compare:CC
5236 
         (zero_extend:SI
5237 
          (subreg:QI
5238 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5239 
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5240 
         (const_int 0)))
5241 
   (clobber (match_scratch:SI 3 "=r,r"))]
5242 
  "includes_rshift_p (operands[2], GEN_INT (255))"
5243 
  "@
5244 
   {rlinm.|rlwinm.} %3,%1,%s2,0xff
5245 
   #"
5246 
  [(set_attr "type" "delayed_compare")
5247 
   (set_attr "length" "4,8")])
5248 
 
5249 
(define_split
5250 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5251 
        (compare:CC
5252 
         (zero_extend:SI
5253 
          (subreg:QI
5254 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5255 
                        (match_operand:SI 2 "const_int_operand" "")) 0))
5256 
         (const_int 0)))
5257 
   (clobber (match_scratch:SI 3 ""))]
5258 
  "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5259 
  [(set (match_dup 3)
5260 
        (zero_extend:SI (subreg:QI
5261 
           (lshiftrt:SI (match_dup 1)
5262 
                        (match_dup 2)) 0)))
5263 
   (set (match_dup 0)
5264 
        (compare:CC (match_dup 3)
5265 
                    (const_int 0)))]
5266 
  "")
5267 
 
5268 
(define_insn ""
5269 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5270 
        (compare:CC
5271 
         (zero_extend:SI
5272 
          (subreg:QI
5273 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5274 
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5275 
         (const_int 0)))
5276 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5277 
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5278 
  "includes_rshift_p (operands[2], GEN_INT (255))"
5279 
  "@
5280 
   {rlinm.|rlwinm.} %0,%1,%s2,0xff
5281 
   #"
5282 
  [(set_attr "type" "delayed_compare")
5283 
   (set_attr "length" "4,8")])
5284 
 
5285 
(define_split
5286 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5287 
        (compare:CC
5288 
         (zero_extend:SI
5289 
          (subreg:QI
5290 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5291 
                        (match_operand:SI 2 "const_int_operand" "")) 0))
5292 
         (const_int 0)))
5293 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
5294 
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5295 
  "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5296 
  [(set (match_dup 0)
5297 
        (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5298 
   (set (match_dup 3)
5299 
        (compare:CC (match_dup 0)
5300 
                    (const_int 0)))]
5301 
  "")
5302 
 
5303 
(define_insn ""
5304 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5305 
        (zero_extend:SI
5306 
         (subreg:HI
5307 
          (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5308 
                       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5309 
  "includes_rshift_p (operands[2], GEN_INT (65535))"
5310 
  "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5311 
 
5312 
(define_insn ""
5313 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5314 
        (compare:CC
5315 
         (zero_extend:SI
5316 
          (subreg:HI
5317 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5318 
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5319 
         (const_int 0)))
5320 
   (clobber (match_scratch:SI 3 "=r,r"))]
5321 
  "includes_rshift_p (operands[2], GEN_INT (65535))"
5322 
  "@
5323 
   {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5324 
   #"
5325 
  [(set_attr "type" "delayed_compare")
5326 
   (set_attr "length" "4,8")])
5327 
 
5328 
(define_split
5329 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5330 
        (compare:CC
5331 
         (zero_extend:SI
5332 
          (subreg:HI
5333 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5334 
                        (match_operand:SI 2 "const_int_operand" "")) 0))
5335 
         (const_int 0)))
5336 
   (clobber (match_scratch:SI 3 ""))]
5337 
  "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5338 
  [(set (match_dup 3)
5339 
        (zero_extend:SI (subreg:HI
5340 
           (lshiftrt:SI (match_dup 1)
5341 
                        (match_dup 2)) 0)))
5342 
   (set (match_dup 0)
5343 
        (compare:CC (match_dup 3)
5344 
                    (const_int 0)))]
5345 
  "")
5346 
 
5347 
(define_insn ""
5348 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5349 
        (compare:CC
5350 
         (zero_extend:SI
5351 
          (subreg:HI
5352 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5353 
                        (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5354 
         (const_int 0)))
5355 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5356 
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5357 
  "includes_rshift_p (operands[2], GEN_INT (65535))"
5358 
  "@
5359 
   {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5360 
   #"
5361 
  [(set_attr "type" "delayed_compare")
5362 
   (set_attr "length" "4,8")])
5363 
 
5364 
(define_split
5365 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5366 
        (compare:CC
5367 
         (zero_extend:SI
5368 
          (subreg:HI
5369 
           (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5370 
                        (match_operand:SI 2 "const_int_operand" "")) 0))
5371 
         (const_int 0)))
5372 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
5373 
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5374 
  "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5375 
  [(set (match_dup 0)
5376 
        (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5377 
   (set (match_dup 3)
5378 
        (compare:CC (match_dup 0)
5379 
                    (const_int 0)))]
5380 
  "")
5381 
 
5382 
(define_insn ""
5383 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5384 
                         (const_int 1)
5385 
                         (match_operand:SI 1 "gpc_reg_operand" "r"))
5386 
        (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5387 
                     (const_int 31)))]
5388 
  "TARGET_POWER"
5389 
  "rrib %0,%1,%2")
5390 
 
5391 
(define_insn ""
5392 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5393 
                         (const_int 1)
5394 
                         (match_operand:SI 1 "gpc_reg_operand" "r"))
5395 
        (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5396 
                     (const_int 31)))]
5397 
  "TARGET_POWER"
5398 
  "rrib %0,%1,%2")
5399 
 
5400 
(define_insn ""
5401 
  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5402 
                         (const_int 1)
5403 
                         (match_operand:SI 1 "gpc_reg_operand" "r"))
5404 
        (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5405 
                         (const_int 1)
5406 
                         (const_int 0)))]
5407 
  "TARGET_POWER"
5408 
  "rrib %0,%1,%2")
5409 
 
5410 
(define_expand "ashrsi3"
5411 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
5412 
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5413 
                     (match_operand:SI 2 "reg_or_cint_operand" "")))]
5414 
  ""
5415 
  "
5416 
{
5417 
  if (TARGET_POWER)
5418 
    emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5419 
  else
5420 
    emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5421 
  DONE;
5422 
}")
5423 
 
5424 
(define_insn "ashrsi3_power"
5425 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5426 
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5427 
                     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5428 
   (clobber (match_scratch:SI 3 "=q,X"))]
5429 
  "TARGET_POWER"
5430 
  "@
5431 
   srea %0,%1,%2
5432 
   {srai|srawi} %0,%1,%h2"
5433 
  [(set_attr "type" "shift")])
5434 
 
5435 
(define_insn "ashrsi3_no_power"
5436 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5437 
        (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5438 
                     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5439 
  "! TARGET_POWER"
5440 
  "@
5441 
   {sra|sraw} %0,%1,%2
5442 
   {srai|srawi} %0,%1,%h2"
5443 
  [(set_attr "type" "var_shift_rotate,shift")])
5444 
 
5445 
(define_insn "*ashrsi3_64"
5446 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5447 
        (sign_extend:DI
5448 
            (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5449 
                         (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5450 
  "TARGET_POWERPC64"
5451 
  "@
5452 
   {sra|sraw} %0,%1,%2
5453 
   {srai|srawi} %0,%1,%h2"
5454 
  [(set_attr "type" "var_shift_rotate,shift")])
5455 
 
5456 
(define_insn ""
5457 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5458 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5459 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5460 
                    (const_int 0)))
5461 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))
5462 
   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5463 
  "TARGET_POWER"
5464 
  "@
5465 
   srea. %3,%1,%2
5466 
   {srai.|srawi.} %3,%1,%h2
5467 
   #
5468 
   #"
5469 
  [(set_attr "type" "delayed_compare")
5470 
   (set_attr "length" "4,4,8,8")])
5471 
 
5472 
(define_split
5473 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5474 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5475 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
5476 
                    (const_int 0)))
5477 
   (clobber (match_scratch:SI 3 ""))
5478 
   (clobber (match_scratch:SI 4 ""))]
5479 
  "TARGET_POWER && reload_completed"
5480 
  [(parallel [(set (match_dup 3)
5481 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
5482 
   (clobber (match_dup 4))])
5483 
   (set (match_dup 0)
5484 
        (compare:CC (match_dup 3)
5485 
                    (const_int 0)))]
5486 
  "")
5487 
 
5488 
(define_insn ""
5489 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5490 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5491 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5492 
                    (const_int 0)))
5493 
   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5494 
  "! TARGET_POWER"
5495 
  "@
5496 
   {sra.|sraw.} %3,%1,%2
5497 
   {srai.|srawi.} %3,%1,%h2
5498 
   #
5499 
   #"
5500 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5501 
   (set_attr "length" "4,4,8,8")])
5502 
 
5503 
(define_split
5504 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5505 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5506 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
5507 
                    (const_int 0)))
5508 
   (clobber (match_scratch:SI 3 ""))]
5509 
  "! TARGET_POWER && reload_completed"
5510 
  [(set (match_dup 3)
5511 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
5512 
   (set (match_dup 0)
5513 
        (compare:CC (match_dup 3)
5514 
                    (const_int 0)))]
5515 
  "")
5516 
 
5517 
(define_insn ""
5518 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5519 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5520 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5521 
                    (const_int 0)))
5522 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5523 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
5524 
   (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5525 
  "TARGET_POWER"
5526 
  "@
5527 
   srea. %0,%1,%2
5528 
   {srai.|srawi.} %0,%1,%h2
5529 
   #
5530 
   #"
5531 
  [(set_attr "type" "delayed_compare")
5532 
   (set_attr "length" "4,4,8,8")])
5533 
 
5534 
(define_split
5535 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5536 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5537 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
5538 
                    (const_int 0)))
5539 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
5540 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
5541 
   (clobber (match_scratch:SI 4 ""))]
5542 
  "TARGET_POWER && reload_completed"
5543 
  [(parallel [(set (match_dup 0)
5544 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
5545 
   (clobber (match_dup 4))])
5546 
   (set (match_dup 3)
5547 
        (compare:CC (match_dup 0)
5548 
                    (const_int 0)))]
5549 
  "")
5550 
 
5551 
(define_insn ""
5552 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5553 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5554 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5555 
                    (const_int 0)))
5556 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5557 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5558 
  "! TARGET_POWER"
5559 
  "@
5560 
   {sra.|sraw.} %0,%1,%2
5561 
   {srai.|srawi.} %0,%1,%h2
5562 
   #
5563 
   #"
5564 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5565 
   (set_attr "length" "4,4,8,8")])
5566 
 
5567 
(define_split
5568 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5569 
        (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5570 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
5571 
                    (const_int 0)))
5572 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
5573 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5574 
  "! TARGET_POWER && reload_completed"
5575 
  [(set (match_dup 0)
5576 
        (ashiftrt:SI (match_dup 1) (match_dup 2)))
5577 
   (set (match_dup 3)
5578 
        (compare:CC (match_dup 0)
5579 
                    (const_int 0)))]
5580 
  "")
5581 
 
5582 
;; Floating-point insns, excluding normal data motion.
5583 
;;
5584 
;; PowerPC has a full set of single-precision floating point instructions.
5585 
;;
5586 
;; For the POWER architecture, we pretend that we have both SFmode and
5587 
;; DFmode insns, while, in fact, all fp insns are actually done in double.
5588 
;; The only conversions we will do will be when storing to memory.  In that
5589 
;; case, we will use the "frsp" instruction before storing.
5590 
;;
5591 
;; Note that when we store into a single-precision memory location, we need to
5592 
;; use the frsp insn first.  If the register being stored isn't dead, we
5593 
;; need a scratch register for the frsp.  But this is difficult when the store
5594 
;; is done by reload.  It is not incorrect to do the frsp on the register in
5595 
;; this case, we just lose precision that we would have otherwise gotten but
5596 
;; is not guaranteed.  Perhaps this should be tightened up at some point.
5597 
 
5598 
(define_expand "extendsfdf2"
5599 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
5600 
        (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5601 
  "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5602 
  "")
5603 
 
5604 
(define_insn_and_split "*extendsfdf2_fpr"
5605 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5606 
        (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5607 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5608 
  "@
5609 
   #
5610 
   fmr %0,%1
5611 
   lfs%U1%X1 %0,%1"
5612 
  "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5613 
  [(const_int 0)]
5614 
{
5615 
  emit_note (NOTE_INSN_DELETED);
5616 
  DONE;
5617 
}
5618 
  [(set_attr "type" "fp,fp,fpload")])
5619 
 
5620 
(define_expand "truncdfsf2"
5621 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5622 
        (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5623 
  "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5624 
  "")
5625 
 
5626 
(define_insn "*truncdfsf2_fpr"
5627 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5628 
        (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5629 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5630 
  "frsp %0,%1"
5631 
  [(set_attr "type" "fp")])
5632 
 
5633 
(define_insn "aux_truncdfsf2"
5634 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5635 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5636 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5637 
  "frsp %0,%1"
5638 
  [(set_attr "type" "fp")])
5639 
 
5640 
(define_expand "negsf2"
5641 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5642 
        (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5643 
  "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5644 
  "")
5645 
 
5646 
(define_insn "*negsf2"
5647 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5648 
        (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5649 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5650 
  "fneg %0,%1"
5651 
  [(set_attr "type" "fp")])
5652 
 
5653 
(define_expand "abssf2"
5654 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5655 
        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5656 
  "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5657 
  "")
5658 
 
5659 
(define_insn "*abssf2"
5660 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5661 
        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5662 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5663 
  "fabs %0,%1"
5664 
  [(set_attr "type" "fp")])
5665 
 
5666 
(define_insn ""
5667 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5668 
        (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5669 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5670 
  "fnabs %0,%1"
5671 
  [(set_attr "type" "fp")])
5672 
 
5673 
(define_expand "addsf3"
5674 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5675 
        (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5676 
                 (match_operand:SF 2 "gpc_reg_operand" "")))]
5677 
  "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5678 
  "")
5679 
 
5680 
(define_insn ""
5681 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5682 
        (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5683 
                 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5684 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5685 
  "fadds %0,%1,%2"
5686 
  [(set_attr "type" "fp")
5687 
   (set_attr "fp_type" "fp_addsub_s")])
5688 
 
5689 
(define_insn ""
5690 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5691 
        (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5692 
                 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5693 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5694 
  "{fa|fadd} %0,%1,%2"
5695 
  [(set_attr "type" "fp")])
5696 
 
5697 
(define_expand "subsf3"
5698 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5699 
        (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5700 
                  (match_operand:SF 2 "gpc_reg_operand" "")))]
5701 
  "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5702 
  "")
5703 
 
5704 
(define_insn ""
5705 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5706 
        (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5707 
                  (match_operand:SF 2 "gpc_reg_operand" "f")))]
5708 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5709 
  "fsubs %0,%1,%2"
5710 
  [(set_attr "type" "fp")
5711 
   (set_attr "fp_type" "fp_addsub_s")])
5712 
 
5713 
(define_insn ""
5714 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5715 
        (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5716 
                  (match_operand:SF 2 "gpc_reg_operand" "f")))]
5717 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5718 
  "{fs|fsub} %0,%1,%2"
5719 
  [(set_attr "type" "fp")])
5720 
 
5721 
(define_expand "mulsf3"
5722 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5723 
        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5724 
                 (match_operand:SF 2 "gpc_reg_operand" "")))]
5725 
  "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5726 
  "")
5727 
 
5728 
(define_insn ""
5729 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5730 
        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5731 
                 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5732 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5733 
  "fmuls %0,%1,%2"
5734 
  [(set_attr "type" "fp")
5735 
   (set_attr "fp_type" "fp_mul_s")])
5736 
 
5737 
(define_insn ""
5738 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5739 
        (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5740 
                 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5741 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5742 
  "{fm|fmul} %0,%1,%2"
5743 
  [(set_attr "type" "dmul")])
5744 
 
5745 
(define_expand "divsf3"
5746 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5747 
        (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5748 
                (match_operand:SF 2 "gpc_reg_operand" "")))]
5749 
  "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5750 
  "")
5751 
 
5752 
(define_insn ""
5753 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5754 
        (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5755 
                (match_operand:SF 2 "gpc_reg_operand" "f")))]
5756 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5757 
   && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5758 
  "fdivs %0,%1,%2"
5759 
  [(set_attr "type" "sdiv")])
5760 
 
5761 
(define_insn ""
5762 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5763 
        (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5764 
                (match_operand:SF 2 "gpc_reg_operand" "f")))]
5765 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5766 
   && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5767 
  "{fd|fdiv} %0,%1,%2"
5768 
  [(set_attr "type" "ddiv")])
5769 
 
5770 
(define_expand "recipsf3"
5771 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5772 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5773 
                    (match_operand:SF 2 "gpc_reg_operand" "f")]
5774 
                   UNSPEC_FRES))]
5775 
  "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5776 
   && flag_finite_math_only && !flag_trapping_math"
5777 
{
5778 
   rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5779 
   DONE;
5780 
})
5781 
 
5782 
(define_insn "fres"
5783 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5784 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5785 
  "TARGET_PPC_GFXOPT && flag_finite_math_only"
5786 
  "fres %0,%1"
5787 
  [(set_attr "type" "fp")])
5788 
 
5789 
(define_insn "*fmaddsf4_powerpc"
5790 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5791 
        (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5792 
                          (match_operand:SF 2 "gpc_reg_operand" "f"))
5793 
                 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5794 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5795 
   && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5796 
  "fmadds %0,%1,%2,%3"
5797 
  [(set_attr "type" "fp")
5798 
   (set_attr "fp_type" "fp_maddsub_s")])
5799 
 
5800 
(define_insn "*fmaddsf4_power"
5801 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5802 
        (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5803 
                          (match_operand:SF 2 "gpc_reg_operand" "f"))
5804 
                 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5805 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5806 
  "{fma|fmadd} %0,%1,%2,%3"
5807 
  [(set_attr "type" "dmul")])
5808 
 
5809 
(define_insn "*fmsubsf4_powerpc"
5810 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5811 
        (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5812 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))
5813 
                  (match_operand:SF 3 "gpc_reg_operand" "f")))]
5814 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5815 
   && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5816 
  "fmsubs %0,%1,%2,%3"
5817 
  [(set_attr "type" "fp")
5818 
   (set_attr "fp_type" "fp_maddsub_s")])
5819 
 
5820 
(define_insn "*fmsubsf4_power"
5821 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5822 
        (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5823 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))
5824 
                  (match_operand:SF 3 "gpc_reg_operand" "f")))]
5825 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5826 
  "{fms|fmsub} %0,%1,%2,%3"
5827 
  [(set_attr "type" "dmul")])
5828 
 
5829 
(define_insn "*fnmaddsf4_powerpc_1"
5830 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5831 
        (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5832 
                                  (match_operand:SF 2 "gpc_reg_operand" "f"))
5833 
                         (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5834 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5835 
   && TARGET_SINGLE_FLOAT"
5836 
  "fnmadds %0,%1,%2,%3"
5837 
  [(set_attr "type" "fp")
5838 
   (set_attr "fp_type" "fp_maddsub_s")])
5839 
 
5840 
(define_insn "*fnmaddsf4_powerpc_2"
5841 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5842 
        (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5843 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))
5844 
                         (match_operand:SF 3 "gpc_reg_operand" "f")))]
5845 
  "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5846 
   && ! HONOR_SIGNED_ZEROS (SFmode)"
5847 
  "fnmadds %0,%1,%2,%3"
5848 
  [(set_attr "type" "fp")
5849 
   (set_attr "fp_type" "fp_maddsub_s")])
5850 
 
5851 
(define_insn "*fnmaddsf4_power_1"
5852 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5853 
        (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5854 
                                  (match_operand:SF 2 "gpc_reg_operand" "f"))
5855 
                         (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5856 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5857 
  "{fnma|fnmadd} %0,%1,%2,%3"
5858 
  [(set_attr "type" "dmul")])
5859 
 
5860 
(define_insn "*fnmaddsf4_power_2"
5861 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5862 
        (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5863 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))
5864 
                         (match_operand:SF 3 "gpc_reg_operand" "f")))]
5865 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5866 
   && ! HONOR_SIGNED_ZEROS (SFmode)"
5867 
  "{fnma|fnmadd} %0,%1,%2,%3"
5868 
  [(set_attr "type" "dmul")])
5869 
 
5870 
(define_insn "*fnmsubsf4_powerpc_1"
5871 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5872 
        (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5873 
                                   (match_operand:SF 2 "gpc_reg_operand" "f"))
5874 
                          (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5875 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5876 
   && TARGET_SINGLE_FLOAT"
5877 
  "fnmsubs %0,%1,%2,%3"
5878 
  [(set_attr "type" "fp")
5879 
   (set_attr "fp_type" "fp_maddsub_s")])
5880 
 
5881 
(define_insn "*fnmsubsf4_powerpc_2"
5882 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5883 
        (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5884 
                  (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5885 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5886 
  "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5887 
   && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5888 
  "fnmsubs %0,%1,%2,%3"
5889 
  [(set_attr "type" "fp")
5890 
   (set_attr "fp_type" "fp_maddsub_s")])
5891 
 
5892 
(define_insn "*fnmsubsf4_power_1"
5893 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5894 
        (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5895 
                                   (match_operand:SF 2 "gpc_reg_operand" "f"))
5896 
                          (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5897 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5898 
  "{fnms|fnmsub} %0,%1,%2,%3"
5899 
  [(set_attr "type" "dmul")])
5900 
 
5901 
(define_insn "*fnmsubsf4_power_2"
5902 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5903 
        (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5904 
                  (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5905 
                           (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5906 
  "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5907 
   && ! HONOR_SIGNED_ZEROS (SFmode)"
5908 
  "{fnms|fnmsub} %0,%1,%2,%3"
5909 
  [(set_attr "type" "dmul")])
5910 
 
5911 
(define_expand "sqrtsf2"
5912 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
5913 
        (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5914 
  "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5915 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5916 
   && !TARGET_SIMPLE_FPU"
5917 
  "")
5918 
 
5919 
(define_insn ""
5920 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5921 
        (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5922 
  "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5923 
   && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5924 
  "fsqrts %0,%1"
5925 
  [(set_attr "type" "ssqrt")])
5926 
 
5927 
(define_insn ""
5928 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5929 
        (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5930 
  "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5931 
   && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5932 
  "fsqrt %0,%1"
5933 
  [(set_attr "type" "dsqrt")])
5934 
 
5935 
(define_expand "rsqrtsf2"
5936 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5937 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5938 
                   UNSPEC_RSQRT))]
5939 
  "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5940 
   && flag_finite_math_only && !flag_trapping_math"
5941 
{
5942 
  rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5943 
  DONE;
5944 
})
5945 
 
5946 
(define_insn "*rsqrt_internal1"
5947 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5948 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5949 
                   UNSPEC_RSQRT))]
5950 
  "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5951 
  "frsqrte %0,%1"
5952 
  [(set_attr "type" "fp")])
5953 
 
5954 
(define_expand "copysignsf3"
5955 
  [(set (match_dup 3)
5956 
        (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5957 
   (set (match_dup 4)
5958 
        (neg:SF (abs:SF (match_dup 1))))
5959 
   (set (match_operand:SF 0 "gpc_reg_operand" "")
5960 
        (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5961 
                             (match_dup 5))
5962 
                         (match_dup 3)
5963 
                         (match_dup 4)))]
5964 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5965 
   && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5966 
  {
5967 
     operands[3] = gen_reg_rtx (SFmode);
5968 
     operands[4] = gen_reg_rtx (SFmode);
5969 
     operands[5] = CONST0_RTX (SFmode);
5970 
  })
5971 
 
5972 
(define_expand "copysigndf3"
5973 
  [(set (match_dup 3)
5974 
        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5975 
   (set (match_dup 4)
5976 
        (neg:DF (abs:DF (match_dup 1))))
5977 
   (set (match_operand:DF 0 "gpc_reg_operand" "")
5978 
        (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5979 
                             (match_dup 5))
5980 
                         (match_dup 3)
5981 
                         (match_dup 4)))]
5982 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5983 
   && ((TARGET_PPC_GFXOPT
5984 
        && !HONOR_NANS (DFmode)
5985 
        && !HONOR_SIGNED_ZEROS (DFmode))
5986 
       || VECTOR_UNIT_VSX_P (DFmode))"
5987 
  {
5988 
     if (VECTOR_UNIT_VSX_P (DFmode))
5989 
       {
5990 
         emit_insn (gen_vsx_copysigndf3 (operands[0], operands[1],
5991 
                                         operands[2], CONST0_RTX (DFmode)));
5992 
         DONE;
5993 
       }
5994 
     operands[3] = gen_reg_rtx (DFmode);
5995 
     operands[4] = gen_reg_rtx (DFmode);
5996 
     operands[5] = CONST0_RTX (DFmode);
5997 
  })
5998 
 
5999 
;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
6000 
;; fsel instruction and some auxiliary computations.  Then we just have a
6001 
;; single DEFINE_INSN for fsel and the define_splits to make them if made by
6002 
;; combine.
6003 
(define_expand "smaxsf3"
6004 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
6005 
        (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6006 
                             (match_operand:SF 2 "gpc_reg_operand" ""))
6007 
                         (match_dup 1)
6008 
                         (match_dup 2)))]
6009 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6010 
   && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6011 
  "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6012 
 
6013 
(define_expand "sminsf3"
6014 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
6015 
        (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6016 
                             (match_operand:SF 2 "gpc_reg_operand" ""))
6017 
                         (match_dup 2)
6018 
                         (match_dup 1)))]
6019 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6020 
   && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6021 
  "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6022 
 
6023 
(define_split
6024 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
6025 
        (match_operator:SF 3 "min_max_operator"
6026 
         [(match_operand:SF 1 "gpc_reg_operand" "")
6027 
          (match_operand:SF 2 "gpc_reg_operand" "")]))]
6028 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6029 
   && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6030 
  [(const_int 0)]
6031 
  "
6032 
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6033 
                      operands[1], operands[2]);
6034 
  DONE;
6035 
}")
6036 
 
6037 
(define_expand "movcc"
6038 
   [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6039 
         (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6040 
                           (match_operand:GPR 2 "gpc_reg_operand" "")
6041 
                           (match_operand:GPR 3 "gpc_reg_operand" "")))]
6042 
  "TARGET_ISEL"
6043 
  "
6044 
{
6045 
  if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6046 
    DONE;
6047 
  else
6048 
    FAIL;
6049 
}")
6050 
 
6051 
;; We use the BASE_REGS for the isel input operands because, if rA is
6052 
;; 0, the value of 0 is placed in rD upon truth.  Similarly for rB
6053 
;; because we may switch the operands and rB may end up being rA.
6054 
;;
6055 
;; We need 2 patterns: an unsigned and a signed pattern.  We could
6056 
;; leave out the mode in operand 4 and use one pattern, but reload can
6057 
;; change the mode underneath our feet and then gets confused trying
6058 
;; to reload the value.
6059 
(define_insn "isel_signed_"
6060 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6061 
        (if_then_else:GPR
6062 
         (match_operator 1 "comparison_operator"
6063 
                         [(match_operand:CC 4 "cc_reg_operand" "y")
6064 
                          (const_int 0)])
6065 
         (match_operand:GPR 2 "gpc_reg_operand" "b")
6066 
         (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6067 
  "TARGET_ISEL"
6068 
  "*
6069 
{ return output_isel (operands); }"
6070 
  [(set_attr "type" "isel")
6071 
   (set_attr "length" "4")])
6072 
 
6073 
(define_insn "isel_unsigned_"
6074 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6075 
        (if_then_else:GPR
6076 
         (match_operator 1 "comparison_operator"
6077 
                         [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6078 
                          (const_int 0)])
6079 
         (match_operand:GPR 2 "gpc_reg_operand" "b")
6080 
         (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6081 
  "TARGET_ISEL"
6082 
  "*
6083 
{ return output_isel (operands); }"
6084 
  [(set_attr "type" "isel")
6085 
   (set_attr "length" "4")])
6086 
 
6087 
(define_expand "movsfcc"
6088 
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
6089 
         (if_then_else:SF (match_operand 1 "comparison_operator" "")
6090 
                          (match_operand:SF 2 "gpc_reg_operand" "")
6091 
                          (match_operand:SF 3 "gpc_reg_operand" "")))]
6092 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6093 
  "
6094 
{
6095 
  if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6096 
    DONE;
6097 
  else
6098 
    FAIL;
6099 
}")
6100 
 
6101 
(define_insn "*fselsfsf4"
6102 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6103 
        (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6104 
                             (match_operand:SF 4 "zero_fp_constant" "F"))
6105 
                         (match_operand:SF 2 "gpc_reg_operand" "f")
6106 
                         (match_operand:SF 3 "gpc_reg_operand" "f")))]
6107 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6108 
  "fsel %0,%1,%2,%3"
6109 
  [(set_attr "type" "fp")])
6110 
 
6111 
(define_insn "*fseldfsf4"
6112 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6113 
        (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6114 
                             (match_operand:DF 4 "zero_fp_constant" "F"))
6115 
                         (match_operand:SF 2 "gpc_reg_operand" "f")
6116 
                         (match_operand:SF 3 "gpc_reg_operand" "f")))]
6117 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6118 
  "fsel %0,%1,%2,%3"
6119 
  [(set_attr "type" "fp")])
6120 
 
6121 
(define_expand "negdf2"
6122 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6123 
        (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6124 
  "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6125 
  "")
6126 
 
6127 
(define_insn "*negdf2_fpr"
6128 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6129 
        (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6130 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6131 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6132 
  "fneg %0,%1"
6133 
  [(set_attr "type" "fp")])
6134 
 
6135 
(define_expand "absdf2"
6136 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6137 
        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6138 
  "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6139 
  "")
6140 
 
6141 
(define_insn "*absdf2_fpr"
6142 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6143 
        (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6144 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6145 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6146 
  "fabs %0,%1"
6147 
  [(set_attr "type" "fp")])
6148 
 
6149 
(define_insn "*nabsdf2_fpr"
6150 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6151 
        (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6152 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6153 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6154 
  "fnabs %0,%1"
6155 
  [(set_attr "type" "fp")])
6156 
 
6157 
(define_expand "adddf3"
6158 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6159 
        (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6160 
                 (match_operand:DF 2 "gpc_reg_operand" "")))]
6161 
  "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6162 
  "")
6163 
 
6164 
(define_insn "*adddf3_fpr"
6165 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6166 
        (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6167 
                 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6168 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6169 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6170 
  "{fa|fadd} %0,%1,%2"
6171 
  [(set_attr "type" "fp")
6172 
   (set_attr "fp_type" "fp_addsub_d")])
6173 
 
6174 
(define_expand "subdf3"
6175 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6176 
        (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6177 
                  (match_operand:DF 2 "gpc_reg_operand" "")))]
6178 
  "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6179 
  "")
6180 
 
6181 
(define_insn "*subdf3_fpr"
6182 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6183 
        (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6184 
                  (match_operand:DF 2 "gpc_reg_operand" "d")))]
6185 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6186 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6187 
  "{fs|fsub} %0,%1,%2"
6188 
  [(set_attr "type" "fp")
6189 
   (set_attr "fp_type" "fp_addsub_d")])
6190 
 
6191 
(define_expand "muldf3"
6192 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6193 
        (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6194 
                 (match_operand:DF 2 "gpc_reg_operand" "")))]
6195 
  "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6196 
  "")
6197 
 
6198 
(define_insn "*muldf3_fpr"
6199 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6200 
        (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6201 
                 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6202 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6203 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6204 
  "{fm|fmul} %0,%1,%2"
6205 
  [(set_attr "type" "dmul")
6206 
   (set_attr "fp_type" "fp_mul_d")])
6207 
 
6208 
(define_expand "divdf3"
6209 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6210 
        (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6211 
                (match_operand:DF 2 "gpc_reg_operand" "")))]
6212 
  "TARGET_HARD_FLOAT
6213 
   && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6214 
   && !TARGET_SIMPLE_FPU"
6215 
  "")
6216 
 
6217 
(define_insn "*divdf3_fpr"
6218 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6219 
        (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6220 
                (match_operand:DF 2 "gpc_reg_operand" "d")))]
6221 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6222 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6223 
  "{fd|fdiv} %0,%1,%2"
6224 
  [(set_attr "type" "ddiv")])
6225 
 
6226 
(define_expand "recipdf3"
6227 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6228 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
6229 
                    (match_operand:DF 2 "gpc_reg_operand" "d")]
6230 
                   UNSPEC_FRES))]
6231 
  "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
6232 
   && flag_finite_math_only && !flag_trapping_math"
6233 
{
6234 
   rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
6235 
   DONE;
6236 
})
6237 
 
6238 
(define_expand "fred"
6239 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6240 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
6241 
  "(TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) && flag_finite_math_only"
6242 
  "")
6243 
 
6244 
(define_insn "*fred_fpr"
6245 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6246 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6247 
  "TARGET_POPCNTB && flag_finite_math_only && !VECTOR_UNIT_VSX_P (DFmode)"
6248 
  "fre %0,%1"
6249 
  [(set_attr "type" "fp")])
6250 
 
6251 
(define_insn "*fmadddf4_fpr"
6252 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6253 
        (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6254 
                          (match_operand:DF 2 "gpc_reg_operand" "d"))
6255 
                 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6256 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6257 
   && VECTOR_UNIT_NONE_P (DFmode)"
6258 
  "{fma|fmadd} %0,%1,%2,%3"
6259 
  [(set_attr "type" "dmul")
6260 
   (set_attr "fp_type" "fp_maddsub_d")])
6261 
 
6262 
(define_insn "*fmsubdf4_fpr"
6263 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6264 
        (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6265 
                           (match_operand:DF 2 "gpc_reg_operand" "d"))
6266 
                  (match_operand:DF 3 "gpc_reg_operand" "d")))]
6267 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6268 
   && VECTOR_UNIT_NONE_P (DFmode)"
6269 
  "{fms|fmsub} %0,%1,%2,%3"
6270 
  [(set_attr "type" "dmul")
6271 
   (set_attr "fp_type" "fp_maddsub_d")])
6272 
 
6273 
(define_insn "*fnmadddf4_fpr_1"
6274 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6275 
        (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6276 
                                  (match_operand:DF 2 "gpc_reg_operand" "d"))
6277 
                         (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6278 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6279 
   && VECTOR_UNIT_NONE_P (DFmode)"
6280 
  "{fnma|fnmadd} %0,%1,%2,%3"
6281 
  [(set_attr "type" "dmul")
6282 
   (set_attr "fp_type" "fp_maddsub_d")])
6283 
 
6284 
(define_insn "*fnmadddf4_fpr_2"
6285 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6286 
        (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6287 
                           (match_operand:DF 2 "gpc_reg_operand" "d"))
6288 
                  (match_operand:DF 3 "gpc_reg_operand" "d")))]
6289 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6290 
   && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6291 
  "{fnma|fnmadd} %0,%1,%2,%3"
6292 
  [(set_attr "type" "dmul")
6293 
   (set_attr "fp_type" "fp_maddsub_d")])
6294 
 
6295 
(define_insn "*fnmsubdf4_fpr_1"
6296 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6297 
        (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6298 
                                   (match_operand:DF 2 "gpc_reg_operand" "d"))
6299 
                          (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6300 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6301 
   && VECTOR_UNIT_NONE_P (DFmode)"
6302 
  "{fnms|fnmsub} %0,%1,%2,%3"
6303 
  [(set_attr "type" "dmul")
6304 
   (set_attr "fp_type" "fp_maddsub_d")])
6305 
 
6306 
(define_insn "*fnmsubdf4_fpr_2"
6307 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6308 
        (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6309 
                  (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6310 
                           (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6311 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6312 
   && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6313 
  "{fnms|fnmsub} %0,%1,%2,%3"
6314 
  [(set_attr "type" "dmul")
6315 
   (set_attr "fp_type" "fp_maddsub_d")])
6316 
 
6317 
(define_expand "sqrtdf2"
6318 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6319 
        (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6320 
  "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6321 
   && TARGET_DOUBLE_FLOAT"
6322 
  "")
6323 
 
6324 
(define_insn "*sqrtdf2_fpr"
6325 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6326 
        (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6327 
  "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6328 
   && TARGET_DOUBLE_FLOAT
6329 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6330 
  "fsqrt %0,%1"
6331 
  [(set_attr "type" "dsqrt")])
6332 
 
6333 
;; The conditional move instructions allow us to perform max and min
6334 
;; operations even when
6335 
 
6336 
(define_expand "smaxdf3"
6337 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6338 
        (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6339 
                             (match_operand:DF 2 "gpc_reg_operand" ""))
6340 
                         (match_dup 1)
6341 
                         (match_dup 2)))]
6342 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6343 
   && !flag_trapping_math"
6344 
  "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6345 
 
6346 
(define_expand "smindf3"
6347 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6348 
        (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6349 
                             (match_operand:DF 2 "gpc_reg_operand" ""))
6350 
                         (match_dup 2)
6351 
                         (match_dup 1)))]
6352 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6353 
   && !flag_trapping_math"
6354 
  "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6355 
 
6356 
(define_split
6357 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6358 
        (match_operator:DF 3 "min_max_operator"
6359 
         [(match_operand:DF 1 "gpc_reg_operand" "")
6360 
          (match_operand:DF 2 "gpc_reg_operand" "")]))]
6361 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6362 
   && !flag_trapping_math"
6363 
  [(const_int 0)]
6364 
  "
6365 
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6366 
                      operands[1], operands[2]);
6367 
  DONE;
6368 
}")
6369 
 
6370 
(define_expand "movdfcc"
6371 
   [(set (match_operand:DF 0 "gpc_reg_operand" "")
6372 
         (if_then_else:DF (match_operand 1 "comparison_operator" "")
6373 
                          (match_operand:DF 2 "gpc_reg_operand" "")
6374 
                          (match_operand:DF 3 "gpc_reg_operand" "")))]
6375 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6376 
  "
6377 
{
6378 
  if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6379 
    DONE;
6380 
  else
6381 
    FAIL;
6382 
}")
6383 
 
6384 
(define_insn "*fseldfdf4"
6385 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6386 
        (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6387 
                             (match_operand:DF 4 "zero_fp_constant" "F"))
6388 
                         (match_operand:DF 2 "gpc_reg_operand" "d")
6389 
                         (match_operand:DF 3 "gpc_reg_operand" "d")))]
6390 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6391 
  "fsel %0,%1,%2,%3"
6392 
  [(set_attr "type" "fp")])
6393 
 
6394 
(define_insn "*fselsfdf4"
6395 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6396 
        (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6397 
                             (match_operand:SF 4 "zero_fp_constant" "F"))
6398 
                         (match_operand:DF 2 "gpc_reg_operand" "d")
6399 
                         (match_operand:DF 3 "gpc_reg_operand" "d")))]
6400 
  "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6401 
  "fsel %0,%1,%2,%3"
6402 
  [(set_attr "type" "fp")])
6403 
 
6404 
;; Conversions to and from floating-point.
6405 
 
6406 
(define_expand "fixuns_truncsfsi2"
6407 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
6408 
        (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6409 
  "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6410 
  "")
6411 
 
6412 
(define_expand "fix_truncsfsi2"
6413 
 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6414 
      (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6415 
 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6416 
 "")
6417 
 
6418 
(define_expand "fixuns_truncdfsi2"
6419 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
6420 
        (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6421 
  "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6422 
  "")
6423 
 
6424 
(define_expand "fixuns_truncdfdi2"
6425 
  [(set (match_operand:DI 0 "register_operand" "")
6426 
        (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
6427 
  "TARGET_HARD_FLOAT && TARGET_VSX"
6428 
  "")
6429 
 
6430 
; For each of these conversions, there is a define_expand, a define_insn
6431 
; with a '#' template, and a define_split (with C code).  The idea is
6432 
; to allow constant folding with the template of the define_insn,
6433 
; then to have the insns split later (between sched1 and final).
6434 
 
6435 
(define_expand "floatsidf2"
6436 
  [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6437 
                   (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6438 
              (use (match_dup 2))
6439 
              (use (match_dup 3))
6440 
              (clobber (match_dup 4))
6441 
              (clobber (match_dup 5))
6442 
              (clobber (match_dup 6))])]
6443 
  "TARGET_HARD_FLOAT
6444 
   && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6445 
  "
6446 
{
6447 
  if (TARGET_E500_DOUBLE)
6448 
    {
6449 
      emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6450 
      DONE;
6451 
    }
6452 
  if (TARGET_POWERPC64)
6453 
    {
6454 
      rtx x = convert_to_mode (DImode, operands[1], 0);
6455 
      emit_insn (gen_floatdidf2 (operands[0], x));
6456 
      DONE;
6457 
    }
6458 
 
6459 
  operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6460 
  operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6461 
  operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6462 
  operands[5] = gen_reg_rtx (DFmode);
6463 
  operands[6] = gen_reg_rtx (SImode);
6464 
}")
6465 
 
6466 
(define_insn_and_split "*floatsidf2_internal"
6467 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6468 
        (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6469 
   (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6470 
   (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6471 
   (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6472 
   (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6473 
   (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6474 
  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6475 
  "#"
6476 
  ""
6477 
  [(pc)]
6478 
  "
6479 
{
6480 
  rtx lowword, highword;
6481 
  gcc_assert (MEM_P (operands[4]));
6482 
  highword = adjust_address (operands[4], SImode, 0);
6483 
  lowword = adjust_address (operands[4], SImode, 4);
6484 
  if (! WORDS_BIG_ENDIAN)
6485 
    {
6486 
      rtx tmp;
6487 
      tmp = highword; highword = lowword; lowword = tmp;
6488 
    }
6489 
 
6490 
  emit_insn (gen_xorsi3 (operands[6], operands[1],
6491 
                         GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6492 
  emit_move_insn (lowword, operands[6]);
6493 
  emit_move_insn (highword, operands[2]);
6494 
  emit_move_insn (operands[5], operands[4]);
6495 
  emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6496 
  DONE;
6497 
}"
6498 
  [(set_attr "length" "24")])
6499 
 
6500 
(define_expand "floatunssisf2"
6501 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
6502 
        (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6503 
  "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6504 
  "")
6505 
 
6506 
(define_expand "floatunssidf2"
6507 
  [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6508 
                   (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6509 
              (use (match_dup 2))
6510 
              (use (match_dup 3))
6511 
              (clobber (match_dup 4))
6512 
              (clobber (match_dup 5))])]
6513 
  "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6514 
  "
6515 
{
6516 
  if (TARGET_E500_DOUBLE)
6517 
    {
6518 
      emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6519 
      DONE;
6520 
    }
6521 
  if (TARGET_POWERPC64)
6522 
    {
6523 
      rtx x = convert_to_mode (DImode, operands[1], 1);
6524 
      emit_insn (gen_floatdidf2 (operands[0], x));
6525 
      DONE;
6526 
    }
6527 
 
6528 
  operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6529 
  operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6530 
  operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6531 
  operands[5] = gen_reg_rtx (DFmode);
6532 
}")
6533 
 
6534 
(define_insn_and_split "*floatunssidf2_internal"
6535 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6536 
        (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6537 
   (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6538 
   (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6539 
   (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6540 
   (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6541 
  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6542 
  "#"
6543 
  ""
6544 
  [(pc)]
6545 
  "
6546 
{
6547 
  rtx lowword, highword;
6548 
  gcc_assert (MEM_P (operands[4]));
6549 
  highword = adjust_address (operands[4], SImode, 0);
6550 
  lowword = adjust_address (operands[4], SImode, 4);
6551 
  if (! WORDS_BIG_ENDIAN)
6552 
    {
6553 
      rtx tmp;
6554 
      tmp = highword; highword = lowword; lowword = tmp;
6555 
    }
6556 
 
6557 
  emit_move_insn (lowword, operands[1]);
6558 
  emit_move_insn (highword, operands[2]);
6559 
  emit_move_insn (operands[5], operands[4]);
6560 
  emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6561 
  DONE;
6562 
}"
6563 
  [(set_attr "length" "20")])
6564 
 
6565 
(define_expand "fix_truncdfsi2"
6566 
  [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6567 
                   (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6568 
              (clobber (match_dup 2))
6569 
              (clobber (match_dup 3))])]
6570 
  "(TARGET_POWER2 || TARGET_POWERPC)
6571 
   && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6572 
  "
6573 
{
6574 
  if (TARGET_E500_DOUBLE)
6575 
    {
6576 
     emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6577 
     DONE;
6578 
    }
6579 
  operands[2] = gen_reg_rtx (DImode);
6580 
  if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6581 
      && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6582 
    {
6583 
      operands[3] = gen_reg_rtx (DImode);
6584 
      emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6585 
                                            operands[2], operands[3]));
6586 
      DONE;
6587 
    }
6588 
  if (TARGET_PPC_GFXOPT)
6589 
    {
6590 
      rtx orig_dest = operands[0];
6591 
      if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6592 
        operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6593 
      emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6594 
                                                     operands[2]));
6595 
      if (operands[0] != orig_dest)
6596 
        emit_move_insn (orig_dest, operands[0]);
6597 
      DONE;
6598 
    }
6599 
  operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6600 
}")
6601 
 
6602 
(define_insn_and_split "*fix_truncdfsi2_internal"
6603 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6604 
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6605 
   (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6606 
   (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6607 
  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6608 
   && TARGET_DOUBLE_FLOAT"
6609 
  "#"
6610 
  ""
6611 
  [(pc)]
6612 
  "
6613 
{
6614 
  rtx lowword;
6615 
  gcc_assert (MEM_P (operands[3]));
6616 
  lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6617 
 
6618 
  emit_insn (gen_fctiwz (operands[2], operands[1]));
6619 
  emit_move_insn (operands[3], operands[2]);
6620 
  emit_move_insn (operands[0], lowword);
6621 
  DONE;
6622 
}"
6623 
  [(set_attr "length" "16")])
6624 
 
6625 
(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6626 
  [(set (match_operand:SI 0 "memory_operand" "=Z")
6627 
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6628 
   (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6629 
  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6630 
   && TARGET_DOUBLE_FLOAT
6631 
   && TARGET_PPC_GFXOPT"
6632 
  "#"
6633 
  "&& 1"
6634 
  [(pc)]
6635 
  "
6636 
{
6637 
  emit_insn (gen_fctiwz (operands[2], operands[1]));
6638 
  emit_insn (gen_stfiwx (operands[0], operands[2]));
6639 
  DONE;
6640 
}"
6641 
  [(set_attr "length" "16")])
6642 
 
6643 
(define_insn_and_split "fix_truncdfsi2_mfpgpr"
6644 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6645 
        (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6646 
   (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6647 
   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6648 
  "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6649 
   && TARGET_DOUBLE_FLOAT"
6650 
  "#"
6651 
  "&& 1"
6652 
  [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6653 
   (set (match_dup 3) (match_dup 2))
6654 
   (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6655 
  ""
6656 
  [(set_attr "length" "12")])
6657 
 
6658 
; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6659 
; rather than (set (subreg:SI (reg)) (fix:SI ...))
6660 
; because the first makes it clear that operand 0 is not live
6661 
; before the instruction.
6662 
(define_insn "fctiwz"
6663 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6664 
        (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6665 
                   UNSPEC_FCTIWZ))]
6666 
  "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6667 
   && TARGET_DOUBLE_FLOAT"
6668 
  "{fcirz|fctiwz} %0,%1"
6669 
  [(set_attr "type" "fp")])
6670 
 
6671 
(define_expand "btruncdf2"
6672 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6673 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6674 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6675 
  "")
6676 
 
6677 
(define_insn "*btruncdf2_fpr"
6678 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6679 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6680 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6681 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6682 
  "friz %0,%1"
6683 
  [(set_attr "type" "fp")])
6684 
 
6685 
(define_insn "btruncsf2"
6686 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6687 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6688 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6689 
  "friz %0,%1"
6690 
  [(set_attr "type" "fp")])
6691 
 
6692 
(define_expand "ceildf2"
6693 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6694 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIP))]
6695 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6696 
  "")
6697 
 
6698 
(define_insn "*ceildf2_fpr"
6699 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6700 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6701 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6702 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6703 
  "frip %0,%1"
6704 
  [(set_attr "type" "fp")])
6705 
 
6706 
(define_insn "ceilsf2"
6707 
 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6708 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6709 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6710 
  "frip %0,%1"
6711 
  [(set_attr "type" "fp")])
6712 
 
6713 
(define_expand "floordf2"
6714 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6715 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIM))]
6716 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6717 
  "")
6718 
 
6719 
(define_insn "*floordf2_fpr"
6720 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6721 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6722 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6723 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6724 
  "frim %0,%1"
6725 
  [(set_attr "type" "fp")])
6726 
 
6727 
(define_insn "floorsf2"
6728 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6729 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6730 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6731 
  "frim %0,%1"
6732 
  [(set_attr "type" "fp")])
6733 
 
6734 
;; No VSX equivalent to frin
6735 
(define_insn "rounddf2"
6736 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6737 
        (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6738 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6739 
  "frin %0,%1"
6740 
  [(set_attr "type" "fp")])
6741 
 
6742 
(define_insn "roundsf2"
6743 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6744 
        (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6745 
  "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6746 
  "frin %0,%1"
6747 
  [(set_attr "type" "fp")])
6748 
 
6749 
(define_expand "ftruncdf2"
6750 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6751 
        (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6752 
  "VECTOR_UNIT_VSX_P (DFmode)"
6753 
  "")
6754 
 
6755 
; An UNSPEC is used so we don't have to support SImode in FP registers.
6756 
(define_insn "stfiwx"
6757 
  [(set (match_operand:SI 0 "memory_operand" "=Z")
6758 
        (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6759 
                   UNSPEC_STFIWX))]
6760 
  "TARGET_PPC_GFXOPT"
6761 
  "stfiwx %1,%y0"
6762 
  [(set_attr "type" "fpstore")])
6763 
 
6764 
(define_expand "floatsisf2"
6765 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
6766 
        (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6767 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
6768 
  "")
6769 
 
6770 
(define_expand "floatdidf2"
6771 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6772 
        (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6773 
  "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6774 
   && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6775 
  "")
6776 
 
6777 
(define_insn "*floatdidf2_fpr"
6778 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6779 
        (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6780 
  "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6781 
   && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6782 
   && !VECTOR_UNIT_VSX_P (DFmode)"
6783 
  "fcfid %0,%1"
6784 
  [(set_attr "type" "fp")])
6785 
 
6786 
(define_expand "floatunsdidf2"
6787 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
6788 
        (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6789 
  "TARGET_VSX"
6790 
  "")
6791 
 
6792 
(define_expand "fix_truncdfdi2"
6793 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
6794 
        (fix:DI (match_operand:DF 1 "gpc_reg_operand" "")))]
6795 
  "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6796 
    && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6797 
  "")
6798 
 
6799 
(define_insn "*fix_truncdfdi2_fpr"
6800 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6801 
        (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6802 
  "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6803 
    && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6804 
    && !VECTOR_UNIT_VSX_P (DFmode)"
6805 
  "fctidz %0,%1"
6806 
  [(set_attr "type" "fp")])
6807 
 
6808 
(define_expand "floatdisf2"
6809 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
6810 
        (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6811 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6812 
  "
6813 
{
6814 
  rtx val = operands[1];
6815 
  if (!flag_unsafe_math_optimizations)
6816 
    {
6817 
      rtx label = gen_label_rtx ();
6818 
      val = gen_reg_rtx (DImode);
6819 
      emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6820 
      emit_label (label);
6821 
    }
6822 
  emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6823 
  DONE;
6824 
}")
6825 
 
6826 
;; This is not IEEE compliant if rounding mode is "round to nearest".
6827 
;; If the DI->DF conversion is inexact, then it's possible to suffer
6828 
;; from double rounding.
6829 
(define_insn_and_split "floatdisf2_internal1"
6830 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6831 
        (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6832 
   (clobber (match_scratch:DF 2 "=d"))]
6833 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6834 
  "#"
6835 
  "&& reload_completed"
6836 
  [(set (match_dup 2)
6837 
        (float:DF (match_dup 1)))
6838 
   (set (match_dup 0)
6839 
        (float_truncate:SF (match_dup 2)))]
6840 
  "")
6841 
 
6842 
;; Twiddles bits to avoid double rounding.
6843 
;; Bits that might be truncated when converting to DFmode are replaced
6844 
;; by a bit that won't be lost at that stage, but is below the SFmode
6845 
;; rounding position.
6846 
(define_expand "floatdisf2_internal2"
6847 
  [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6848 
                                   (const_int 53)))
6849 
   (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6850 
                                                      (const_int 2047)))
6851 
              (clobber (scratch:CC))])
6852 
   (set (match_dup 3) (plus:DI (match_dup 3)
6853 
                               (const_int 1)))
6854 
   (set (match_dup 0) (plus:DI (match_dup 0)
6855 
                               (const_int 2047)))
6856 
   (set (match_dup 4) (compare:CCUNS (match_dup 3)
6857 
                                     (const_int 2)))
6858 
   (set (match_dup 0) (ior:DI (match_dup 0)
6859 
                              (match_dup 1)))
6860 
   (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6861 
                                         (const_int -2048)))
6862 
              (clobber (scratch:CC))])
6863 
   (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6864 
                           (label_ref (match_operand:DI 2 "" ""))
6865 
                           (pc)))
6866 
   (set (match_dup 0) (match_dup 1))]
6867 
  "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6868 
  "
6869 
{
6870 
  operands[3] = gen_reg_rtx (DImode);
6871 
  operands[4] = gen_reg_rtx (CCUNSmode);
6872 
}")
6873 
 
6874 
;; Define the DImode operations that can be done in a small number
6875 
;; of instructions.  The & constraints are to prevent the register
6876 
;; allocator from allocating registers that overlap with the inputs
6877 
;; (for example, having an input in 7,8 and an output in 6,7).  We
6878 
;; also allow for the output being the same as one of the inputs.
6879 
 
6880 
(define_insn "*adddi3_noppc64"
6881 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6882 
        (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6883 
                 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6884 
  "! TARGET_POWERPC64"
6885 
  "*
6886 
{
6887 
  if (WORDS_BIG_ENDIAN)
6888 
    return (GET_CODE (operands[2])) != CONST_INT
6889 
            ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6890 
            : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6891 
  else
6892 
    return (GET_CODE (operands[2])) != CONST_INT
6893 
            ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6894 
            : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6895 
}"
6896 
  [(set_attr "type" "two")
6897 
   (set_attr "length" "8")])
6898 
 
6899 
(define_insn "*subdi3_noppc64"
6900 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6901 
        (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6902 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6903 
  "! TARGET_POWERPC64"
6904 
  "*
6905 
{
6906 
  if (WORDS_BIG_ENDIAN)
6907 
    return (GET_CODE (operands[1]) != CONST_INT)
6908 
            ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6909 
            : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6910 
  else
6911 
    return (GET_CODE (operands[1]) != CONST_INT)
6912 
            ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6913 
            : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6914 
}"
6915 
  [(set_attr "type" "two")
6916 
   (set_attr "length" "8")])
6917 
 
6918 
(define_insn "*negdi2_noppc64"
6919 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6920 
        (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6921 
  "! TARGET_POWERPC64"
6922 
  "*
6923 
{
6924 
  return (WORDS_BIG_ENDIAN)
6925 
    ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6926 
    : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6927 
}"
6928 
  [(set_attr "type" "two")
6929 
   (set_attr "length" "8")])
6930 
 
6931 
(define_expand "mulsidi3"
6932 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
6933 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6934 
                 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6935 
  "! TARGET_POWERPC64"
6936 
  "
6937 
{
6938 
  if (! TARGET_POWER && ! TARGET_POWERPC)
6939 
    {
6940 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6941 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6942 
      emit_insn (gen_mull_call ());
6943 
      if (WORDS_BIG_ENDIAN)
6944 
        emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6945 
      else
6946 
        {
6947 
          emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6948 
                          gen_rtx_REG (SImode, 3));
6949 
          emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6950 
                          gen_rtx_REG (SImode, 4));
6951 
        }
6952 
      DONE;
6953 
    }
6954 
  else if (TARGET_POWER)
6955 
    {
6956 
      emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6957 
      DONE;
6958 
    }
6959 
}")
6960 
 
6961 
(define_insn "mulsidi3_mq"
6962 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6963 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6964 
                 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6965 
   (clobber (match_scratch:SI 3 "=q"))]
6966 
  "TARGET_POWER"
6967 
  "mul %0,%1,%2\;mfmq %L0"
6968 
  [(set_attr "type" "imul")
6969 
   (set_attr "length" "8")])
6970 
 
6971 
(define_insn "*mulsidi3_no_mq"
6972 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6973 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6974 
                 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6975 
  "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6976 
  "*
6977 
{
6978 
  return (WORDS_BIG_ENDIAN)
6979 
    ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6980 
    : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6981 
}"
6982 
  [(set_attr "type" "imul")
6983 
   (set_attr "length" "8")])
6984 
 
6985 
(define_split
6986 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
6987 
        (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6988 
                 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6989 
  "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6990 
  [(set (match_dup 3)
6991 
        (truncate:SI
6992 
         (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6993 
                               (sign_extend:DI (match_dup 2)))
6994 
                      (const_int 32))))
6995 
   (set (match_dup 4)
6996 
        (mult:SI (match_dup 1)
6997 
                 (match_dup 2)))]
6998 
  "
6999 
{
7000 
  int endian = (WORDS_BIG_ENDIAN == 0);
7001 
  operands[3] = operand_subword (operands[0], endian, 0, DImode);
7002 
  operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7003 
}")
7004 
 
7005 
(define_expand "umulsidi3"
7006 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7007 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7008 
                 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7009 
  "TARGET_POWERPC && ! TARGET_POWERPC64"
7010 
  "
7011 
{
7012 
  if (TARGET_POWER)
7013 
    {
7014 
      emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7015 
      DONE;
7016 
    }
7017 
}")
7018 
 
7019 
(define_insn "umulsidi3_mq"
7020 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7021 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7022 
                 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7023 
   (clobber (match_scratch:SI 3 "=q"))]
7024 
  "TARGET_POWERPC && TARGET_POWER"
7025 
  "*
7026 
{
7027 
  return (WORDS_BIG_ENDIAN)
7028 
    ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7029 
    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7030 
}"
7031 
  [(set_attr "type" "imul")
7032 
   (set_attr "length" "8")])
7033 
 
7034 
(define_insn "*umulsidi3_no_mq"
7035 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7036 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7037 
                 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7038 
  "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7039 
  "*
7040 
{
7041 
  return (WORDS_BIG_ENDIAN)
7042 
    ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7043 
    : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7044 
}"
7045 
  [(set_attr "type" "imul")
7046 
   (set_attr "length" "8")])
7047 
 
7048 
(define_split
7049 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7050 
        (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7051 
                 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7052 
  "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7053 
  [(set (match_dup 3)
7054 
        (truncate:SI
7055 
         (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7056 
                               (zero_extend:DI (match_dup 2)))
7057 
                      (const_int 32))))
7058 
   (set (match_dup 4)
7059 
        (mult:SI (match_dup 1)
7060 
                 (match_dup 2)))]
7061 
  "
7062 
{
7063 
  int endian = (WORDS_BIG_ENDIAN == 0);
7064 
  operands[3] = operand_subword (operands[0], endian, 0, DImode);
7065 
  operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7066 
}")
7067 
 
7068 
(define_expand "smulsi3_highpart"
7069 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
7070 
        (truncate:SI
7071 
         (lshiftrt:DI (mult:DI (sign_extend:DI
7072 
                                (match_operand:SI 1 "gpc_reg_operand" ""))
7073 
                               (sign_extend:DI
7074 
                                (match_operand:SI 2 "gpc_reg_operand" "")))
7075 
                      (const_int 32))))]
7076 
  ""
7077 
  "
7078 
{
7079 
  if (! TARGET_POWER && ! TARGET_POWERPC)
7080 
    {
7081 
      emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7082 
      emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7083 
      emit_insn (gen_mulh_call ());
7084 
      emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7085 
      DONE;
7086 
    }
7087 
  else if (TARGET_POWER)
7088 
    {
7089 
      emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7090 
      DONE;
7091 
    }
7092 
}")
7093 
 
7094 
(define_insn "smulsi3_highpart_mq"
7095 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7096 
        (truncate:SI
7097 
         (lshiftrt:DI (mult:DI (sign_extend:DI
7098 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
7099 
                               (sign_extend:DI
7100 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
7101 
                      (const_int 32))))
7102 
   (clobber (match_scratch:SI 3 "=q"))]
7103 
  "TARGET_POWER"
7104 
  "mul %0,%1,%2"
7105 
  [(set_attr "type" "imul")])
7106 
 
7107 
(define_insn "*smulsi3_highpart_no_mq"
7108 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7109 
        (truncate:SI
7110 
         (lshiftrt:DI (mult:DI (sign_extend:DI
7111 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
7112 
                               (sign_extend:DI
7113 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
7114 
                      (const_int 32))))]
7115 
  "TARGET_POWERPC && ! TARGET_POWER"
7116 
  "mulhw %0,%1,%2"
7117 
  [(set_attr "type" "imul")])
7118 
 
7119 
(define_expand "umulsi3_highpart"
7120 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
7121 
        (truncate:SI
7122 
         (lshiftrt:DI (mult:DI (zero_extend:DI
7123 
                                (match_operand:SI 1 "gpc_reg_operand" ""))
7124 
                               (zero_extend:DI
7125 
                                (match_operand:SI 2 "gpc_reg_operand" "")))
7126 
                      (const_int 32))))]
7127 
  "TARGET_POWERPC"
7128 
  "
7129 
{
7130 
  if (TARGET_POWER)
7131 
    {
7132 
      emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7133 
      DONE;
7134 
    }
7135 
}")
7136 
 
7137 
(define_insn "umulsi3_highpart_mq"
7138 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7139 
        (truncate:SI
7140 
         (lshiftrt:DI (mult:DI (zero_extend:DI
7141 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
7142 
                               (zero_extend:DI
7143 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
7144 
                      (const_int 32))))
7145 
   (clobber (match_scratch:SI 3 "=q"))]
7146 
  "TARGET_POWERPC && TARGET_POWER"
7147 
  "mulhwu %0,%1,%2"
7148 
  [(set_attr "type" "imul")])
7149 
 
7150 
(define_insn "*umulsi3_highpart_no_mq"
7151 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7152 
        (truncate:SI
7153 
         (lshiftrt:DI (mult:DI (zero_extend:DI
7154 
                                (match_operand:SI 1 "gpc_reg_operand" "%r"))
7155 
                               (zero_extend:DI
7156 
                                (match_operand:SI 2 "gpc_reg_operand" "r")))
7157 
                      (const_int 32))))]
7158 
  "TARGET_POWERPC && ! TARGET_POWER"
7159 
  "mulhwu %0,%1,%2"
7160 
  [(set_attr "type" "imul")])
7161 
 
7162 
;; If operands 0 and 2 are in the same register, we have a problem.  But
7163 
;; operands 0 and 1 (the usual case) can be in the same register.  That's
7164 
;; why we have the strange constraints below.
7165 
(define_insn "ashldi3_power"
7166 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7167 
        (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7168 
                   (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7169 
   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7170 
  "TARGET_POWER"
7171 
  "@
7172 
   {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7173 
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7174 
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7175 
   sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7176 
  [(set_attr "length" "8")])
7177 
 
7178 
(define_insn "lshrdi3_power"
7179 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7180 
        (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7181 
                     (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7182 
   (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7183 
  "TARGET_POWER"
7184 
  "@
7185 
   {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7186 
   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7187 
   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7188 
   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7189 
  [(set_attr "length" "8")])
7190 
 
7191 
;; Shift by a variable amount is too complex to be worth open-coding.  We
7192 
;; just handle shifts by constants.
7193 
(define_insn "ashrdi3_power"
7194 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7195 
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7196 
                     (match_operand:SI 2 "const_int_operand" "M,i")))
7197 
   (clobber (match_scratch:SI 3 "=X,q"))]
7198 
  "TARGET_POWER"
7199 
  "@
7200 
   {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7201 
   sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7202 
  [(set_attr "type" "shift")
7203 
   (set_attr "length" "8")])
7204 
 
7205 
(define_insn "ashrdi3_no_power"
7206 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7207 
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7208 
                     (match_operand:SI 2 "const_int_operand" "M,i")))]
7209 
  "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7210 
  "@
7211 
   {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7212 
   {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7213 
  [(set_attr "type" "two,three")
7214 
   (set_attr "length" "8,12")])
7215 
 
7216 
(define_insn "*ashrdisi3_noppc64"
7217 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7218 
        (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7219 
                                (const_int 32)) 4))]
7220 
  "TARGET_32BIT && !TARGET_POWERPC64"
7221 
  "*
7222 
{
7223 
  if (REGNO (operands[0]) == REGNO (operands[1]))
7224 
    return \"\";
7225 
  else
7226 
    return \"mr %0,%1\";
7227 
}"
7228 
   [(set_attr "length" "4")])
7229 
 
7230 
 
7231 
;; PowerPC64 DImode operations.
7232 
 
7233 
(define_expand "absdi2"
7234 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7235 
        (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7236 
  "TARGET_POWERPC64"
7237 
  "
7238 
{
7239 
  if (TARGET_ISEL)
7240 
    emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7241 
  else
7242 
    emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7243 
  DONE;
7244 
}")
7245 
 
7246 
(define_insn_and_split "absdi2_internal"
7247 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7248 
        (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7249 
   (clobber (match_scratch:DI 2 "=&r,&r"))]
7250 
  "TARGET_POWERPC64 && !TARGET_ISEL"
7251 
  "#"
7252 
  "&& reload_completed"
7253 
  [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7254 
   (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7255 
   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7256 
  "")
7257 
 
7258 
(define_insn_and_split "*nabsdi2"
7259 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7260 
        (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7261 
   (clobber (match_scratch:DI 2 "=&r,&r"))]
7262 
  "TARGET_POWERPC64 && !TARGET_ISEL"
7263 
  "#"
7264 
  "&& reload_completed"
7265 
  [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7266 
   (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7267 
   (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7268 
  "")
7269 
 
7270 
(define_insn "muldi3"
7271 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7272 
        (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7273 
                 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7274 
  "TARGET_POWERPC64"
7275 
  "@
7276 
   mulld %0,%1,%2
7277 
   mulli %0,%1,%2"
7278 
   [(set (attr "type")
7279 
      (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7280 
                (const_string "imul3")
7281 
             (match_operand:SI 2 "short_cint_operand" "")
7282 
                (const_string "imul2")]
7283 
        (const_string "lmul")))])
7284 
 
7285 
(define_insn "*muldi3_internal1"
7286 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7287 
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7288 
                             (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7289 
                    (const_int 0)))
7290 
   (clobber (match_scratch:DI 3 "=r,r"))]
7291 
  "TARGET_POWERPC64"
7292 
  "@
7293 
   mulld. %3,%1,%2
7294 
   #"
7295 
  [(set_attr "type" "lmul_compare")
7296 
   (set_attr "length" "4,8")])
7297 
 
7298 
(define_split
7299 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7300 
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7301 
                             (match_operand:DI 2 "gpc_reg_operand" ""))
7302 
                    (const_int 0)))
7303 
   (clobber (match_scratch:DI 3 ""))]
7304 
  "TARGET_POWERPC64 && reload_completed"
7305 
  [(set (match_dup 3)
7306 
        (mult:DI (match_dup 1) (match_dup 2)))
7307 
   (set (match_dup 0)
7308 
        (compare:CC (match_dup 3)
7309 
                    (const_int 0)))]
7310 
  "")
7311 
 
7312 
(define_insn "*muldi3_internal2"
7313 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7314 
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7315 
                             (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7316 
                    (const_int 0)))
7317 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7318 
        (mult:DI (match_dup 1) (match_dup 2)))]
7319 
  "TARGET_POWERPC64"
7320 
  "@
7321 
   mulld. %0,%1,%2
7322 
   #"
7323 
  [(set_attr "type" "lmul_compare")
7324 
   (set_attr "length" "4,8")])
7325 
 
7326 
(define_split
7327 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7328 
        (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7329 
                             (match_operand:DI 2 "gpc_reg_operand" ""))
7330 
                    (const_int 0)))
7331 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7332 
        (mult:DI (match_dup 1) (match_dup 2)))]
7333 
  "TARGET_POWERPC64 && reload_completed"
7334 
  [(set (match_dup 0)
7335 
        (mult:DI (match_dup 1) (match_dup 2)))
7336 
   (set (match_dup 3)
7337 
        (compare:CC (match_dup 0)
7338 
                    (const_int 0)))]
7339 
  "")
7340 
 
7341 
(define_insn "smuldi3_highpart"
7342 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7343 
        (truncate:DI
7344 
         (lshiftrt:TI (mult:TI (sign_extend:TI
7345 
                                (match_operand:DI 1 "gpc_reg_operand" "%r"))
7346 
                               (sign_extend:TI
7347 
                                (match_operand:DI 2 "gpc_reg_operand" "r")))
7348 
                      (const_int 64))))]
7349 
  "TARGET_POWERPC64"
7350 
  "mulhd %0,%1,%2"
7351 
  [(set_attr "type" "lmul")])
7352 
 
7353 
(define_insn "umuldi3_highpart"
7354 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7355 
        (truncate:DI
7356 
         (lshiftrt:TI (mult:TI (zero_extend:TI
7357 
                                (match_operand:DI 1 "gpc_reg_operand" "%r"))
7358 
                               (zero_extend:TI
7359 
                                (match_operand:DI 2 "gpc_reg_operand" "r")))
7360 
                      (const_int 64))))]
7361 
  "TARGET_POWERPC64"
7362 
  "mulhdu %0,%1,%2"
7363 
  [(set_attr "type" "lmul")])
7364 
 
7365 
(define_insn "rotldi3"
7366 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7367 
        (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7368 
                   (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7369 
  "TARGET_POWERPC64"
7370 
  "@
7371 
   rldcl %0,%1,%2,0
7372 
   rldicl %0,%1,%H2,0"
7373 
  [(set_attr "type" "var_shift_rotate,integer")])
7374 
 
7375 
(define_insn "*rotldi3_internal2"
7376 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7377 
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7378 
                               (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7379 
                    (const_int 0)))
7380 
   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7381 
  "TARGET_64BIT"
7382 
  "@
7383 
   rldcl. %3,%1,%2,0
7384 
   rldicl. %3,%1,%H2,0
7385 
   #
7386 
   #"
7387 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7388 
   (set_attr "length" "4,4,8,8")])
7389 
 
7390 
(define_split
7391 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7392 
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7393 
                               (match_operand:DI 2 "reg_or_cint_operand" ""))
7394 
                    (const_int 0)))
7395 
   (clobber (match_scratch:DI 3 ""))]
7396 
  "TARGET_POWERPC64 && reload_completed"
7397 
  [(set (match_dup 3)
7398 
        (rotate:DI (match_dup 1) (match_dup 2)))
7399 
   (set (match_dup 0)
7400 
        (compare:CC (match_dup 3)
7401 
                    (const_int 0)))]
7402 
  "")
7403 
 
7404 
(define_insn "*rotldi3_internal3"
7405 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7406 
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7407 
                               (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7408 
                    (const_int 0)))
7409 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7410 
        (rotate:DI (match_dup 1) (match_dup 2)))]
7411 
  "TARGET_64BIT"
7412 
  "@
7413 
   rldcl. %0,%1,%2,0
7414 
   rldicl. %0,%1,%H2,0
7415 
   #
7416 
   #"
7417 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7418 
   (set_attr "length" "4,4,8,8")])
7419 
 
7420 
(define_split
7421 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7422 
        (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7423 
                               (match_operand:DI 2 "reg_or_cint_operand" ""))
7424 
                    (const_int 0)))
7425 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7426 
        (rotate:DI (match_dup 1) (match_dup 2)))]
7427 
  "TARGET_POWERPC64 && reload_completed"
7428 
  [(set (match_dup 0)
7429 
        (rotate:DI (match_dup 1) (match_dup 2)))
7430 
   (set (match_dup 3)
7431 
        (compare:CC (match_dup 0)
7432 
                    (const_int 0)))]
7433 
  "")
7434 
 
7435 
(define_insn "*rotldi3_internal4"
7436 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7437 
        (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7438 
                           (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7439 
                (match_operand:DI 3 "mask64_operand" "n,n")))]
7440 
  "TARGET_POWERPC64"
7441 
  "@
7442 
   rldc%B3 %0,%1,%2,%S3
7443 
   rldic%B3 %0,%1,%H2,%S3"
7444 
  [(set_attr "type" "var_shift_rotate,integer")])
7445 
 
7446 
(define_insn "*rotldi3_internal5"
7447 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7448 
        (compare:CC (and:DI
7449 
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7450 
                                (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7451 
                     (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7452 
                    (const_int 0)))
7453 
   (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7454 
  "TARGET_64BIT"
7455 
  "@
7456 
   rldc%B3. %4,%1,%2,%S3
7457 
   rldic%B3. %4,%1,%H2,%S3
7458 
   #
7459 
   #"
7460 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7461 
   (set_attr "length" "4,4,8,8")])
7462 
 
7463 
(define_split
7464 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7465 
        (compare:CC (and:DI
7466 
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7467 
                                (match_operand:DI 2 "reg_or_cint_operand" ""))
7468 
                     (match_operand:DI 3 "mask64_operand" ""))
7469 
                    (const_int 0)))
7470 
   (clobber (match_scratch:DI 4 ""))]
7471 
  "TARGET_POWERPC64 && reload_completed"
7472 
  [(set (match_dup 4)
7473 
        (and:DI (rotate:DI (match_dup 1)
7474 
                                (match_dup 2))
7475 
                     (match_dup 3)))
7476 
   (set (match_dup 0)
7477 
        (compare:CC (match_dup 4)
7478 
                    (const_int 0)))]
7479 
  "")
7480 
 
7481 
(define_insn "*rotldi3_internal6"
7482 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7483 
        (compare:CC (and:DI
7484 
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7485 
                                (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7486 
                     (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7487 
                    (const_int 0)))
7488 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7489 
        (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7490 
  "TARGET_64BIT"
7491 
  "@
7492 
   rldc%B3. %0,%1,%2,%S3
7493 
   rldic%B3. %0,%1,%H2,%S3
7494 
   #
7495 
   #"
7496 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7497 
   (set_attr "length" "4,4,8,8")])
7498 
 
7499 
(define_split
7500 
  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7501 
        (compare:CC (and:DI
7502 
                     (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7503 
                                (match_operand:DI 2 "reg_or_cint_operand" ""))
7504 
                     (match_operand:DI 3 "mask64_operand" ""))
7505 
                    (const_int 0)))
7506 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7507 
        (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7508 
  "TARGET_POWERPC64 && reload_completed"
7509 
  [(set (match_dup 0)
7510 
        (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7511 
   (set (match_dup 4)
7512 
        (compare:CC (match_dup 0)
7513 
                    (const_int 0)))]
7514 
  "")
7515 
 
7516 
(define_insn "*rotldi3_internal7"
7517 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7518 
        (zero_extend:DI
7519 
         (subreg:QI
7520 
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7521 
                     (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7522 
  "TARGET_POWERPC64"
7523 
  "@
7524 
   rldcl %0,%1,%2,56
7525 
   rldicl %0,%1,%H2,56"
7526 
  [(set_attr "type" "var_shift_rotate,integer")])
7527 
 
7528 
(define_insn "*rotldi3_internal8"
7529 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7530 
        (compare:CC (zero_extend:DI
7531 
                     (subreg:QI
7532 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7533 
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7534 
                    (const_int 0)))
7535 
   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7536 
  "TARGET_64BIT"
7537 
  "@
7538 
   rldcl. %3,%1,%2,56
7539 
   rldicl. %3,%1,%H2,56
7540 
   #
7541 
   #"
7542 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7543 
   (set_attr "length" "4,4,8,8")])
7544 
 
7545 
(define_split
7546 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7547 
        (compare:CC (zero_extend:DI
7548 
                     (subreg:QI
7549 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7550 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7551 
                    (const_int 0)))
7552 
   (clobber (match_scratch:DI 3 ""))]
7553 
  "TARGET_POWERPC64 && reload_completed"
7554 
  [(set (match_dup 3)
7555 
        (zero_extend:DI (subreg:QI
7556 
                      (rotate:DI (match_dup 1)
7557 
                                 (match_dup 2)) 0)))
7558 
   (set (match_dup 0)
7559 
        (compare:CC (match_dup 3)
7560 
                    (const_int 0)))]
7561 
  "")
7562 
 
7563 
(define_insn "*rotldi3_internal9"
7564 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7565 
        (compare:CC (zero_extend:DI
7566 
                     (subreg:QI
7567 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7568 
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7569 
                    (const_int 0)))
7570 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7571 
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7572 
  "TARGET_64BIT"
7573 
  "@
7574 
   rldcl. %0,%1,%2,56
7575 
   rldicl. %0,%1,%H2,56
7576 
   #
7577 
   #"
7578 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7579 
   (set_attr "length" "4,4,8,8")])
7580 
 
7581 
(define_split
7582 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7583 
        (compare:CC (zero_extend:DI
7584 
                     (subreg:QI
7585 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7586 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7587 
                    (const_int 0)))
7588 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7589 
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7590 
  "TARGET_POWERPC64 && reload_completed"
7591 
  [(set (match_dup 0)
7592 
        (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7593 
   (set (match_dup 3)
7594 
        (compare:CC (match_dup 0)
7595 
                    (const_int 0)))]
7596 
  "")
7597 
 
7598 
(define_insn "*rotldi3_internal10"
7599 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7600 
        (zero_extend:DI
7601 
         (subreg:HI
7602 
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7603 
                     (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7604 
  "TARGET_POWERPC64"
7605 
  "@
7606 
   rldcl %0,%1,%2,48
7607 
   rldicl %0,%1,%H2,48"
7608 
  [(set_attr "type" "var_shift_rotate,integer")])
7609 
 
7610 
(define_insn "*rotldi3_internal11"
7611 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7612 
        (compare:CC (zero_extend:DI
7613 
                     (subreg:HI
7614 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7615 
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7616 
                    (const_int 0)))
7617 
   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7618 
  "TARGET_64BIT"
7619 
  "@
7620 
   rldcl. %3,%1,%2,48
7621 
   rldicl. %3,%1,%H2,48
7622 
   #
7623 
   #"
7624 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7625 
   (set_attr "length" "4,4,8,8")])
7626 
 
7627 
(define_split
7628 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7629 
        (compare:CC (zero_extend:DI
7630 
                     (subreg:HI
7631 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7632 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7633 
                    (const_int 0)))
7634 
   (clobber (match_scratch:DI 3 ""))]
7635 
  "TARGET_POWERPC64 && reload_completed"
7636 
  [(set (match_dup 3)
7637 
        (zero_extend:DI (subreg:HI
7638 
                      (rotate:DI (match_dup 1)
7639 
                                 (match_dup 2)) 0)))
7640 
   (set (match_dup 0)
7641 
        (compare:CC (match_dup 3)
7642 
                    (const_int 0)))]
7643 
  "")
7644 
 
7645 
(define_insn "*rotldi3_internal12"
7646 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7647 
        (compare:CC (zero_extend:DI
7648 
                     (subreg:HI
7649 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7650 
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7651 
                    (const_int 0)))
7652 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7653 
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7654 
  "TARGET_64BIT"
7655 
  "@
7656 
   rldcl. %0,%1,%2,48
7657 
   rldicl. %0,%1,%H2,48
7658 
   #
7659 
   #"
7660 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7661 
   (set_attr "length" "4,4,8,8")])
7662 
 
7663 
(define_split
7664 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7665 
        (compare:CC (zero_extend:DI
7666 
                     (subreg:HI
7667 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7668 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7669 
                    (const_int 0)))
7670 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7671 
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7672 
  "TARGET_POWERPC64 && reload_completed"
7673 
  [(set (match_dup 0)
7674 
        (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7675 
   (set (match_dup 3)
7676 
        (compare:CC (match_dup 0)
7677 
                    (const_int 0)))]
7678 
  "")
7679 
 
7680 
(define_insn "*rotldi3_internal13"
7681 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7682 
        (zero_extend:DI
7683 
         (subreg:SI
7684 
          (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7685 
                     (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7686 
  "TARGET_POWERPC64"
7687 
  "@
7688 
   rldcl %0,%1,%2,32
7689 
   rldicl %0,%1,%H2,32"
7690 
  [(set_attr "type" "var_shift_rotate,integer")])
7691 
 
7692 
(define_insn "*rotldi3_internal14"
7693 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7694 
        (compare:CC (zero_extend:DI
7695 
                     (subreg:SI
7696 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7697 
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7698 
                    (const_int 0)))
7699 
   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7700 
  "TARGET_64BIT"
7701 
  "@
7702 
   rldcl. %3,%1,%2,32
7703 
   rldicl. %3,%1,%H2,32
7704 
   #
7705 
   #"
7706 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7707 
   (set_attr "length" "4,4,8,8")])
7708 
 
7709 
(define_split
7710 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7711 
        (compare:CC (zero_extend:DI
7712 
                     (subreg:SI
7713 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7714 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7715 
                    (const_int 0)))
7716 
   (clobber (match_scratch:DI 3 ""))]
7717 
  "TARGET_POWERPC64 && reload_completed"
7718 
  [(set (match_dup 3)
7719 
        (zero_extend:DI (subreg:SI
7720 
                      (rotate:DI (match_dup 1)
7721 
                                 (match_dup 2)) 0)))
7722 
   (set (match_dup 0)
7723 
        (compare:CC (match_dup 3)
7724 
                    (const_int 0)))]
7725 
  "")
7726 
 
7727 
(define_insn "*rotldi3_internal15"
7728 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7729 
        (compare:CC (zero_extend:DI
7730 
                     (subreg:SI
7731 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7732 
                                 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7733 
                    (const_int 0)))
7734 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7735 
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7736 
  "TARGET_64BIT"
7737 
  "@
7738 
   rldcl. %0,%1,%2,32
7739 
   rldicl. %0,%1,%H2,32
7740 
   #
7741 
   #"
7742 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7743 
   (set_attr "length" "4,4,8,8")])
7744 
 
7745 
(define_split
7746 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7747 
        (compare:CC (zero_extend:DI
7748 
                     (subreg:SI
7749 
                      (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7750 
                                 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7751 
                    (const_int 0)))
7752 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7753 
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7754 
  "TARGET_POWERPC64 && reload_completed"
7755 
  [(set (match_dup 0)
7756 
        (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7757 
   (set (match_dup 3)
7758 
        (compare:CC (match_dup 0)
7759 
                    (const_int 0)))]
7760 
  "")
7761 
 
7762 
(define_expand "ashldi3"
7763 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
7764 
        (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7765 
                   (match_operand:SI 2 "reg_or_cint_operand" "")))]
7766 
  "TARGET_POWERPC64 || TARGET_POWER"
7767 
  "
7768 
{
7769 
  if (TARGET_POWERPC64)
7770 
    ;
7771 
  else if (TARGET_POWER)
7772 
    {
7773 
      emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7774 
      DONE;
7775 
    }
7776 
  else
7777 
    FAIL;
7778 
}")
7779 
 
7780 
(define_insn "*ashldi3_internal1"
7781 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7782 
        (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7783 
                   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7784 
  "TARGET_POWERPC64"
7785 
  "@
7786 
   sld %0,%1,%2
7787 
   sldi %0,%1,%H2"
7788 
  [(set_attr "type" "var_shift_rotate,shift")])
7789 
 
7790 
(define_insn "*ashldi3_internal2"
7791 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7792 
        (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7793 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7794 
                    (const_int 0)))
7795 
   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7796 
  "TARGET_64BIT"
7797 
  "@
7798 
   sld. %3,%1,%2
7799 
   sldi. %3,%1,%H2
7800 
   #
7801 
   #"
7802 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7803 
   (set_attr "length" "4,4,8,8")])
7804 
 
7805 
(define_split
7806 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7807 
        (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7808 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
7809 
                    (const_int 0)))
7810 
   (clobber (match_scratch:DI 3 ""))]
7811 
  "TARGET_POWERPC64 && reload_completed"
7812 
  [(set (match_dup 3)
7813 
        (ashift:DI (match_dup 1) (match_dup 2)))
7814 
   (set (match_dup 0)
7815 
        (compare:CC (match_dup 3)
7816 
                    (const_int 0)))]
7817 
  "")
7818 
 
7819 
(define_insn "*ashldi3_internal3"
7820 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7821 
        (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7822 
                               (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7823 
                    (const_int 0)))
7824 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7825 
        (ashift:DI (match_dup 1) (match_dup 2)))]
7826 
  "TARGET_64BIT"
7827 
  "@
7828 
   sld. %0,%1,%2
7829 
   sldi. %0,%1,%H2
7830 
   #
7831 
   #"
7832 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7833 
   (set_attr "length" "4,4,8,8")])
7834 
 
7835 
(define_split
7836 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7837 
        (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7838 
                               (match_operand:SI 2 "reg_or_cint_operand" ""))
7839 
                    (const_int 0)))
7840 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7841 
        (ashift:DI (match_dup 1) (match_dup 2)))]
7842 
  "TARGET_POWERPC64 && reload_completed"
7843 
  [(set (match_dup 0)
7844 
        (ashift:DI (match_dup 1) (match_dup 2)))
7845 
   (set (match_dup 3)
7846 
        (compare:CC (match_dup 0)
7847 
                    (const_int 0)))]
7848 
  "")
7849 
 
7850 
(define_insn "*ashldi3_internal4"
7851 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7852 
        (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7853 
                           (match_operand:SI 2 "const_int_operand" "i"))
7854 
                (match_operand:DI 3 "const_int_operand" "n")))]
7855 
  "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7856 
  "rldic %0,%1,%H2,%W3")
7857 
 
7858 
(define_insn "ashldi3_internal5"
7859 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7860 
        (compare:CC
7861 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7862 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
7863 
                 (match_operand:DI 3 "const_int_operand" "n,n"))
7864 
         (const_int 0)))
7865 
   (clobber (match_scratch:DI 4 "=r,r"))]
7866 
  "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7867 
  "@
7868 
   rldic. %4,%1,%H2,%W3
7869 
   #"
7870 
  [(set_attr "type" "compare")
7871 
   (set_attr "length" "4,8")])
7872 
 
7873 
(define_split
7874 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7875 
        (compare:CC
7876 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7877 
                            (match_operand:SI 2 "const_int_operand" ""))
7878 
                 (match_operand:DI 3 "const_int_operand" ""))
7879 
         (const_int 0)))
7880 
   (clobber (match_scratch:DI 4 ""))]
7881 
  "TARGET_POWERPC64 && reload_completed
7882 
   && includes_rldic_lshift_p (operands[2], operands[3])"
7883 
  [(set (match_dup 4)
7884 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7885 
                (match_dup 3)))
7886 
   (set (match_dup 0)
7887 
        (compare:CC (match_dup 4)
7888 
                    (const_int 0)))]
7889 
  "")
7890 
 
7891 
(define_insn "*ashldi3_internal6"
7892 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7893 
        (compare:CC
7894 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7895 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
7896 
                    (match_operand:DI 3 "const_int_operand" "n,n"))
7897 
         (const_int 0)))
7898 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7899 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7900 
  "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7901 
  "@
7902 
   rldic. %0,%1,%H2,%W3
7903 
   #"
7904 
  [(set_attr "type" "compare")
7905 
   (set_attr "length" "4,8")])
7906 
 
7907 
(define_split
7908 
  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7909 
        (compare:CC
7910 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7911 
                            (match_operand:SI 2 "const_int_operand" ""))
7912 
                 (match_operand:DI 3 "const_int_operand" ""))
7913 
         (const_int 0)))
7914 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7915 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7916 
  "TARGET_POWERPC64 && reload_completed
7917 
   && includes_rldic_lshift_p (operands[2], operands[3])"
7918 
  [(set (match_dup 0)
7919 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7920 
                (match_dup 3)))
7921 
   (set (match_dup 4)
7922 
        (compare:CC (match_dup 0)
7923 
                    (const_int 0)))]
7924 
  "")
7925 
 
7926 
(define_insn "*ashldi3_internal7"
7927 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7928 
        (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7929 
                           (match_operand:SI 2 "const_int_operand" "i"))
7930 
                (match_operand:DI 3 "mask64_operand" "n")))]
7931 
  "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7932 
  "rldicr %0,%1,%H2,%S3")
7933 
 
7934 
(define_insn "ashldi3_internal8"
7935 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7936 
        (compare:CC
7937 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7938 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
7939 
                 (match_operand:DI 3 "mask64_operand" "n,n"))
7940 
         (const_int 0)))
7941 
   (clobber (match_scratch:DI 4 "=r,r"))]
7942 
  "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7943 
  "@
7944 
   rldicr. %4,%1,%H2,%S3
7945 
   #"
7946 
  [(set_attr "type" "compare")
7947 
   (set_attr "length" "4,8")])
7948 
 
7949 
(define_split
7950 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7951 
        (compare:CC
7952 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7953 
                            (match_operand:SI 2 "const_int_operand" ""))
7954 
                 (match_operand:DI 3 "mask64_operand" ""))
7955 
         (const_int 0)))
7956 
   (clobber (match_scratch:DI 4 ""))]
7957 
  "TARGET_POWERPC64 && reload_completed
7958 
   && includes_rldicr_lshift_p (operands[2], operands[3])"
7959 
  [(set (match_dup 4)
7960 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7961 
                (match_dup 3)))
7962 
   (set (match_dup 0)
7963 
        (compare:CC (match_dup 4)
7964 
                    (const_int 0)))]
7965 
  "")
7966 
 
7967 
(define_insn "*ashldi3_internal9"
7968 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7969 
        (compare:CC
7970 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7971 
                            (match_operand:SI 2 "const_int_operand" "i,i"))
7972 
                    (match_operand:DI 3 "mask64_operand" "n,n"))
7973 
         (const_int 0)))
7974 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7975 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7976 
  "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7977 
  "@
7978 
   rldicr. %0,%1,%H2,%S3
7979 
   #"
7980 
  [(set_attr "type" "compare")
7981 
   (set_attr "length" "4,8")])
7982 
 
7983 
(define_split
7984 
  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7985 
        (compare:CC
7986 
         (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7987 
                            (match_operand:SI 2 "const_int_operand" ""))
7988 
                 (match_operand:DI 3 "mask64_operand" ""))
7989 
         (const_int 0)))
7990 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
7991 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7992 
  "TARGET_POWERPC64 && reload_completed
7993 
   && includes_rldicr_lshift_p (operands[2], operands[3])"
7994 
  [(set (match_dup 0)
7995 
        (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7996 
                (match_dup 3)))
7997 
   (set (match_dup 4)
7998 
        (compare:CC (match_dup 0)
7999 
                    (const_int 0)))]
8000 
  "")
8001 
 
8002 
(define_expand "lshrdi3"
8003 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8004 
        (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8005 
                     (match_operand:SI 2 "reg_or_cint_operand" "")))]
8006 
  "TARGET_POWERPC64 || TARGET_POWER"
8007 
  "
8008 
{
8009 
  if (TARGET_POWERPC64)
8010 
    ;
8011 
  else if (TARGET_POWER)
8012 
    {
8013 
      emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8014 
      DONE;
8015 
    }
8016 
  else
8017 
    FAIL;
8018 
}")
8019 
 
8020 
(define_insn "*lshrdi3_internal1"
8021 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8022 
        (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8023 
                     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8024 
  "TARGET_POWERPC64"
8025 
  "@
8026 
   srd %0,%1,%2
8027 
   srdi %0,%1,%H2"
8028 
  [(set_attr "type" "var_shift_rotate,shift")])
8029 
 
8030 
(define_insn "*lshrdi3_internal2"
8031 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8032 
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8033 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8034 
                    (const_int 0)))
8035 
   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8036 
  "TARGET_64BIT "
8037 
  "@
8038 
   srd. %3,%1,%2
8039 
   srdi. %3,%1,%H2
8040 
   #
8041 
   #"
8042 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8043 
   (set_attr "length" "4,4,8,8")])
8044 
 
8045 
(define_split
8046 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8047 
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8048 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
8049 
                    (const_int 0)))
8050 
   (clobber (match_scratch:DI 3 ""))]
8051 
  "TARGET_POWERPC64 && reload_completed"
8052 
  [(set (match_dup 3)
8053 
        (lshiftrt:DI (match_dup 1) (match_dup 2)))
8054 
   (set (match_dup 0)
8055 
        (compare:CC (match_dup 3)
8056 
                    (const_int 0)))]
8057 
  "")
8058 
 
8059 
(define_insn "*lshrdi3_internal3"
8060 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8061 
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8062 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8063 
                    (const_int 0)))
8064 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8065 
        (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8066 
  "TARGET_64BIT"
8067 
  "@
8068 
   srd. %0,%1,%2
8069 
   srdi. %0,%1,%H2
8070 
   #
8071 
   #"
8072 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8073 
   (set_attr "length" "4,4,8,8")])
8074 
 
8075 
(define_split
8076 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8077 
        (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8078 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
8079 
                    (const_int 0)))
8080 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
8081 
        (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8082 
  "TARGET_POWERPC64 && reload_completed"
8083 
  [(set (match_dup 0)
8084 
        (lshiftrt:DI (match_dup 1) (match_dup 2)))
8085 
   (set (match_dup 3)
8086 
        (compare:CC (match_dup 0)
8087 
                    (const_int 0)))]
8088 
  "")
8089 
 
8090 
(define_expand "ashrdi3"
8091 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8092 
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8093 
                     (match_operand:SI 2 "reg_or_cint_operand" "")))]
8094 
  "WORDS_BIG_ENDIAN"
8095 
  "
8096 
{
8097 
  if (TARGET_POWERPC64)
8098 
    ;
8099 
  else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8100 
    {
8101 
      emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8102 
      DONE;
8103 
    }
8104 
  else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8105 
           && WORDS_BIG_ENDIAN)
8106 
    {
8107 
      emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8108 
      DONE;
8109 
    }
8110 
  else
8111 
    FAIL;
8112 
}")
8113 
 
8114 
(define_insn "*ashrdi3_internal1"
8115 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8116 
        (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8117 
                     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8118 
  "TARGET_POWERPC64"
8119 
  "@
8120 
   srad %0,%1,%2
8121 
   sradi %0,%1,%H2"
8122 
  [(set_attr "type" "var_shift_rotate,shift")])
8123 
 
8124 
(define_insn "*ashrdi3_internal2"
8125 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8126 
        (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8127 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8128 
                    (const_int 0)))
8129 
   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8130 
  "TARGET_64BIT"
8131 
  "@
8132 
   srad. %3,%1,%2
8133 
   sradi. %3,%1,%H2
8134 
   #
8135 
   #"
8136 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8137 
   (set_attr "length" "4,4,8,8")])
8138 
 
8139 
(define_split
8140 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8141 
        (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8142 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
8143 
                    (const_int 0)))
8144 
   (clobber (match_scratch:DI 3 ""))]
8145 
  "TARGET_POWERPC64 && reload_completed"
8146 
  [(set (match_dup 3)
8147 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))
8148 
   (set (match_dup 0)
8149 
        (compare:CC (match_dup 3)
8150 
                    (const_int 0)))]
8151 
  "")
8152 
 
8153 
(define_insn "*ashrdi3_internal3"
8154 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8155 
        (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8156 
                                 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8157 
                    (const_int 0)))
8158 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8159 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8160 
  "TARGET_64BIT"
8161 
  "@
8162 
   srad. %0,%1,%2
8163 
   sradi. %0,%1,%H2
8164 
   #
8165 
   #"
8166 
  [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8167 
   (set_attr "length" "4,4,8,8")])
8168 
 
8169 
(define_split
8170 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8171 
        (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8172 
                                 (match_operand:SI 2 "reg_or_cint_operand" ""))
8173 
                    (const_int 0)))
8174 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
8175 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8176 
  "TARGET_POWERPC64 && reload_completed"
8177 
  [(set (match_dup 0)
8178 
        (ashiftrt:DI (match_dup 1) (match_dup 2)))
8179 
   (set (match_dup 3)
8180 
        (compare:CC (match_dup 0)
8181 
                    (const_int 0)))]
8182 
  "")
8183 
 
8184 
(define_expand "anddi3"
8185 
  [(parallel
8186 
    [(set (match_operand:DI 0 "gpc_reg_operand" "")
8187 
          (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8188 
                  (match_operand:DI 2 "and64_2_operand" "")))
8189 
     (clobber (match_scratch:CC 3 ""))])]
8190 
  "TARGET_POWERPC64"
8191 
  "")
8192 
 
8193 
(define_insn "anddi3_mc"
8194 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8195 
        (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8196 
                (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8197 
   (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8198 
  "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8199 
  "@
8200 
   and %0,%1,%2
8201 
   rldic%B2 %0,%1,0,%S2
8202 
   rlwinm %0,%1,0,%m2,%M2
8203 
   andi. %0,%1,%b2
8204 
   andis. %0,%1,%u2
8205 
   #"
8206 
  [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8207 
   (set_attr "length" "4,4,4,4,4,8")])
8208 
 
8209 
(define_insn "anddi3_nomc"
8210 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8211 
        (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8212 
                (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8213 
   (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8214 
  "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8215 
  "@
8216 
   and %0,%1,%2
8217 
   rldic%B2 %0,%1,0,%S2
8218 
   rlwinm %0,%1,0,%m2,%M2
8219 
   #"
8220 
  [(set_attr "length" "4,4,4,8")])
8221 
 
8222 
(define_split
8223 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8224 
        (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8225 
                (match_operand:DI 2 "mask64_2_operand" "")))
8226 
   (clobber (match_scratch:CC 3 ""))]
8227 
  "TARGET_POWERPC64
8228 
    && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8229 
    && !mask_operand (operands[2], DImode)
8230 
    && !mask64_operand (operands[2], DImode)"
8231 
  [(set (match_dup 0)
8232 
        (and:DI (rotate:DI (match_dup 1)
8233 
                           (match_dup 4))
8234 
                (match_dup 5)))
8235 
   (set (match_dup 0)
8236 
        (and:DI (rotate:DI (match_dup 0)
8237 
                           (match_dup 6))
8238 
                (match_dup 7)))]
8239 
{
8240 
  build_mask64_2_operands (operands[2], &operands[4]);
8241 
})
8242 
 
8243 
(define_insn "*anddi3_internal2_mc"
8244 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8245 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8246 
                            (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8247 
                    (const_int 0)))
8248 
   (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8249 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8250 
  "TARGET_64BIT && rs6000_gen_cell_microcode"
8251 
  "@
8252 
   and. %3,%1,%2
8253 
   rldic%B2. %3,%1,0,%S2
8254 
   rlwinm. %3,%1,0,%m2,%M2
8255 
   andi. %3,%1,%b2
8256 
   andis. %3,%1,%u2
8257 
   #
8258 
   #
8259 
   #
8260 
   #
8261 
   #
8262 
   #
8263 
   #"
8264 
  [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8265 
                     fast_compare,compare,compare,compare,compare,compare,\
8266 
                     compare,compare")
8267 
   (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8268 
 
8269 
(define_split
8270 
  [(set (match_operand:CC 0 "cc_reg_operand" "")
8271 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8272 
                            (match_operand:DI 2 "mask64_2_operand" ""))
8273 
                    (const_int 0)))
8274 
   (clobber (match_scratch:DI 3 ""))
8275 
   (clobber (match_scratch:CC 4 ""))]
8276 
  "TARGET_64BIT && reload_completed
8277 
    && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8278 
    && !mask_operand (operands[2], DImode)
8279 
    && !mask64_operand (operands[2], DImode)"
8280 
  [(set (match_dup 3)
8281 
        (and:DI (rotate:DI (match_dup 1)
8282 
                           (match_dup 5))
8283 
                (match_dup 6)))
8284 
   (parallel [(set (match_dup 0)
8285 
                   (compare:CC (and:DI (rotate:DI (match_dup 3)
8286 
                                                  (match_dup 7))
8287 
                                       (match_dup 8))
8288 
                               (const_int 0)))
8289 
              (clobber (match_dup 3))])]
8290 
  "
8291 
{
8292 
  build_mask64_2_operands (operands[2], &operands[5]);
8293 
}")
8294 
 
8295 
(define_insn "*anddi3_internal3_mc"
8296 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8297 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8298 
                            (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8299 
                    (const_int 0)))
8300 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8301 
        (and:DI (match_dup 1) (match_dup 2)))
8302 
   (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8303 
  "TARGET_64BIT && rs6000_gen_cell_microcode"
8304 
  "@
8305 
   and. %0,%1,%2
8306 
   rldic%B2. %0,%1,0,%S2
8307 
   rlwinm. %0,%1,0,%m2,%M2
8308 
   andi. %0,%1,%b2
8309 
   andis. %0,%1,%u2
8310 
   #
8311 
   #
8312 
   #
8313 
   #
8314 
   #
8315 
   #
8316 
   #"
8317 
  [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8318 
                     fast_compare,compare,compare,compare,compare,compare,\
8319 
                     compare,compare")
8320 
   (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8321 
 
8322 
(define_split
8323 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8324 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8325 
                            (match_operand:DI 2 "and64_2_operand" ""))
8326 
                    (const_int 0)))
8327 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
8328 
        (and:DI (match_dup 1) (match_dup 2)))
8329 
   (clobber (match_scratch:CC 4 ""))]
8330 
  "TARGET_64BIT && reload_completed"
8331 
  [(parallel [(set (match_dup 0)
8332 
                    (and:DI (match_dup 1) (match_dup 2)))
8333 
               (clobber (match_dup 4))])
8334 
   (set (match_dup 3)
8335 
        (compare:CC (match_dup 0)
8336 
                    (const_int 0)))]
8337 
  "")
8338 
 
8339 
(define_split
8340 
  [(set (match_operand:CC 3 "cc_reg_operand" "")
8341 
        (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8342 
                            (match_operand:DI 2 "mask64_2_operand" ""))
8343 
                    (const_int 0)))
8344 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
8345 
        (and:DI (match_dup 1) (match_dup 2)))
8346 
   (clobber (match_scratch:CC 4 ""))]
8347 
  "TARGET_64BIT && reload_completed
8348 
    && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8349 
    && !mask_operand (operands[2], DImode)
8350 
    && !mask64_operand (operands[2], DImode)"
8351 
  [(set (match_dup 0)
8352 
        (and:DI (rotate:DI (match_dup 1)
8353 
                           (match_dup 5))
8354 
                (match_dup 6)))
8355 
   (parallel [(set (match_dup 3)
8356 
                   (compare:CC (and:DI (rotate:DI (match_dup 0)
8357 
                                                  (match_dup 7))
8358 
                                       (match_dup 8))
8359 
                               (const_int 0)))
8360 
              (set (match_dup 0)
8361 
                   (and:DI (rotate:DI (match_dup 0)
8362 
                                      (match_dup 7))
8363 
                           (match_dup 8)))])]
8364 
  "
8365 
{
8366 
  build_mask64_2_operands (operands[2], &operands[5]);
8367 
}")
8368 
 
8369 
(define_expand "iordi3"
8370 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8371 
        (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8372 
                (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8373 
  "TARGET_POWERPC64"
8374 
  "
8375 
{
8376 
  if (non_logical_cint_operand (operands[2], DImode))
8377 
    {
8378 
      HOST_WIDE_INT value;
8379 
      rtx tmp = ((!can_create_pseudo_p ()
8380 
                  || rtx_equal_p (operands[0], operands[1]))
8381 
                 ? operands[0] : gen_reg_rtx (DImode));
8382 
 
8383 
      if (GET_CODE (operands[2]) == CONST_INT)
8384 
        {
8385 
          value = INTVAL (operands[2]);
8386 
          emit_insn (gen_iordi3 (tmp, operands[1],
8387 
                                 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8388 
        }
8389 
      else
8390 
        {
8391 
          value = CONST_DOUBLE_LOW (operands[2]);
8392 
          emit_insn (gen_iordi3 (tmp, operands[1],
8393 
                                 immed_double_const (value
8394 
                                                     & (~ (HOST_WIDE_INT) 0xffff),
8395 
                                                     0, DImode)));
8396 
        }
8397 
 
8398 
      emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8399 
      DONE;
8400 
    }
8401 
}")
8402 
 
8403 
(define_expand "xordi3"
8404 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8405 
        (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8406 
                (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8407 
  "TARGET_POWERPC64"
8408 
  "
8409 
{
8410 
  if (non_logical_cint_operand (operands[2], DImode))
8411 
    {
8412 
      HOST_WIDE_INT value;
8413 
      rtx tmp = ((!can_create_pseudo_p ()
8414 
                  || rtx_equal_p (operands[0], operands[1]))
8415 
                 ? operands[0] : gen_reg_rtx (DImode));
8416 
 
8417 
      if (GET_CODE (operands[2]) == CONST_INT)
8418 
        {
8419 
          value = INTVAL (operands[2]);
8420 
          emit_insn (gen_xordi3 (tmp, operands[1],
8421 
                                 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8422 
        }
8423 
      else
8424 
        {
8425 
          value = CONST_DOUBLE_LOW (operands[2]);
8426 
          emit_insn (gen_xordi3 (tmp, operands[1],
8427 
                                 immed_double_const (value
8428 
                                                     & (~ (HOST_WIDE_INT) 0xffff),
8429 
                                                     0, DImode)));
8430 
        }
8431 
 
8432 
      emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8433 
      DONE;
8434 
    }
8435 
}")
8436 
 
8437 
(define_insn "*booldi3_internal1"
8438 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8439 
        (match_operator:DI 3 "boolean_or_operator"
8440 
         [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8441 
          (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8442 
  "TARGET_POWERPC64"
8443 
  "@
8444 
   %q3 %0,%1,%2
8445 
   %q3i %0,%1,%b2
8446 
   %q3is %0,%1,%u2")
8447 
 
8448 
(define_insn "*booldi3_internal2"
8449 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8450 
        (compare:CC (match_operator:DI 4 "boolean_or_operator"
8451 
         [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8452 
          (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8453 
         (const_int 0)))
8454 
   (clobber (match_scratch:DI 3 "=r,r"))]
8455 
  "TARGET_64BIT"
8456 
  "@
8457 
   %q4. %3,%1,%2
8458 
   #"
8459 
  [(set_attr "type" "fast_compare,compare")
8460 
   (set_attr "length" "4,8")])
8461 
 
8462 
(define_split
8463 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8464 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8465 
         [(match_operand:DI 1 "gpc_reg_operand" "")
8466 
          (match_operand:DI 2 "gpc_reg_operand" "")])
8467 
         (const_int 0)))
8468 
   (clobber (match_scratch:DI 3 ""))]
8469 
  "TARGET_POWERPC64 && reload_completed"
8470 
  [(set (match_dup 3) (match_dup 4))
8471 
   (set (match_dup 0)
8472 
        (compare:CC (match_dup 3)
8473 
                    (const_int 0)))]
8474 
  "")
8475 
 
8476 
(define_insn "*booldi3_internal3"
8477 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8478 
        (compare:CC (match_operator:DI 4 "boolean_or_operator"
8479 
         [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8480 
          (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8481 
         (const_int 0)))
8482 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8483 
        (match_dup 4))]
8484 
  "TARGET_64BIT"
8485 
  "@
8486 
   %q4. %0,%1,%2
8487 
   #"
8488 
  [(set_attr "type" "fast_compare,compare")
8489 
   (set_attr "length" "4,8")])
8490 
 
8491 
(define_split
8492 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8493 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8494 
         [(match_operand:DI 1 "gpc_reg_operand" "")
8495 
          (match_operand:DI 2 "gpc_reg_operand" "")])
8496 
         (const_int 0)))
8497 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
8498 
        (match_dup 4))]
8499 
  "TARGET_POWERPC64 && reload_completed"
8500 
  [(set (match_dup 0) (match_dup 4))
8501 
   (set (match_dup 3)
8502 
        (compare:CC (match_dup 0)
8503 
                    (const_int 0)))]
8504 
  "")
8505 
 
8506 
;; Split a logical operation that we can't do in one insn into two insns,
8507 
;; each of which does one 16-bit part.  This is used by combine.
8508 
 
8509 
(define_split
8510 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
8511 
        (match_operator:DI 3 "boolean_or_operator"
8512 
         [(match_operand:DI 1 "gpc_reg_operand" "")
8513 
          (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8514 
  "TARGET_POWERPC64"
8515 
  [(set (match_dup 0) (match_dup 4))
8516 
   (set (match_dup 0) (match_dup 5))]
8517 
"
8518 
{
8519 
  rtx i3,i4;
8520 
 
8521 
  if (GET_CODE (operands[2]) == CONST_DOUBLE)
8522 
    {
8523 
      HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8524 
      i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8525 
                                        0, DImode);
8526 
      i4 = GEN_INT (value & 0xffff);
8527 
    }
8528 
  else
8529 
    {
8530 
      i3 = GEN_INT (INTVAL (operands[2])
8531 
                             & (~ (HOST_WIDE_INT) 0xffff));
8532 
      i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8533 
    }
8534 
  operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8535 
                                operands[1], i3);
8536 
  operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8537 
                                operands[0], i4);
8538 
}")
8539 
 
8540 
(define_insn "*boolcdi3_internal1"
8541 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8542 
        (match_operator:DI 3 "boolean_operator"
8543 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8544 
          (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8545 
  "TARGET_POWERPC64"
8546 
  "%q3 %0,%2,%1")
8547 
 
8548 
(define_insn "*boolcdi3_internal2"
8549 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8550 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8551 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8552 
          (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8553 
         (const_int 0)))
8554 
   (clobber (match_scratch:DI 3 "=r,r"))]
8555 
  "TARGET_64BIT"
8556 
  "@
8557 
   %q4. %3,%2,%1
8558 
   #"
8559 
  [(set_attr "type" "fast_compare,compare")
8560 
   (set_attr "length" "4,8")])
8561 
 
8562 
(define_split
8563 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8564 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8565 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8566 
          (match_operand:DI 2 "gpc_reg_operand" "")])
8567 
         (const_int 0)))
8568 
   (clobber (match_scratch:DI 3 ""))]
8569 
  "TARGET_POWERPC64 && reload_completed"
8570 
  [(set (match_dup 3) (match_dup 4))
8571 
   (set (match_dup 0)
8572 
        (compare:CC (match_dup 3)
8573 
                    (const_int 0)))]
8574 
  "")
8575 
 
8576 
(define_insn "*boolcdi3_internal3"
8577 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8578 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8579 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8580 
          (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8581 
         (const_int 0)))
8582 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8583 
        (match_dup 4))]
8584 
  "TARGET_64BIT"
8585 
  "@
8586 
   %q4. %0,%2,%1
8587 
   #"
8588 
  [(set_attr "type" "fast_compare,compare")
8589 
   (set_attr "length" "4,8")])
8590 
 
8591 
(define_split
8592 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8593 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8594 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8595 
          (match_operand:DI 2 "gpc_reg_operand" "")])
8596 
         (const_int 0)))
8597 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
8598 
        (match_dup 4))]
8599 
  "TARGET_POWERPC64 && reload_completed"
8600 
  [(set (match_dup 0) (match_dup 4))
8601 
   (set (match_dup 3)
8602 
        (compare:CC (match_dup 0)
8603 
                    (const_int 0)))]
8604 
  "")
8605 
 
8606 
(define_insn "*boolccdi3_internal1"
8607 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8608 
        (match_operator:DI 3 "boolean_operator"
8609 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8610 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8611 
  "TARGET_POWERPC64"
8612 
  "%q3 %0,%1,%2")
8613 
 
8614 
(define_insn "*boolccdi3_internal2"
8615 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8616 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8617 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8618 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8619 
         (const_int 0)))
8620 
   (clobber (match_scratch:DI 3 "=r,r"))]
8621 
  "TARGET_64BIT"
8622 
  "@
8623 
   %q4. %3,%1,%2
8624 
   #"
8625 
  [(set_attr "type" "fast_compare,compare")
8626 
   (set_attr "length" "4,8")])
8627 
 
8628 
(define_split
8629 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8630 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8631 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8632 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8633 
         (const_int 0)))
8634 
   (clobber (match_scratch:DI 3 ""))]
8635 
  "TARGET_POWERPC64 && reload_completed"
8636 
  [(set (match_dup 3) (match_dup 4))
8637 
   (set (match_dup 0)
8638 
        (compare:CC (match_dup 3)
8639 
                    (const_int 0)))]
8640 
  "")
8641 
 
8642 
(define_insn "*boolccdi3_internal3"
8643 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8644 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8645 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8646 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8647 
         (const_int 0)))
8648 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8649 
        (match_dup 4))]
8650 
  "TARGET_64BIT"
8651 
  "@
8652 
   %q4. %0,%1,%2
8653 
   #"
8654 
  [(set_attr "type" "fast_compare,compare")
8655 
   (set_attr "length" "4,8")])
8656 
 
8657 
(define_split
8658 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8659 
        (compare:CC (match_operator:DI 4 "boolean_operator"
8660 
         [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8661 
          (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8662 
         (const_int 0)))
8663 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
8664 
        (match_dup 4))]
8665 
  "TARGET_POWERPC64 && reload_completed"
8666 
  [(set (match_dup 0) (match_dup 4))
8667 
   (set (match_dup 3)
8668 
        (compare:CC (match_dup 0)
8669 
                    (const_int 0)))]
8670 
  "")
8671 
 
8672 
(define_expand "smindi3"
8673 
  [(match_operand:DI 0 "gpc_reg_operand" "")
8674 
   (match_operand:DI 1 "gpc_reg_operand" "")
8675 
   (match_operand:DI 2 "gpc_reg_operand" "")]
8676 
  "TARGET_ISEL64"
8677 
  "
8678 
{
8679 
  rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8680 
  DONE;
8681 
}")
8682 
 
8683 
(define_expand "smaxdi3"
8684 
  [(match_operand:DI 0 "gpc_reg_operand" "")
8685 
   (match_operand:DI 1 "gpc_reg_operand" "")
8686 
   (match_operand:DI 2 "gpc_reg_operand" "")]
8687 
  "TARGET_ISEL64"
8688 
  "
8689 
{
8690 
  rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8691 
  DONE;
8692 
}")
8693 
 
8694 
(define_expand "umindi3"
8695 
  [(match_operand:DI 0 "gpc_reg_operand" "")
8696 
   (match_operand:DI 1 "gpc_reg_operand" "")
8697 
   (match_operand:DI 2 "gpc_reg_operand" "")]
8698 
  "TARGET_ISEL64"
8699 
  "
8700 
{
8701 
  rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8702 
  DONE;
8703 
}")
8704 
 
8705 
(define_expand "umaxdi3"
8706 
  [(match_operand:DI 0 "gpc_reg_operand" "")
8707 
   (match_operand:DI 1 "gpc_reg_operand" "")
8708 
   (match_operand:DI 2 "gpc_reg_operand" "")]
8709 
  "TARGET_ISEL64"
8710 
  "
8711 
{
8712 
  rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8713 
  DONE;
8714 
}")
8715 
 
8716 
 
8717 
;; Now define ways of moving data around.
8718 
 
8719 
;; Set up a register with a value from the GOT table
8720 
 
8721 
(define_expand "movsi_got"
8722 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
8723 
        (unspec:SI [(match_operand:SI 1 "got_operand" "")
8724 
                    (match_dup 2)] UNSPEC_MOVSI_GOT))]
8725 
  "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8726 
  "
8727 
{
8728 
  if (GET_CODE (operands[1]) == CONST)
8729 
    {
8730 
      rtx offset = const0_rtx;
8731 
      HOST_WIDE_INT value;
8732 
 
8733 
      operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8734 
      value = INTVAL (offset);
8735 
      if (value != 0)
8736 
        {
8737 
          rtx tmp = (!can_create_pseudo_p ()
8738 
                     ? operands[0]
8739 
                     : gen_reg_rtx (Pmode));
8740 
          emit_insn (gen_movsi_got (tmp, operands[1]));
8741 
          emit_insn (gen_addsi3 (operands[0], tmp, offset));
8742 
          DONE;
8743 
        }
8744 
    }
8745 
 
8746 
  operands[2] = rs6000_got_register (operands[1]);
8747 
}")
8748 
 
8749 
(define_insn "*movsi_got_internal"
8750 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8751 
        (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8752 
                    (match_operand:SI 2 "gpc_reg_operand" "b")]
8753 
                   UNSPEC_MOVSI_GOT))]
8754 
  "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8755 
  "{l|lwz} %0,%a1@got(%2)"
8756 
  [(set_attr "type" "load")])
8757 
 
8758 
;; Used by sched, shorten_branches and final when the GOT pseudo reg
8759 
;; didn't get allocated to a hard register.
8760 
(define_split
8761 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
8762 
        (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8763 
                    (match_operand:SI 2 "memory_operand" "")]
8764 
                   UNSPEC_MOVSI_GOT))]
8765 
  "DEFAULT_ABI == ABI_V4
8766 
    && flag_pic == 1
8767 
    && (reload_in_progress || reload_completed)"
8768 
  [(set (match_dup 0) (match_dup 2))
8769 
   (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8770 
                                 UNSPEC_MOVSI_GOT))]
8771 
  "")
8772 
 
8773 
;; For SI, we special-case integers that can't be loaded in one insn.  We
8774 
;; do the load 16-bits at a time.  We could do this by loading from memory,
8775 
;; and this is even supposed to be faster, but it is simpler not to get
8776 
;; integers in the TOC.
8777 
(define_insn "movsi_low"
8778 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8779 
        (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8780 
                           (match_operand 2 "" ""))))]
8781 
  "TARGET_MACHO && ! TARGET_64BIT"
8782 
  "{l|lwz} %0,lo16(%2)(%1)"
8783 
  [(set_attr "type" "load")
8784 
   (set_attr "length" "4")])
8785 
 
8786 
(define_insn "*movsi_internal1"
8787 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8788 
        (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8789 
  "!TARGET_SINGLE_FPU &&
8790 
   (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8791 
  "@
8792 
   mr %0,%1
8793 
   {cal|la} %0,%a1
8794 
   {l%U1%X1|lwz%U1%X1} %0,%1
8795 
   {st%U0%X0|stw%U0%X0} %1,%0
8796 
   {lil|li} %0,%1
8797 
   {liu|lis} %0,%v1
8798 
   #
8799 
   {cal|la} %0,%a1
8800 
   mf%1 %0
8801 
   mt%0 %1
8802 
   mt%0 %1
8803 
   mt%0 %1
8804 
   {cror 0,0,0|nop}"
8805 
  [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8806 
   (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8807 
 
8808 
(define_insn "*movsi_internal1_single"
8809 
  [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8810 
        (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8811 
  "TARGET_SINGLE_FPU &&
8812 
   (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8813 
  "@
8814 
   mr %0,%1
8815 
   {cal|la} %0,%a1
8816 
   {l%U1%X1|lwz%U1%X1} %0,%1
8817 
   {st%U0%X0|stw%U0%X0} %1,%0
8818 
   {lil|li} %0,%1
8819 
   {liu|lis} %0,%v1
8820 
   #
8821 
   {cal|la} %0,%a1
8822 
   mf%1 %0
8823 
   mt%0 %1
8824 
   mt%0 %1
8825 
   mt%0 %1
8826 
   {cror 0,0,0|nop}
8827 
   stfs%U0%X0 %1, %0
8828 
   lfs%U1%X1 %0, %1"
8829 
  [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8830 
   (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8831 
 
8832 
;; Split a load of a large constant into the appropriate two-insn
8833 
;; sequence.
8834 
 
8835 
(define_split
8836 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
8837 
        (match_operand:SI 1 "const_int_operand" ""))]
8838 
  "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8839 
   && (INTVAL (operands[1]) & 0xffff) != 0"
8840 
  [(set (match_dup 0)
8841 
        (match_dup 2))
8842 
   (set (match_dup 0)
8843 
        (ior:SI (match_dup 0)
8844 
                (match_dup 3)))]
8845 
  "
8846 
{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8847 
 
8848 
  if (tem == operands[0])
8849 
    DONE;
8850 
  else
8851 
    FAIL;
8852 
}")
8853 
 
8854 
(define_insn "*mov_internal2"
8855 
  [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8856 
        (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8857 
                    (const_int 0)))
8858 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8859 
  ""
8860 
  "@
8861 
   {cmpi|cmpi} %2,%0,0
8862 
   mr. %0,%1
8863 
   #"
8864 
  [(set_attr "type" "cmp,compare,cmp")
8865 
   (set_attr "length" "4,4,8")])
8866 
 
8867 
(define_split
8868 
  [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8869 
        (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8870 
                    (const_int 0)))
8871 
   (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8872 
  "reload_completed"
8873 
  [(set (match_dup 0) (match_dup 1))
8874 
   (set (match_dup 2)
8875 
        (compare:CC (match_dup 0)
8876 
                    (const_int 0)))]
8877 
  "")
8878 
 
8879 
(define_insn "*movhi_internal"
8880 
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8881 
        (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8882 
  "gpc_reg_operand (operands[0], HImode)
8883 
   || gpc_reg_operand (operands[1], HImode)"
8884 
  "@
8885 
   mr %0,%1
8886 
   lhz%U1%X1 %0,%1
8887 
   sth%U0%X0 %1,%0
8888 
   {lil|li} %0,%w1
8889 
   mf%1 %0
8890 
   mt%0 %1
8891 
   mt%0 %1
8892 
   {cror 0,0,0|nop}"
8893 
  [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8894 
 
8895 
(define_expand "mov"
8896 
  [(set (match_operand:INT 0 "general_operand" "")
8897 
        (match_operand:INT 1 "any_operand" ""))]
8898 
  ""
8899 
  "{ rs6000_emit_move (operands[0], operands[1], mode); DONE; }")
8900 
 
8901 
(define_insn "*movqi_internal"
8902 
  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8903 
        (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8904 
  "gpc_reg_operand (operands[0], QImode)
8905 
   || gpc_reg_operand (operands[1], QImode)"
8906 
  "@
8907 
   mr %0,%1
8908 
   lbz%U1%X1 %0,%1
8909 
   stb%U0%X0 %1,%0
8910 
   {lil|li} %0,%1
8911 
   mf%1 %0
8912 
   mt%0 %1
8913 
   mt%0 %1
8914 
   {cror 0,0,0|nop}"
8915 
  [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8916 
 
8917 
;; Here is how to move condition codes around.  When we store CC data in
8918 
;; an integer register or memory, we store just the high-order 4 bits.
8919 
;; This lets us not shift in the most common case of CR0.
8920 
(define_expand "movcc"
8921 
  [(set (match_operand:CC 0 "nonimmediate_operand" "")
8922 
        (match_operand:CC 1 "nonimmediate_operand" ""))]
8923 
  ""
8924 
  "")
8925 
 
8926 
(define_insn "*movcc_internal1"
8927 
  [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8928 
        (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8929 
  "register_operand (operands[0], CCmode)
8930 
   || register_operand (operands[1], CCmode)"
8931 
  "@
8932 
   mcrf %0,%1
8933 
   mtcrf 128,%1
8934 
   {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8935 
   crxor %0,%0,%0
8936 
   mfcr %0%Q1
8937 
   mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8938 
   mr %0,%1
8939 
   {lil|li} %0,%1
8940 
   mf%1 %0
8941 
   mt%0 %1
8942 
   mt%0 %1
8943 
   {l%U1%X1|lwz%U1%X1} %0,%1
8944 
   {st%U0%U1|stw%U0%U1} %1,%0"
8945 
  [(set (attr "type")
8946 
     (cond [(eq_attr "alternative" "0,3")
8947 
                (const_string "cr_logical")
8948 
            (eq_attr "alternative" "1,2")
8949 
                (const_string "mtcr")
8950 
            (eq_attr "alternative" "6,7,9")
8951 
                (const_string "integer")
8952 
            (eq_attr "alternative" "8")
8953 
                (const_string "mfjmpr")
8954 
            (eq_attr "alternative" "10")
8955 
                (const_string "mtjmpr")
8956 
            (eq_attr "alternative" "11")
8957 
                (const_string "load")
8958 
            (eq_attr "alternative" "12")
8959 
                (const_string "store")
8960 
            (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8961 
                (const_string "mfcrf")
8962 
           ]
8963 
        (const_string "mfcr")))
8964 
   (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8965 
 
8966 
;; For floating-point, we normally deal with the floating-point registers
8967 
;; unless -msoft-float is used.  The sole exception is that parameter passing
8968 
;; can produce floating-point values in fixed-point registers.  Unless the
8969 
;; value is a simple constant or already in memory, we deal with this by
8970 
;; allocating memory and copying the value explicitly via that memory location.
8971 
(define_expand "movsf"
8972 
  [(set (match_operand:SF 0 "nonimmediate_operand" "")
8973 
        (match_operand:SF 1 "any_operand" ""))]
8974 
  ""
8975 
  "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8976 
 
8977 
(define_split
8978 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
8979 
        (match_operand:SF 1 "const_double_operand" ""))]
8980 
  "reload_completed
8981 
   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8982 
       || (GET_CODE (operands[0]) == SUBREG
8983 
           && GET_CODE (SUBREG_REG (operands[0])) == REG
8984 
           && REGNO (SUBREG_REG (operands[0])) <= 31))"
8985 
  [(set (match_dup 2) (match_dup 3))]
8986 
  "
8987 
{
8988 
  long l;
8989 
  REAL_VALUE_TYPE rv;
8990 
 
8991 
  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8992 
  REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8993 
 
8994 
  if (! TARGET_POWERPC64)
8995 
    operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8996 
  else
8997 
    operands[2] = gen_lowpart (SImode, operands[0]);
8998 
 
8999 
  operands[3] = gen_int_mode (l, SImode);
9000 
}")
9001 
 
9002 
(define_insn "*movsf_hardfloat"
9003 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9004 
        (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9005 
  "(gpc_reg_operand (operands[0], SFmode)
9006 
   || gpc_reg_operand (operands[1], SFmode))
9007 
   && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9008 
  "@
9009 
   mr %0,%1
9010 
   {l%U1%X1|lwz%U1%X1} %0,%1
9011 
   {st%U0%X0|stw%U0%X0} %1,%0
9012 
   fmr %0,%1
9013 
   lfs%U1%X1 %0,%1
9014 
   stfs%U0%X0 %1,%0
9015 
   mt%0 %1
9016 
   mt%0 %1
9017 
   mf%1 %0
9018 
   {cror 0,0,0|nop}
9019 
   #
9020 
   #"
9021 
  [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9022 
   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9023 
 
9024 
(define_insn "*movsf_softfloat"
9025 
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9026 
        (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9027 
  "(gpc_reg_operand (operands[0], SFmode)
9028 
   || gpc_reg_operand (operands[1], SFmode))
9029 
   && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9030 
  "@
9031 
   mr %0,%1
9032 
   mt%0 %1
9033 
   mt%0 %1
9034 
   mf%1 %0
9035 
   {l%U1%X1|lwz%U1%X1} %0,%1
9036 
   {st%U0%X0|stw%U0%X0} %1,%0
9037 
   {lil|li} %0,%1
9038 
   {liu|lis} %0,%v1
9039 
   {cal|la} %0,%a1
9040 
   #
9041 
   #
9042 
   {cror 0,0,0|nop}"
9043 
  [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9044 
   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9045 
 
9046 
 
9047 
(define_expand "movdf"
9048 
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
9049 
        (match_operand:DF 1 "any_operand" ""))]
9050 
  ""
9051 
  "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9052 
 
9053 
(define_split
9054 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
9055 
        (match_operand:DF 1 "const_int_operand" ""))]
9056 
  "! TARGET_POWERPC64 && reload_completed
9057 
   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9058 
       || (GET_CODE (operands[0]) == SUBREG
9059 
           && GET_CODE (SUBREG_REG (operands[0])) == REG
9060 
           && REGNO (SUBREG_REG (operands[0])) <= 31))"
9061 
  [(set (match_dup 2) (match_dup 4))
9062 
   (set (match_dup 3) (match_dup 1))]
9063 
  "
9064 
{
9065 
  int endian = (WORDS_BIG_ENDIAN == 0);
9066 
  HOST_WIDE_INT value = INTVAL (operands[1]);
9067 
 
9068 
  operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9069 
  operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9070 
#if HOST_BITS_PER_WIDE_INT == 32
9071 
  operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9072 
#else
9073 
  operands[4] = GEN_INT (value >> 32);
9074 
  operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9075 
#endif
9076 
}")
9077 
 
9078 
(define_split
9079 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
9080 
        (match_operand:DF 1 "const_double_operand" ""))]
9081 
  "! TARGET_POWERPC64 && reload_completed
9082 
   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9083 
       || (GET_CODE (operands[0]) == SUBREG
9084 
           && GET_CODE (SUBREG_REG (operands[0])) == REG
9085 
           && REGNO (SUBREG_REG (operands[0])) <= 31))"
9086 
  [(set (match_dup 2) (match_dup 4))
9087 
   (set (match_dup 3) (match_dup 5))]
9088 
  "
9089 
{
9090 
  int endian = (WORDS_BIG_ENDIAN == 0);
9091 
  long l[2];
9092 
  REAL_VALUE_TYPE rv;
9093 
 
9094 
  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9095 
  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9096 
 
9097 
  operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9098 
  operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9099 
  operands[4] = gen_int_mode (l[endian], SImode);
9100 
  operands[5] = gen_int_mode (l[1 - endian], SImode);
9101 
}")
9102 
 
9103 
(define_split
9104 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
9105 
        (match_operand:DF 1 "const_double_operand" ""))]
9106 
  "TARGET_POWERPC64 && reload_completed
9107 
   && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9108 
       || (GET_CODE (operands[0]) == SUBREG
9109 
           && GET_CODE (SUBREG_REG (operands[0])) == REG
9110 
           && REGNO (SUBREG_REG (operands[0])) <= 31))"
9111 
  [(set (match_dup 2) (match_dup 3))]
9112 
  "
9113 
{
9114 
  int endian = (WORDS_BIG_ENDIAN == 0);
9115 
  long l[2];
9116 
  REAL_VALUE_TYPE rv;
9117 
#if HOST_BITS_PER_WIDE_INT >= 64
9118 
  HOST_WIDE_INT val;
9119 
#endif
9120 
 
9121 
  REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9122 
  REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9123 
 
9124 
  operands[2] = gen_lowpart (DImode, operands[0]);
9125 
  /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN.  */
9126 
#if HOST_BITS_PER_WIDE_INT >= 64
9127 
  val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9128 
         | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9129 
 
9130 
  operands[3] = gen_int_mode (val, DImode);
9131 
#else
9132 
  operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9133 
#endif
9134 
}")
9135 
 
9136 
;; Don't have reload use general registers to load a constant.  First,
9137 
;; it might not work if the output operand is the equivalent of
9138 
;; a non-offsettable memref, but also it is less efficient than loading
9139 
;; the constant into an FP register, since it will probably be used there.
9140 
;; The "??" is a kludge until we can figure out a more reasonable way
9141 
;; of handling these non-offsettable values.
9142 
(define_insn "*movdf_hardfloat32"
9143 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9144 
        (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9145 
  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9146 
   && (gpc_reg_operand (operands[0], DFmode)
9147 
       || gpc_reg_operand (operands[1], DFmode))"
9148 
  "*
9149 
{
9150 
  switch (which_alternative)
9151 
    {
9152 
    default:
9153 
      gcc_unreachable ();
9154 
    case 0:
9155 
    case 1:
9156 
    case 2:
9157 
      return \"#\";
9158 
    case 3:
9159 
    case 4:
9160 
      return \"xxlor %x0,%x1,%x1\";
9161 
    case 5:
9162 
    case 6:
9163 
      return \"lxsd%U1x %x0,%y1\";
9164 
    case 7:
9165 
    case 8:
9166 
      return \"stxsd%U0x %x1,%y0\";
9167 
    case 9:
9168 
      return \"fmr %0,%1\";
9169 
    case 10:
9170 
      return \"lfd%U1%X1 %0,%1\";
9171 
    case 11:
9172 
      return \"stfd%U0%X0 %1,%0\";
9173 
    case 12:
9174 
      return \"xxlxor %x0,%x0,%x0\";
9175 
    case 13:
9176 
    case 14:
9177 
    case 15:
9178 
      return \"#\";
9179 
    }
9180 
}"
9181 
  [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9182 
   (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9183 
 
9184 
(define_insn "*movdf_softfloat32"
9185 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9186 
        (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9187 
  "! TARGET_POWERPC64
9188 
   && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9189 
       || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9190 
   && (gpc_reg_operand (operands[0], DFmode)
9191 
       || gpc_reg_operand (operands[1], DFmode))"
9192 
  "#"
9193 
  [(set_attr "type" "two,load,store,*,*,*")
9194 
   (set_attr "length" "8,8,8,8,12,16")])
9195 
 
9196 
; ld/std require word-aligned displacements -> 'Y' constraint.
9197 
; List Y->r and r->Y before r->r for reload.
9198 
(define_insn "*movdf_hardfloat64_mfpgpr"
9199 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9200 
        (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9201 
  "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9202 
   && TARGET_DOUBLE_FLOAT
9203 
   && (gpc_reg_operand (operands[0], DFmode)
9204 
       || gpc_reg_operand (operands[1], DFmode))"
9205 
  "@
9206 
   std%U0%X0 %1,%0
9207 
   ld%U1%X1 %0,%1
9208 
   mr %0,%1
9209 
   xxlor %x0,%x1,%x1
9210 
   xxlor %x0,%x1,%x1
9211 
   lxsd%U1x %x0,%y1
9212 
   lxsd%U1x %x0,%y1
9213 
   stxsd%U0x %x1,%y0
9214 
   stxsd%U0x %x1,%y0
9215 
   fmr %0,%1
9216 
   lfd%U1%X1 %0,%1
9217 
   stfd%U0%X0 %1,%0
9218 
   xxlxor %x0,%x0,%x0
9219 
   mt%0 %1
9220 
   mf%1 %0
9221 
   {cror 0,0,0|nop}
9222 
   #
9223 
   #
9224 
   #
9225 
   mftgpr %0,%1
9226 
   mffgpr %0,%1"
9227 
  [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9228 
   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9229 
 
9230 
; ld/std require word-aligned displacements -> 'Y' constraint.
9231 
; List Y->r and r->Y before r->r for reload.
9232 
(define_insn "*movdf_hardfloat64"
9233 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9234 
        (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9235 
  "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9236 
   && TARGET_DOUBLE_FLOAT
9237 
   && (gpc_reg_operand (operands[0], DFmode)
9238 
       || gpc_reg_operand (operands[1], DFmode))"
9239 
  "@
9240 
   std%U0%X0 %1,%0
9241 
   ld%U1%X1 %0,%1
9242 
   mr %0,%1
9243 
   xxlor %x0,%x1,%x1
9244 
   xxlor %x0,%x1,%x1
9245 
   lxsd%U1x %x0,%y1
9246 
   lxsd%U1x %x0,%y1
9247 
   stxsd%U0x %x1,%y0
9248 
   stxsd%U0x %x1,%y0
9249 
   fmr %0,%1
9250 
   lfd%U1%X1 %0,%1
9251 
   stfd%U0%X0 %1,%0
9252 
   xxlxor %x0,%x0,%x0
9253 
   mt%0 %1
9254 
   mf%1 %0
9255 
   {cror 0,0,0|nop}
9256 
   #
9257 
   #
9258 
   #"
9259 
  [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9260 
   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9261 
 
9262 
(define_insn "*movdf_softfloat64"
9263 
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9264 
        (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9265 
  "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9266 
   && (gpc_reg_operand (operands[0], DFmode)
9267 
       || gpc_reg_operand (operands[1], DFmode))"
9268 
  "@
9269 
   ld%U1%X1 %0,%1
9270 
   std%U0%X0 %1,%0
9271 
   mr %0,%1
9272 
   mt%0 %1
9273 
   mf%1 %0
9274 
   #
9275 
   #
9276 
   #
9277 
   {cror 0,0,0|nop}"
9278 
  [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9279 
   (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9280 
 
9281 
(define_expand "movtf"
9282 
  [(set (match_operand:TF 0 "general_operand" "")
9283 
        (match_operand:TF 1 "any_operand" ""))]
9284 
  "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9285 
  "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9286 
 
9287 
; It's important to list the o->f and f->o moves before f->f because
9288 
; otherwise reload, given m->f, will try to pick f->f and reload it,
9289 
; which doesn't make progress.  Likewise r->Y must be before r->r.
9290 
(define_insn_and_split "*movtf_internal"
9291 
  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9292 
        (match_operand:TF 1 "input_operand"         "d,o,d,YGHF,r,r"))]
9293 
  "!TARGET_IEEEQUAD
9294 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9295 
   && (gpc_reg_operand (operands[0], TFmode)
9296 
       || gpc_reg_operand (operands[1], TFmode))"
9297 
  "#"
9298 
  "&& reload_completed"
9299 
  [(pc)]
9300 
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9301 
  [(set_attr "length" "8,8,8,20,20,16")])
9302 
 
9303 
(define_insn_and_split "*movtf_softfloat"
9304 
  [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9305 
        (match_operand:TF 1 "input_operand"         "YGHF,r,r"))]
9306 
  "!TARGET_IEEEQUAD
9307 
   && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9308 
   && (gpc_reg_operand (operands[0], TFmode)
9309 
       || gpc_reg_operand (operands[1], TFmode))"
9310 
  "#"
9311 
  "&& reload_completed"
9312 
  [(pc)]
9313 
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9314 
  [(set_attr "length" "20,20,16")])
9315 
 
9316 
(define_expand "extenddftf2"
9317 
  [(set (match_operand:TF 0 "nonimmediate_operand" "")
9318 
        (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9319 
  "!TARGET_IEEEQUAD
9320 
   && TARGET_HARD_FLOAT
9321 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
9322 
   && TARGET_LONG_DOUBLE_128"
9323 
{
9324 
  if (TARGET_E500_DOUBLE)
9325 
    emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9326 
  else
9327 
    emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9328 
  DONE;
9329 
})
9330 
 
9331 
(define_expand "extenddftf2_fprs"
9332 
  [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9333 
                   (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9334 
              (use (match_dup 2))])]
9335 
  "!TARGET_IEEEQUAD
9336 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9337 
   && TARGET_LONG_DOUBLE_128"
9338 
{
9339 
  operands[2] = CONST0_RTX (DFmode);
9340 
  /* Generate GOT reference early for SVR4 PIC.  */
9341 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
9342 
    operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9343 
})
9344 
 
9345 
(define_insn_and_split "*extenddftf2_internal"
9346 
  [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9347 
       (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9348 
   (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9349 
  "!TARGET_IEEEQUAD
9350 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9351 
   && TARGET_LONG_DOUBLE_128"
9352 
  "#"
9353 
  "&& reload_completed"
9354 
  [(pc)]
9355 
{
9356 
  const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9357 
  const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9358 
  emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9359 
                  operands[1]);
9360 
  emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9361 
                  operands[2]);
9362 
  DONE;
9363 
})
9364 
 
9365 
(define_expand "extendsftf2"
9366 
  [(set (match_operand:TF 0 "nonimmediate_operand" "")
9367 
        (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9368 
  "!TARGET_IEEEQUAD
9369 
   && TARGET_HARD_FLOAT
9370 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
9371 
   && TARGET_LONG_DOUBLE_128"
9372 
{
9373 
  rtx tmp = gen_reg_rtx (DFmode);
9374 
  emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9375 
  emit_insn (gen_extenddftf2 (operands[0], tmp));
9376 
  DONE;
9377 
})
9378 
 
9379 
(define_expand "trunctfdf2"
9380 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
9381 
        (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9382 
  "!TARGET_IEEEQUAD
9383 
   && TARGET_HARD_FLOAT
9384 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
9385 
   && TARGET_LONG_DOUBLE_128"
9386 
  "")
9387 
 
9388 
(define_insn_and_split "trunctfdf2_internal1"
9389 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9390 
        (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9391 
  "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9392 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9393 
  "@
9394 
   #
9395 
   fmr %0,%1"
9396 
  "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9397 
  [(const_int 0)]
9398 
{
9399 
  emit_note (NOTE_INSN_DELETED);
9400 
  DONE;
9401 
}
9402 
  [(set_attr "type" "fp")])
9403 
 
9404 
(define_insn "trunctfdf2_internal2"
9405 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9406 
        (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9407 
  "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9408 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9409 
   && TARGET_LONG_DOUBLE_128"
9410 
  "fadd %0,%1,%L1"
9411 
  [(set_attr "type" "fp")
9412 
   (set_attr "fp_type" "fp_addsub_d")])
9413 
 
9414 
(define_expand "trunctfsf2"
9415 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
9416 
        (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9417 
  "!TARGET_IEEEQUAD
9418 
   && TARGET_HARD_FLOAT
9419 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
9420 
   && TARGET_LONG_DOUBLE_128"
9421 
{
9422 
  if (TARGET_E500_DOUBLE)
9423 
    emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9424 
  else
9425 
    emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9426 
  DONE;
9427 
})
9428 
 
9429 
(define_insn_and_split "trunctfsf2_fprs"
9430 
  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9431 
        (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9432 
   (clobber (match_scratch:DF 2 "=d"))]
9433 
  "!TARGET_IEEEQUAD
9434 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9435 
   && TARGET_LONG_DOUBLE_128"
9436 
  "#"
9437 
  "&& reload_completed"
9438 
  [(set (match_dup 2)
9439 
        (float_truncate:DF (match_dup 1)))
9440 
   (set (match_dup 0)
9441 
        (float_truncate:SF (match_dup 2)))]
9442 
  "")
9443 
 
9444 
(define_expand "floatsitf2"
9445 
  [(set (match_operand:TF 0 "gpc_reg_operand" "")
9446 
        (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9447 
  "!TARGET_IEEEQUAD
9448 
   && TARGET_HARD_FLOAT
9449 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
9450 
   && TARGET_LONG_DOUBLE_128"
9451 
{
9452 
  rtx tmp = gen_reg_rtx (DFmode);
9453 
  expand_float (tmp, operands[1], false);
9454 
  emit_insn (gen_extenddftf2 (operands[0], tmp));
9455 
  DONE;
9456 
})
9457 
 
9458 
; fadd, but rounding towards zero.
9459 
; This is probably not the optimal code sequence.
9460 
(define_insn "fix_trunc_helper"
9461 
  [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9462 
        (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9463 
                   UNSPEC_FIX_TRUNC_TF))
9464 
   (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9465 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9466 
  "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9467 
  [(set_attr "type" "fp")
9468 
   (set_attr "length" "20")])
9469 
 
9470 
(define_expand "fix_trunctfsi2"
9471 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
9472 
        (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9473 
  "!TARGET_IEEEQUAD
9474 
   && (TARGET_POWER2 || TARGET_POWERPC)
9475 
   && TARGET_HARD_FLOAT
9476 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
9477 
   && TARGET_LONG_DOUBLE_128"
9478 
{
9479 
  if (TARGET_E500_DOUBLE)
9480 
    emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9481 
  else
9482 
    emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9483 
  DONE;
9484 
})
9485 
 
9486 
(define_expand "fix_trunctfsi2_fprs"
9487 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9488 
                   (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9489 
              (clobber (match_dup 2))
9490 
              (clobber (match_dup 3))
9491 
              (clobber (match_dup 4))
9492 
              (clobber (match_dup 5))])]
9493 
  "!TARGET_IEEEQUAD
9494 
   && (TARGET_POWER2 || TARGET_POWERPC)
9495 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9496 
{
9497 
  operands[2] = gen_reg_rtx (DFmode);
9498 
  operands[3] = gen_reg_rtx (DFmode);
9499 
  operands[4] = gen_reg_rtx (DImode);
9500 
  operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9501 
})
9502 
 
9503 
(define_insn_and_split "*fix_trunctfsi2_internal"
9504 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9505 
        (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9506 
   (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9507 
   (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9508 
   (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9509 
   (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9510 
  "!TARGET_IEEEQUAD
9511 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9512 
  "#"
9513 
  ""
9514 
  [(pc)]
9515 
{
9516 
  rtx lowword;
9517 
  emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9518 
 
9519 
  gcc_assert (MEM_P (operands[5]));
9520 
  lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9521 
 
9522 
  emit_insn (gen_fctiwz (operands[4], operands[2]));
9523 
  emit_move_insn (operands[5], operands[4]);
9524 
  emit_move_insn (operands[0], lowword);
9525 
  DONE;
9526 
})
9527 
 
9528 
(define_expand "negtf2"
9529 
  [(set (match_operand:TF 0 "gpc_reg_operand" "")
9530 
        (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9531 
  "!TARGET_IEEEQUAD
9532 
   && TARGET_HARD_FLOAT
9533 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
9534 
   && TARGET_LONG_DOUBLE_128"
9535 
  "")
9536 
 
9537 
(define_insn "negtf2_internal"
9538 
  [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9539 
        (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9540 
  "!TARGET_IEEEQUAD
9541 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9542 
  "*
9543 
{
9544 
  if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9545 
    return \"fneg %L0,%L1\;fneg %0,%1\";
9546 
  else
9547 
    return \"fneg %0,%1\;fneg %L0,%L1\";
9548 
}"
9549 
  [(set_attr "type" "fp")
9550 
   (set_attr "length" "8")])
9551 
 
9552 
(define_expand "abstf2"
9553 
  [(set (match_operand:TF 0 "gpc_reg_operand" "")
9554 
        (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9555 
  "!TARGET_IEEEQUAD
9556 
   && TARGET_HARD_FLOAT
9557 
   && (TARGET_FPRS || TARGET_E500_DOUBLE)
9558 
   && TARGET_LONG_DOUBLE_128"
9559 
  "
9560 
{
9561 
  rtx label = gen_label_rtx ();
9562 
  if (TARGET_E500_DOUBLE)
9563 
    {
9564 
      if (flag_finite_math_only && !flag_trapping_math)
9565 
        emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9566 
      else
9567 
        emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9568 
    }
9569 
  else
9570 
    emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9571 
  emit_label (label);
9572 
  DONE;
9573 
}")
9574 
 
9575 
(define_expand "abstf2_internal"
9576 
  [(set (match_operand:TF 0 "gpc_reg_operand" "")
9577 
        (match_operand:TF 1 "gpc_reg_operand" ""))
9578 
   (set (match_dup 3) (match_dup 5))
9579 
   (set (match_dup 5) (abs:DF (match_dup 5)))
9580 
   (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9581 
   (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9582 
                           (label_ref (match_operand 2 "" ""))
9583 
                           (pc)))
9584 
   (set (match_dup 6) (neg:DF (match_dup 6)))]
9585 
  "!TARGET_IEEEQUAD
9586 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9587 
   && TARGET_LONG_DOUBLE_128"
9588 
  "
9589 
{
9590 
  const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9591 
  const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9592 
  operands[3] = gen_reg_rtx (DFmode);
9593 
  operands[4] = gen_reg_rtx (CCFPmode);
9594 
  operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9595 
  operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9596 
}")
9597 
 
9598 
;; Next come the multi-word integer load and store and the load and store
9599 
;; multiple insns.
9600 
 
9601 
; List r->r after r->"o<>", otherwise reload will try to reload a
9602 
; non-offsettable address by using r->r which won't make progress.
9603 
(define_insn "*movdi_internal32"
9604 
  [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9605 
        (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9606 
  "! TARGET_POWERPC64
9607 
   && (gpc_reg_operand (operands[0], DImode)
9608 
       || gpc_reg_operand (operands[1], DImode))"
9609 
  "@
9610 
   #
9611 
   #
9612 
   #
9613 
   fmr %0,%1
9614 
   lfd%U1%X1 %0,%1
9615 
   stfd%U0%X0 %1,%0
9616 
   #"
9617 
  [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9618 
 
9619 
(define_split
9620 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
9621 
        (match_operand:DI 1 "const_int_operand" ""))]
9622 
  "! TARGET_POWERPC64 && reload_completed"
9623 
  [(set (match_dup 2) (match_dup 4))
9624 
   (set (match_dup 3) (match_dup 1))]
9625 
  "
9626 
{
9627 
  HOST_WIDE_INT value = INTVAL (operands[1]);
9628 
  operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9629 
                                       DImode);
9630 
  operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9631 
                                       DImode);
9632 
#if HOST_BITS_PER_WIDE_INT == 32
9633 
  operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9634 
#else
9635 
  operands[4] = GEN_INT (value >> 32);
9636 
  operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9637 
#endif
9638 
}")
9639 
 
9640 
(define_split
9641 
  [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9642 
        (match_operand:DIFD 1 "input_operand" ""))]
9643 
  "reload_completed && !TARGET_POWERPC64
9644 
   && gpr_or_gpr_p (operands[0], operands[1])"
9645 
  [(pc)]
9646 
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9647 
 
9648 
(define_insn "*movdi_mfpgpr"
9649 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9650 
        (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9651 
  "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9652 
   && (gpc_reg_operand (operands[0], DImode)
9653 
       || gpc_reg_operand (operands[1], DImode))"
9654 
  "@
9655 
   mr %0,%1
9656 
   ld%U1%X1 %0,%1
9657 
   std%U0%X0 %1,%0
9658 
   li %0,%1
9659 
   lis %0,%v1
9660 
   #
9661 
   {cal|la} %0,%a1
9662 
   fmr %0,%1
9663 
   lfd%U1%X1 %0,%1
9664 
   stfd%U0%X0 %1,%0
9665 
   mf%1 %0
9666 
   mt%0 %1
9667 
   {cror 0,0,0|nop}
9668 
   mftgpr %0,%1
9669 
   mffgpr %0,%1"
9670 
  [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9671 
   (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9672 
 
9673 
(define_insn "*movdi_internal64"
9674 
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9675 
        (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9676 
  "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9677 
   && (gpc_reg_operand (operands[0], DImode)
9678 
       || gpc_reg_operand (operands[1], DImode))"
9679 
  "@
9680 
   mr %0,%1
9681 
   ld%U1%X1 %0,%1
9682 
   std%U0%X0 %1,%0
9683 
   li %0,%1
9684 
   lis %0,%v1
9685 
   #
9686 
   {cal|la} %0,%a1
9687 
   fmr %0,%1
9688 
   lfd%U1%X1 %0,%1
9689 
   stfd%U0%X0 %1,%0
9690 
   mf%1 %0
9691 
   mt%0 %1
9692 
   {cror 0,0,0|nop}"
9693 
  [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9694 
   (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9695 
 
9696 
;; immediate value valid for a single instruction hiding in a const_double
9697 
(define_insn ""
9698 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9699 
        (match_operand:DI 1 "const_double_operand" "F"))]
9700 
  "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9701 
   && GET_CODE (operands[1]) == CONST_DOUBLE
9702 
   && num_insns_constant (operands[1], DImode) == 1"
9703 
  "*
9704 
{
9705 
  return ((unsigned HOST_WIDE_INT)
9706 
          (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9707 
         ? \"li %0,%1\" : \"lis %0,%v1\";
9708 
}")
9709 
 
9710 
;; Generate all one-bits and clear left or right.
9711 
;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9712 
(define_split
9713 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
9714 
        (match_operand:DI 1 "mask64_operand" ""))]
9715 
  "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9716 
  [(set (match_dup 0) (const_int -1))
9717 
   (set (match_dup 0)
9718 
        (and:DI (rotate:DI (match_dup 0)
9719 
                           (const_int 0))
9720 
                (match_dup 1)))]
9721 
  "")
9722 
 
9723 
;; Split a load of a large constant into the appropriate five-instruction
9724 
;; sequence.  Handle anything in a constant number of insns.
9725 
;; When non-easy constants can go in the TOC, this should use
9726 
;; easy_fp_constant predicate.
9727 
(define_split
9728 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
9729 
        (match_operand:DI 1 "const_int_operand" ""))]
9730 
  "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9731 
  [(set (match_dup 0) (match_dup 2))
9732 
   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9733 
  "
9734 
{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9735 
 
9736 
  if (tem == operands[0])
9737 
    DONE;
9738 
  else
9739 
    FAIL;
9740 
}")
9741 
 
9742 
(define_split
9743 
  [(set (match_operand:DI 0 "gpc_reg_operand" "")
9744 
        (match_operand:DI 1 "const_double_operand" ""))]
9745 
  "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9746 
  [(set (match_dup 0) (match_dup 2))
9747 
   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9748 
  "
9749 
{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9750 
 
9751 
  if (tem == operands[0])
9752 
    DONE;
9753 
  else
9754 
    FAIL;
9755 
}")
9756 
 
9757 
;; TImode is similar, except that we usually want to compute the address into
9758 
;; a register and use lsi/stsi (the exception is during reload).  MQ is also
9759 
;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9760 
 
9761 
;; We say that MQ is clobbered in the last alternative because the first
9762 
;; alternative would never get used otherwise since it would need a reload
9763 
;; while the 2nd alternative would not.  We put memory cases first so they
9764 
;; are preferred.  Otherwise, we'd try to reload the output instead of
9765 
;; giving the SCRATCH mq.
9766 
 
9767 
(define_insn "*movti_power"
9768 
  [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9769 
        (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9770 
   (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9771 
  "TARGET_POWER && ! TARGET_POWERPC64
9772 
   && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9773 
  "*
9774 
{
9775 
  switch (which_alternative)
9776 
    {
9777 
    default:
9778 
      gcc_unreachable ();
9779 
 
9780 
    case 0:
9781 
      if (TARGET_STRING)
9782 
        return \"{stsi|stswi} %1,%P0,16\";
9783 
    case 1:
9784 
    case 2:
9785 
      return \"#\";
9786 
    case 3:
9787 
      /* If the address is not used in the output, we can use lsi.  Otherwise,
9788 
         fall through to generating four loads.  */
9789 
      if (TARGET_STRING
9790 
          && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9791 
        return \"{lsi|lswi} %0,%P1,16\";
9792 
      /* ... fall through ...  */
9793 
    case 4:
9794 
    case 5:
9795 
      return \"#\";
9796 
    }
9797 
}"
9798 
  [(set_attr "type" "store,store,*,load,load,*")])
9799 
 
9800 
(define_insn "*movti_string"
9801 
  [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9802 
        (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9803 
  "! TARGET_POWER && ! TARGET_POWERPC64
9804 
   && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9805 
  "*
9806 
{
9807 
  switch (which_alternative)
9808 
    {
9809 
    default:
9810 
      gcc_unreachable ();
9811 
    case 0:
9812 
      if (TARGET_STRING)
9813 
        return \"{stsi|stswi} %1,%P0,16\";
9814 
    case 1:
9815 
    case 2:
9816 
      return \"#\";
9817 
    case 3:
9818 
      /* If the address is not used in the output, we can use lsi.  Otherwise,
9819 
         fall through to generating four loads.  */
9820 
      if (TARGET_STRING
9821 
          && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9822 
        return \"{lsi|lswi} %0,%P1,16\";
9823 
      /* ... fall through ...  */
9824 
    case 4:
9825 
    case 5:
9826 
      return \"#\";
9827 
    }
9828 
}"
9829 
  [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9830 
   (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9831 
                                          (const_string "always")
9832 
                                          (const_string "conditional")))])
9833 
 
9834 
(define_insn "*movti_ppc64"
9835 
  [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9836 
        (match_operand:TI 1 "input_operand" "r,r,m"))]
9837 
  "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9838 
    || gpc_reg_operand (operands[1], TImode)))
9839 
   && VECTOR_MEM_NONE_P (TImode)"
9840 
  "#"
9841 
  [(set_attr "type" "*,store,load")])
9842 
 
9843 
(define_split
9844 
  [(set (match_operand:TI 0 "gpc_reg_operand" "")
9845 
        (match_operand:TI 1 "const_double_operand" ""))]
9846 
  "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9847 
  [(set (match_dup 2) (match_dup 4))
9848 
   (set (match_dup 3) (match_dup 5))]
9849 
  "
9850 
{
9851 
  operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9852 
                                       TImode);
9853 
  operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9854 
                                       TImode);
9855 
  if (GET_CODE (operands[1]) == CONST_DOUBLE)
9856 
    {
9857 
      operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9858 
      operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9859 
    }
9860 
  else if (GET_CODE (operands[1]) == CONST_INT)
9861 
    {
9862 
      operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9863 
      operands[5] = operands[1];
9864 
    }
9865 
  else
9866 
    FAIL;
9867 
}")
9868 
 
9869 
(define_split
9870 
  [(set (match_operand:TI 0 "nonimmediate_operand" "")
9871 
        (match_operand:TI 1 "input_operand" ""))]
9872 
  "reload_completed && VECTOR_MEM_NONE_P (TImode)
9873 
   && gpr_or_gpr_p (operands[0], operands[1])"
9874 
  [(pc)]
9875 
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9876 
 
9877 
(define_expand "load_multiple"
9878 
  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9879 
                          (match_operand:SI 1 "" ""))
9880 
                     (use (match_operand:SI 2 "" ""))])]
9881 
  "TARGET_STRING && !TARGET_POWERPC64"
9882 
  "
9883 
{
9884 
  int regno;
9885 
  int count;
9886 
  rtx op1;
9887 
  int i;
9888 
 
9889 
  /* Support only loading a constant number of fixed-point registers from
9890 
     memory and only bother with this if more than two; the machine
9891 
     doesn't support more than eight.  */
9892 
  if (GET_CODE (operands[2]) != CONST_INT
9893 
      || INTVAL (operands[2]) <= 2
9894 
      || INTVAL (operands[2]) > 8
9895 
      || GET_CODE (operands[1]) != MEM
9896 
      || GET_CODE (operands[0]) != REG
9897 
      || REGNO (operands[0]) >= 32)
9898 
    FAIL;
9899 
 
9900 
  count = INTVAL (operands[2]);
9901 
  regno = REGNO (operands[0]);
9902 
 
9903 
  operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9904 
  op1 = replace_equiv_address (operands[1],
9905 
                               force_reg (SImode, XEXP (operands[1], 0)));
9906 
 
9907 
  for (i = 0; i < count; i++)
9908 
    XVECEXP (operands[3], 0, i)
9909 
      = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9910 
                     adjust_address_nv (op1, SImode, i * 4));
9911 
}")
9912 
 
9913 
(define_insn "*ldmsi8"
9914 
  [(match_parallel 0 "load_multiple_operation"
9915 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
9916 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9917 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
9918 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9919 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
9920 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9921 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
9922 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9923 
     (set (match_operand:SI 6 "gpc_reg_operand" "")
9924 
          (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9925 
     (set (match_operand:SI 7 "gpc_reg_operand" "")
9926 
          (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9927 
     (set (match_operand:SI 8 "gpc_reg_operand" "")
9928 
          (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9929 
     (set (match_operand:SI 9 "gpc_reg_operand" "")
9930 
          (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9931 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9932 
  "*
9933 
{ return rs6000_output_load_multiple (operands); }"
9934 
  [(set_attr "type" "load_ux")
9935 
   (set_attr "length" "32")])
9936 
 
9937 
(define_insn "*ldmsi7"
9938 
  [(match_parallel 0 "load_multiple_operation"
9939 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
9940 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9941 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
9942 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9943 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
9944 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9945 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
9946 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9947 
     (set (match_operand:SI 6 "gpc_reg_operand" "")
9948 
          (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9949 
     (set (match_operand:SI 7 "gpc_reg_operand" "")
9950 
          (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9951 
     (set (match_operand:SI 8 "gpc_reg_operand" "")
9952 
          (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9953 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9954 
  "*
9955 
{ return rs6000_output_load_multiple (operands); }"
9956 
  [(set_attr "type" "load_ux")
9957 
   (set_attr "length" "32")])
9958 
 
9959 
(define_insn "*ldmsi6"
9960 
  [(match_parallel 0 "load_multiple_operation"
9961 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
9962 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9963 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
9964 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9965 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
9966 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9967 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
9968 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9969 
     (set (match_operand:SI 6 "gpc_reg_operand" "")
9970 
          (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9971 
     (set (match_operand:SI 7 "gpc_reg_operand" "")
9972 
          (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9973 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9974 
  "*
9975 
{ return rs6000_output_load_multiple (operands); }"
9976 
  [(set_attr "type" "load_ux")
9977 
   (set_attr "length" "32")])
9978 
 
9979 
(define_insn "*ldmsi5"
9980 
  [(match_parallel 0 "load_multiple_operation"
9981 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
9982 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9983 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
9984 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9985 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
9986 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9987 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
9988 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9989 
     (set (match_operand:SI 6 "gpc_reg_operand" "")
9990 
          (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9991 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9992 
  "*
9993 
{ return rs6000_output_load_multiple (operands); }"
9994 
  [(set_attr "type" "load_ux")
9995 
   (set_attr "length" "32")])
9996 
 
9997 
(define_insn "*ldmsi4"
9998 
  [(match_parallel 0 "load_multiple_operation"
9999 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
10000 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10001 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
10002 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10003 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
10004 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10005 
     (set (match_operand:SI 5 "gpc_reg_operand" "")
10006 
          (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10007 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10008 
  "*
10009 
{ return rs6000_output_load_multiple (operands); }"
10010 
  [(set_attr "type" "load_ux")
10011 
   (set_attr "length" "32")])
10012 
 
10013 
(define_insn "*ldmsi3"
10014 
  [(match_parallel 0 "load_multiple_operation"
10015 
    [(set (match_operand:SI 2 "gpc_reg_operand" "")
10016 
          (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10017 
     (set (match_operand:SI 3 "gpc_reg_operand" "")
10018 
          (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10019 
     (set (match_operand:SI 4 "gpc_reg_operand" "")
10020 
          (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10021 
  "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10022 
  "*
10023 
{ return rs6000_output_load_multiple (operands); }"
10024 
  [(set_attr "type" "load_ux")
10025 
   (set_attr "length" "32")])
10026 
 
10027 
(define_expand "store_multiple"
10028 
  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10029 
                          (match_operand:SI 1 "" ""))
10030 
                     (clobber (scratch:SI))
10031 
                     (use (match_operand:SI 2 "" ""))])]
10032 
  "TARGET_STRING && !TARGET_POWERPC64"
10033 
  "
10034 
{
10035 
  int regno;
10036 
  int count;
10037 
  rtx to;
10038 
  rtx op0;
10039 
  int i;
10040 
 
10041 
  /* Support only storing a constant number of fixed-point registers to
10042 
     memory and only bother with this if more than two; the machine
10043 
     doesn't support more than eight.  */
10044 
  if (GET_CODE (operands[2]) != CONST_INT
10045 
      || INTVAL (operands[2]) <= 2
10046 
      || INTVAL (operands[2]) > 8
10047 
      || GET_CODE (operands[0]) != MEM
10048 
      || GET_CODE (operands[1]) != REG
10049 
      || REGNO (operands[1]) >= 32)
10050 
    FAIL;
10051 
 
10052 
  count = INTVAL (operands[2]);
10053 
  regno = REGNO (operands[1]);
10054 
 
10055 
  operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10056 
  to = force_reg (SImode, XEXP (operands[0], 0));
10057 
  op0 = replace_equiv_address (operands[0], to);
10058 
 
10059 
  XVECEXP (operands[3], 0, 0)
10060 
    = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10061 
  XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10062 
                                                 gen_rtx_SCRATCH (SImode));
10063 
 
10064 
  for (i = 1; i < count; i++)
10065 
    XVECEXP (operands[3], 0, i + 1)
10066 
      = gen_rtx_SET (VOIDmode,
10067 
                     adjust_address_nv (op0, SImode, i * 4),
10068 
                     gen_rtx_REG (SImode, regno + i));
10069 
}")
10070 
 
10071 
(define_insn "*stmsi8"
10072 
  [(match_parallel 0 "store_multiple_operation"
10073 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10074 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10075 
     (clobber (match_scratch:SI 3 "=X"))
10076 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10077 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10078 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10079 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10080 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10081 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
10082 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10083 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
10084 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10085 
          (match_operand:SI 8 "gpc_reg_operand" "r"))
10086 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10087 
          (match_operand:SI 9 "gpc_reg_operand" "r"))
10088 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10089 
          (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10090 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10091 
  "{stsi|stswi} %2,%1,%O0"
10092 
  [(set_attr "type" "store_ux")
10093 
   (set_attr "cell_micro" "always")])
10094 
 
10095 
(define_insn "*stmsi7"
10096 
  [(match_parallel 0 "store_multiple_operation"
10097 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10098 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10099 
     (clobber (match_scratch:SI 3 "=X"))
10100 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10101 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10102 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10103 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10104 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10105 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
10106 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10107 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
10108 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10109 
          (match_operand:SI 8 "gpc_reg_operand" "r"))
10110 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10111 
          (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10112 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10113 
  "{stsi|stswi} %2,%1,%O0"
10114 
  [(set_attr "type" "store_ux")
10115 
   (set_attr "cell_micro" "always")])
10116 
 
10117 
(define_insn "*stmsi6"
10118 
  [(match_parallel 0 "store_multiple_operation"
10119 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10120 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10121 
     (clobber (match_scratch:SI 3 "=X"))
10122 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10123 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10124 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10125 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10126 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10127 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
10128 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10129 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
10130 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10131 
          (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10132 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10133 
  "{stsi|stswi} %2,%1,%O0"
10134 
  [(set_attr "type" "store_ux")
10135 
   (set_attr "cell_micro" "always")])
10136 
 
10137 
(define_insn "*stmsi5"
10138 
  [(match_parallel 0 "store_multiple_operation"
10139 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10140 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10141 
     (clobber (match_scratch:SI 3 "=X"))
10142 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10143 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10144 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10145 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10146 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10147 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
10148 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10149 
          (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10150 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10151 
  "{stsi|stswi} %2,%1,%O0"
10152 
  [(set_attr "type" "store_ux")
10153 
   (set_attr "cell_micro" "always")])
10154 
 
10155 
(define_insn "*stmsi4"
10156 
  [(match_parallel 0 "store_multiple_operation"
10157 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10158 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10159 
     (clobber (match_scratch:SI 3 "=X"))
10160 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10161 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10162 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10163 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10164 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10165 
          (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10166 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10167 
  "{stsi|stswi} %2,%1,%O0"
10168 
  [(set_attr "type" "store_ux")
10169 
   (set_attr "cell_micro" "always")])
10170 
 
10171 
(define_insn "*stmsi3"
10172 
  [(match_parallel 0 "store_multiple_operation"
10173 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10174 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10175 
     (clobber (match_scratch:SI 3 "=X"))
10176 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10177 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10178 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10179 
          (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10180 
  "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10181 
  "{stsi|stswi} %2,%1,%O0"
10182 
  [(set_attr "type" "store_ux")
10183 
   (set_attr "cell_micro" "always")])
10184 
 
10185 
(define_insn "*stmsi8_power"
10186 
  [(match_parallel 0 "store_multiple_operation"
10187 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10188 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10189 
     (clobber (match_scratch:SI 3 "=q"))
10190 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10191 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10192 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10193 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10194 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10195 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
10196 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10197 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
10198 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10199 
          (match_operand:SI 8 "gpc_reg_operand" "r"))
10200 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10201 
          (match_operand:SI 9 "gpc_reg_operand" "r"))
10202 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10203 
          (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10204 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10205 
  "{stsi|stswi} %2,%1,%O0"
10206 
  [(set_attr "type" "store_ux")
10207 
   (set_attr "cell_micro" "always")])
10208 
 
10209 
(define_insn "*stmsi7_power"
10210 
  [(match_parallel 0 "store_multiple_operation"
10211 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10212 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10213 
     (clobber (match_scratch:SI 3 "=q"))
10214 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10215 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10216 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10217 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10218 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10219 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
10220 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10221 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
10222 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10223 
          (match_operand:SI 8 "gpc_reg_operand" "r"))
10224 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10225 
          (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10226 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10227 
  "{stsi|stswi} %2,%1,%O0"
10228 
  [(set_attr "type" "store_ux")
10229 
   (set_attr "cell_micro" "always")])
10230 
 
10231 
(define_insn "*stmsi6_power"
10232 
  [(match_parallel 0 "store_multiple_operation"
10233 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10234 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10235 
     (clobber (match_scratch:SI 3 "=q"))
10236 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10237 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10238 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10239 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10240 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10241 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
10242 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10243 
          (match_operand:SI 7 "gpc_reg_operand" "r"))
10244 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10245 
          (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10246 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10247 
  "{stsi|stswi} %2,%1,%O0"
10248 
  [(set_attr "type" "store_ux")
10249 
   (set_attr "cell_micro" "always")])
10250 
 
10251 
(define_insn "*stmsi5_power"
10252 
  [(match_parallel 0 "store_multiple_operation"
10253 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10254 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10255 
     (clobber (match_scratch:SI 3 "=q"))
10256 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10257 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10258 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10259 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10260 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10261 
          (match_operand:SI 6 "gpc_reg_operand" "r"))
10262 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10263 
          (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10264 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10265 
  "{stsi|stswi} %2,%1,%O0"
10266 
  [(set_attr "type" "store_ux")
10267 
   (set_attr "cell_micro" "always")])
10268 
 
10269 
(define_insn "*stmsi4_power"
10270 
  [(match_parallel 0 "store_multiple_operation"
10271 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10272 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10273 
     (clobber (match_scratch:SI 3 "=q"))
10274 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10275 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10276 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10277 
          (match_operand:SI 5 "gpc_reg_operand" "r"))
10278 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10279 
          (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10280 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10281 
  "{stsi|stswi} %2,%1,%O0"
10282 
  [(set_attr "type" "store_ux")
10283 
   (set_attr "cell_micro" "always")])
10284 
 
10285 
(define_insn "*stmsi3_power"
10286 
  [(match_parallel 0 "store_multiple_operation"
10287 
    [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10288 
          (match_operand:SI 2 "gpc_reg_operand" "r"))
10289 
     (clobber (match_scratch:SI 3 "=q"))
10290 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10291 
          (match_operand:SI 4 "gpc_reg_operand" "r"))
10292 
     (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10293 
          (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10294 
  "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10295 
  "{stsi|stswi} %2,%1,%O0"
10296 
  [(set_attr "type" "store_ux")
10297 
   (set_attr "cell_micro" "always")])
10298 
 
10299 
(define_expand "setmemsi"
10300 
  [(parallel [(set (match_operand:BLK 0 "" "")
10301 
                   (match_operand 2 "const_int_operand" ""))
10302 
              (use (match_operand:SI 1 "" ""))
10303 
              (use (match_operand:SI 3 "" ""))])]
10304 
  ""
10305 
  "
10306 
{
10307 
  /* If value to set is not zero, use the library routine.  */
10308 
  if (operands[2] != const0_rtx)
10309 
    FAIL;
10310 
 
10311 
  if (expand_block_clear (operands))
10312 
    DONE;
10313 
  else
10314 
    FAIL;
10315 
}")
10316 
 
10317 
;; String/block move insn.
10318 
;; Argument 0 is the destination
10319 
;; Argument 1 is the source
10320 
;; Argument 2 is the length
10321 
;; Argument 3 is the alignment
10322 
 
10323 
(define_expand "movmemsi"
10324 
  [(parallel [(set (match_operand:BLK 0 "" "")
10325 
                   (match_operand:BLK 1 "" ""))
10326 
              (use (match_operand:SI 2 "" ""))
10327 
              (use (match_operand:SI 3 "" ""))])]
10328 
  ""
10329 
  "
10330 
{
10331 
  if (expand_block_move (operands))
10332 
    DONE;
10333 
  else
10334 
    FAIL;
10335 
}")
10336 
 
10337 
;; Move up to 32 bytes at a time.  The fixed registers are needed because the
10338 
;; register allocator doesn't have a clue about allocating 8 word registers.
10339 
;; rD/rS = r5 is preferred, efficient form.
10340 
(define_expand "movmemsi_8reg"
10341 
  [(parallel [(set (match_operand 0 "" "")
10342 
                   (match_operand 1 "" ""))
10343 
              (use (match_operand 2 "" ""))
10344 
              (use (match_operand 3 "" ""))
10345 
              (clobber (reg:SI  5))
10346 
              (clobber (reg:SI  6))
10347 
              (clobber (reg:SI  7))
10348 
              (clobber (reg:SI  8))
10349 
              (clobber (reg:SI  9))
10350 
              (clobber (reg:SI 10))
10351 
              (clobber (reg:SI 11))
10352 
              (clobber (reg:SI 12))
10353 
              (clobber (match_scratch:SI 4 ""))])]
10354 
  "TARGET_STRING"
10355 
  "")
10356 
 
10357 
(define_insn ""
10358 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10359 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10360 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10361 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10362 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10363 
   (clobber (reg:SI  6))
10364 
   (clobber (reg:SI  7))
10365 
   (clobber (reg:SI  8))
10366 
   (clobber (reg:SI  9))
10367 
   (clobber (reg:SI 10))
10368 
   (clobber (reg:SI 11))
10369 
   (clobber (reg:SI 12))
10370 
   (clobber (match_scratch:SI 5 "=q"))]
10371 
  "TARGET_STRING && TARGET_POWER
10372 
   && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10373 
       || INTVAL (operands[2]) == 0)
10374 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10375 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10376 
   && REGNO (operands[4]) == 5"
10377 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10378 
  [(set_attr "type" "store_ux")
10379 
   (set_attr "cell_micro" "always")
10380 
   (set_attr "length" "8")])
10381 
 
10382 
(define_insn ""
10383 
  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10384 
        (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10385 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10386 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10387 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10388 
   (clobber (reg:SI  6))
10389 
   (clobber (reg:SI  7))
10390 
   (clobber (reg:SI  8))
10391 
   (clobber (reg:SI  9))
10392 
   (clobber (reg:SI 10))
10393 
   (clobber (reg:SI 11))
10394 
   (clobber (reg:SI 12))
10395 
   (clobber (match_scratch:SI 5 "=X"))]
10396 
  "TARGET_STRING && ! TARGET_POWER
10397 
   && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10398 
       || INTVAL (operands[2]) == 0)
10399 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10400 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10401 
   && REGNO (operands[4]) == 5"
10402 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10403 
  [(set_attr "type" "store_ux")
10404 
   (set_attr "cell_micro" "always")
10405 
   (set_attr "length" "8")])
10406 
 
10407 
;; Move up to 24 bytes at a time.  The fixed registers are needed because the
10408 
;; register allocator doesn't have a clue about allocating 6 word registers.
10409 
;; rD/rS = r5 is preferred, efficient form.
10410 
(define_expand "movmemsi_6reg"
10411 
  [(parallel [(set (match_operand 0 "" "")
10412 
                   (match_operand 1 "" ""))
10413 
              (use (match_operand 2 "" ""))
10414 
              (use (match_operand 3 "" ""))
10415 
              (clobber (reg:SI  5))
10416 
              (clobber (reg:SI  6))
10417 
              (clobber (reg:SI  7))
10418 
              (clobber (reg:SI  8))
10419 
              (clobber (reg:SI  9))
10420 
              (clobber (reg:SI 10))
10421 
              (clobber (match_scratch:SI 4 ""))])]
10422 
  "TARGET_STRING"
10423 
  "")
10424 
 
10425 
(define_insn ""
10426 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10427 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10428 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10429 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10430 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10431 
   (clobber (reg:SI  6))
10432 
   (clobber (reg:SI  7))
10433 
   (clobber (reg:SI  8))
10434 
   (clobber (reg:SI  9))
10435 
   (clobber (reg:SI 10))
10436 
   (clobber (match_scratch:SI 5 "=q"))]
10437 
  "TARGET_STRING && TARGET_POWER
10438 
   && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10439 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10440 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10441 
   && REGNO (operands[4]) == 5"
10442 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10443 
  [(set_attr "type" "store_ux")
10444 
   (set_attr "cell_micro" "always")
10445 
   (set_attr "length" "8")])
10446 
 
10447 
(define_insn ""
10448 
  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10449 
        (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10450 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10451 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10452 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10453 
   (clobber (reg:SI  6))
10454 
   (clobber (reg:SI  7))
10455 
   (clobber (reg:SI  8))
10456 
   (clobber (reg:SI  9))
10457 
   (clobber (reg:SI 10))
10458 
   (clobber (match_scratch:SI 5 "=X"))]
10459 
  "TARGET_STRING && ! TARGET_POWER
10460 
   && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10461 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10462 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10463 
   && REGNO (operands[4]) == 5"
10464 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10465 
  [(set_attr "type" "store_ux")
10466 
   (set_attr "cell_micro" "always")
10467 
   (set_attr "length" "8")])
10468 
 
10469 
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10470 
;; problems with TImode.
10471 
;; rD/rS = r5 is preferred, efficient form.
10472 
(define_expand "movmemsi_4reg"
10473 
  [(parallel [(set (match_operand 0 "" "")
10474 
                   (match_operand 1 "" ""))
10475 
              (use (match_operand 2 "" ""))
10476 
              (use (match_operand 3 "" ""))
10477 
              (clobber (reg:SI 5))
10478 
              (clobber (reg:SI 6))
10479 
              (clobber (reg:SI 7))
10480 
              (clobber (reg:SI 8))
10481 
              (clobber (match_scratch:SI 4 ""))])]
10482 
  "TARGET_STRING"
10483 
  "")
10484 
 
10485 
(define_insn ""
10486 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10487 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10488 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10489 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10490 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10491 
   (clobber (reg:SI 6))
10492 
   (clobber (reg:SI 7))
10493 
   (clobber (reg:SI 8))
10494 
   (clobber (match_scratch:SI 5 "=q"))]
10495 
  "TARGET_STRING && TARGET_POWER
10496 
   && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10497 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10498 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10499 
   && REGNO (operands[4]) == 5"
10500 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10501 
  [(set_attr "type" "store_ux")
10502 
   (set_attr "cell_micro" "always")
10503 
   (set_attr "length" "8")])
10504 
 
10505 
(define_insn ""
10506 
  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10507 
        (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10508 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10509 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10510 
   (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10511 
   (clobber (reg:SI 6))
10512 
   (clobber (reg:SI 7))
10513 
   (clobber (reg:SI 8))
10514 
   (clobber (match_scratch:SI 5 "=X"))]
10515 
  "TARGET_STRING && ! TARGET_POWER
10516 
   && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10517 
   && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10518 
   && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10519 
   && REGNO (operands[4]) == 5"
10520 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10521 
  [(set_attr "type" "store_ux")
10522 
   (set_attr "cell_micro" "always")
10523 
   (set_attr "length" "8")])
10524 
 
10525 
;; Move up to 8 bytes at a time.
10526 
(define_expand "movmemsi_2reg"
10527 
  [(parallel [(set (match_operand 0 "" "")
10528 
                   (match_operand 1 "" ""))
10529 
              (use (match_operand 2 "" ""))
10530 
              (use (match_operand 3 "" ""))
10531 
              (clobber (match_scratch:DI 4 ""))
10532 
              (clobber (match_scratch:SI 5 ""))])]
10533 
  "TARGET_STRING && ! TARGET_POWERPC64"
10534 
  "")
10535 
 
10536 
(define_insn ""
10537 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10538 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10539 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10540 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10541 
   (clobber (match_scratch:DI 4 "=&r"))
10542 
   (clobber (match_scratch:SI 5 "=q"))]
10543 
  "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10544 
   && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10545 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10546 
  [(set_attr "type" "store_ux")
10547 
   (set_attr "cell_micro" "always")
10548 
   (set_attr "length" "8")])
10549 
 
10550 
(define_insn ""
10551 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10552 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10553 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10554 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10555 
   (clobber (match_scratch:DI 4 "=&r"))
10556 
   (clobber (match_scratch:SI 5 "=X"))]
10557 
  "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10558 
   && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10559 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10560 
  [(set_attr "type" "store_ux")
10561 
   (set_attr "cell_micro" "always")
10562 
   (set_attr "length" "8")])
10563 
 
10564 
;; Move up to 4 bytes at a time.
10565 
(define_expand "movmemsi_1reg"
10566 
  [(parallel [(set (match_operand 0 "" "")
10567 
                   (match_operand 1 "" ""))
10568 
              (use (match_operand 2 "" ""))
10569 
              (use (match_operand 3 "" ""))
10570 
              (clobber (match_scratch:SI 4 ""))
10571 
              (clobber (match_scratch:SI 5 ""))])]
10572 
  "TARGET_STRING"
10573 
  "")
10574 
 
10575 
(define_insn ""
10576 
  [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10577 
        (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10578 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10579 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10580 
   (clobber (match_scratch:SI 4 "=&r"))
10581 
   (clobber (match_scratch:SI 5 "=q"))]
10582 
  "TARGET_STRING && TARGET_POWER
10583 
   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10584 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10585 
  [(set_attr "type" "store_ux")
10586 
   (set_attr "cell_micro" "always")
10587 
   (set_attr "length" "8")])
10588 
 
10589 
(define_insn ""
10590 
  [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10591 
        (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10592 
   (use (match_operand:SI 2 "immediate_operand" "i"))
10593 
   (use (match_operand:SI 3 "immediate_operand" "i"))
10594 
   (clobber (match_scratch:SI 4 "=&r"))
10595 
   (clobber (match_scratch:SI 5 "=X"))]
10596 
  "TARGET_STRING && ! TARGET_POWER
10597 
   && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10598 
  "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10599 
  [(set_attr "type" "store_ux")
10600 
   (set_attr "cell_micro" "always")
10601 
   (set_attr "length" "8")])
10602 
 
10603 
;; Define insns that do load or store with update.  Some of these we can
10604 
;; get by using pre-decrement or pre-increment, but the hardware can also
10605 
;; do cases where the increment is not the size of the object.
10606 
;;
10607 
;; In all these cases, we use operands 0 and 1 for the register being
10608 
;; incremented because those are the operands that local-alloc will
10609 
;; tie and these are the pair most likely to be tieable (and the ones
10610 
;; that will benefit the most).
10611 
 
10612 
(define_insn "*movdi_update1"
10613 
  [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10614 
        (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10615 
                         (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10616 
   (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10617 
        (plus:DI (match_dup 1) (match_dup 2)))]
10618 
  "TARGET_POWERPC64 && TARGET_UPDATE
10619 
   && (!avoiding_indexed_address_p (DImode)
10620 
       || !gpc_reg_operand (operands[2], DImode))"
10621 
  "@
10622 
   ldux %3,%0,%2
10623 
   ldu %3,%2(%0)"
10624 
  [(set_attr "type" "load_ux,load_u")])
10625 
 
10626 
(define_insn "movdi__update"
10627 
  [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10628 
                         (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10629 
        (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10630 
   (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10631 
        (plus:P (match_dup 1) (match_dup 2)))]
10632 
  "TARGET_POWERPC64 && TARGET_UPDATE
10633 
   && (!avoiding_indexed_address_p (Pmode)
10634 
       || !gpc_reg_operand (operands[2], Pmode)
10635 
       || (REG_P (operands[0])
10636 
           && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10637 
  "@
10638 
   stdux %3,%0,%2
10639 
   stdu %3,%2(%0)"
10640 
  [(set_attr "type" "store_ux,store_u")])
10641 
 
10642 
;; This pattern is only conditional on TARGET_POWERPC64, as it is
10643 
;; needed for stack allocation, even if the user passes -mno-update.
10644 
(define_insn "movdi__update_stack"
10645 
  [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10646 
                         (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10647 
        (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10648 
   (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10649 
        (plus:P (match_dup 1) (match_dup 2)))]
10650 
  "TARGET_POWERPC64"
10651 
  "@
10652 
   stdux %3,%0,%2
10653 
   stdu %3,%2(%0)"
10654 
  [(set_attr "type" "store_ux,store_u")])
10655 
 
10656 
(define_insn "*movsi_update1"
10657 
  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10658 
        (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10659 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10660 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10661 
        (plus:SI (match_dup 1) (match_dup 2)))]
10662 
  "TARGET_UPDATE
10663 
   && (!avoiding_indexed_address_p (SImode)
10664 
       || !gpc_reg_operand (operands[2], SImode))"
10665 
  "@
10666 
   {lux|lwzux} %3,%0,%2
10667 
   {lu|lwzu} %3,%2(%0)"
10668 
  [(set_attr "type" "load_ux,load_u")])
10669 
 
10670 
(define_insn "*movsi_update2"
10671 
  [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10672 
        (sign_extend:DI
10673 
         (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10674 
                          (match_operand:DI 2 "gpc_reg_operand" "r")))))
10675 
   (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10676 
        (plus:DI (match_dup 1) (match_dup 2)))]
10677 
  "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10678 
   && !avoiding_indexed_address_p (DImode)"
10679 
  "lwaux %3,%0,%2"
10680 
  [(set_attr "type" "load_ext_ux")])
10681 
 
10682 
(define_insn "movsi_update"
10683 
  [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10684 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10685 
        (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10686 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10687 
        (plus:SI (match_dup 1) (match_dup 2)))]
10688 
  "TARGET_UPDATE
10689 
   && (!avoiding_indexed_address_p (SImode)
10690 
       || !gpc_reg_operand (operands[2], SImode)
10691 
       || (REG_P (operands[0])
10692 
           && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10693 
  "@
10694 
   {stux|stwux} %3,%0,%2
10695 
   {stu|stwu} %3,%2(%0)"
10696 
  [(set_attr "type" "store_ux,store_u")])
10697 
 
10698 
;; This is an unconditional pattern; needed for stack allocation, even
10699 
;; if the user passes -mno-update.
10700 
(define_insn "movsi_update_stack"
10701 
  [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10702 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10703 
        (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10704 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10705 
        (plus:SI (match_dup 1) (match_dup 2)))]
10706 
  ""
10707 
  "@
10708 
   {stux|stwux} %3,%0,%2
10709 
   {stu|stwu} %3,%2(%0)"
10710 
  [(set_attr "type" "store_ux,store_u")])
10711 
 
10712 
(define_insn "*movhi_update1"
10713 
  [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10714 
        (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10715 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10716 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10717 
        (plus:SI (match_dup 1) (match_dup 2)))]
10718 
  "TARGET_UPDATE
10719 
   && (!avoiding_indexed_address_p (SImode)
10720 
       || !gpc_reg_operand (operands[2], SImode))"
10721 
  "@
10722 
   lhzux %3,%0,%2
10723 
   lhzu %3,%2(%0)"
10724 
  [(set_attr "type" "load_ux,load_u")])
10725 
 
10726 
(define_insn "*movhi_update2"
10727 
  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10728 
        (zero_extend:SI
10729 
         (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10730 
                          (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10731 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10732 
        (plus:SI (match_dup 1) (match_dup 2)))]
10733 
  "TARGET_UPDATE
10734 
   && (!avoiding_indexed_address_p (SImode)
10735 
       || !gpc_reg_operand (operands[2], SImode))"
10736 
  "@
10737 
   lhzux %3,%0,%2
10738 
   lhzu %3,%2(%0)"
10739 
  [(set_attr "type" "load_ux,load_u")])
10740 
 
10741 
(define_insn "*movhi_update3"
10742 
  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10743 
        (sign_extend:SI
10744 
         (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10745 
                          (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10746 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10747 
        (plus:SI (match_dup 1) (match_dup 2)))]
10748 
  "TARGET_UPDATE && rs6000_gen_cell_microcode
10749 
   && (!avoiding_indexed_address_p (SImode)
10750 
       || !gpc_reg_operand (operands[2], SImode))"
10751 
  "@
10752 
   lhaux %3,%0,%2
10753 
   lhau %3,%2(%0)"
10754 
  [(set_attr "type" "load_ext_ux,load_ext_u")])
10755 
 
10756 
(define_insn "*movhi_update4"
10757 
  [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10758 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10759 
        (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10760 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10761 
        (plus:SI (match_dup 1) (match_dup 2)))]
10762 
  "TARGET_UPDATE
10763 
   && (!avoiding_indexed_address_p (SImode)
10764 
       || !gpc_reg_operand (operands[2], SImode))"
10765 
  "@
10766 
   sthux %3,%0,%2
10767 
   sthu %3,%2(%0)"
10768 
  [(set_attr "type" "store_ux,store_u")])
10769 
 
10770 
(define_insn "*movqi_update1"
10771 
  [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10772 
        (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10773 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10774 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10775 
        (plus:SI (match_dup 1) (match_dup 2)))]
10776 
  "TARGET_UPDATE
10777 
   && (!avoiding_indexed_address_p (SImode)
10778 
       || !gpc_reg_operand (operands[2], SImode))"
10779 
  "@
10780 
   lbzux %3,%0,%2
10781 
   lbzu %3,%2(%0)"
10782 
  [(set_attr "type" "load_ux,load_u")])
10783 
 
10784 
(define_insn "*movqi_update2"
10785 
  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10786 
        (zero_extend:SI
10787 
         (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10788 
                          (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10789 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10790 
        (plus:SI (match_dup 1) (match_dup 2)))]
10791 
  "TARGET_UPDATE
10792 
   && (!avoiding_indexed_address_p (SImode)
10793 
       || !gpc_reg_operand (operands[2], SImode))"
10794 
  "@
10795 
   lbzux %3,%0,%2
10796 
   lbzu %3,%2(%0)"
10797 
  [(set_attr "type" "load_ux,load_u")])
10798 
 
10799 
(define_insn "*movqi_update3"
10800 
  [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10801 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10802 
        (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10803 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10804 
        (plus:SI (match_dup 1) (match_dup 2)))]
10805 
  "TARGET_UPDATE
10806 
   && (!avoiding_indexed_address_p (SImode)
10807 
       || !gpc_reg_operand (operands[2], SImode))"
10808 
  "@
10809 
   stbux %3,%0,%2
10810 
   stbu %3,%2(%0)"
10811 
  [(set_attr "type" "store_ux,store_u")])
10812 
 
10813 
(define_insn "*movsf_update1"
10814 
  [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10815 
        (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10816 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10817 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10818 
        (plus:SI (match_dup 1) (match_dup 2)))]
10819 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10820 
   && (!avoiding_indexed_address_p (SImode)
10821 
       || !gpc_reg_operand (operands[2], SImode))"
10822 
  "@
10823 
   lfsux %3,%0,%2
10824 
   lfsu %3,%2(%0)"
10825 
  [(set_attr "type" "fpload_ux,fpload_u")])
10826 
 
10827 
(define_insn "*movsf_update2"
10828 
  [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10829 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10830 
        (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10831 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10832 
        (plus:SI (match_dup 1) (match_dup 2)))]
10833 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10834 
   && (!avoiding_indexed_address_p (SImode)
10835 
       || !gpc_reg_operand (operands[2], SImode))"
10836 
  "@
10837 
   stfsux %3,%0,%2
10838 
   stfsu %3,%2(%0)"
10839 
  [(set_attr "type" "fpstore_ux,fpstore_u")])
10840 
 
10841 
(define_insn "*movsf_update3"
10842 
  [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10843 
        (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10844 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10845 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10846 
        (plus:SI (match_dup 1) (match_dup 2)))]
10847 
  "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10848 
   && (!avoiding_indexed_address_p (SImode)
10849 
       || !gpc_reg_operand (operands[2], SImode))"
10850 
  "@
10851 
   {lux|lwzux} %3,%0,%2
10852 
   {lu|lwzu} %3,%2(%0)"
10853 
  [(set_attr "type" "load_ux,load_u")])
10854 
 
10855 
(define_insn "*movsf_update4"
10856 
  [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10857 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10858 
        (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10859 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10860 
        (plus:SI (match_dup 1) (match_dup 2)))]
10861 
  "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10862 
   && (!avoiding_indexed_address_p (SImode)
10863 
       || !gpc_reg_operand (operands[2], SImode))"
10864 
  "@
10865 
   {stux|stwux} %3,%0,%2
10866 
   {stu|stwu} %3,%2(%0)"
10867 
  [(set_attr "type" "store_ux,store_u")])
10868 
 
10869 
(define_insn "*movdf_update1"
10870 
  [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10871 
        (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10872 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10873 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10874 
        (plus:SI (match_dup 1) (match_dup 2)))]
10875 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10876 
   && (!avoiding_indexed_address_p (SImode)
10877 
       || !gpc_reg_operand (operands[2], SImode))"
10878 
  "@
10879 
   lfdux %3,%0,%2
10880 
   lfdu %3,%2(%0)"
10881 
  [(set_attr "type" "fpload_ux,fpload_u")])
10882 
 
10883 
(define_insn "*movdf_update2"
10884 
  [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10885 
                         (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10886 
        (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10887 
   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10888 
        (plus:SI (match_dup 1) (match_dup 2)))]
10889 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10890 
   && (!avoiding_indexed_address_p (SImode)
10891 
       || !gpc_reg_operand (operands[2], SImode))"
10892 
  "@
10893 
   stfdux %3,%0,%2
10894 
   stfdu %3,%2(%0)"
10895 
  [(set_attr "type" "fpstore_ux,fpstore_u")])
10896 
 
10897 
;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10898 
 
10899 
(define_insn "*lfq_power2"
10900 
  [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10901 
        (match_operand:V2DF 1 "memory_operand" ""))]
10902 
  "TARGET_POWER2
10903 
   && TARGET_HARD_FLOAT && TARGET_FPRS"
10904 
  "lfq%U1%X1 %0,%1")
10905 
 
10906 
(define_peephole2
10907 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
10908 
        (match_operand:DF 1 "memory_operand" ""))
10909 
   (set (match_operand:DF 2 "gpc_reg_operand" "")
10910 
        (match_operand:DF 3 "memory_operand" ""))]
10911 
  "TARGET_POWER2
10912 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10913 
   && registers_ok_for_quad_peep (operands[0], operands[2])
10914 
   && mems_ok_for_quad_peep (operands[1], operands[3])"
10915 
  [(set (match_dup 0)
10916 
        (match_dup 1))]
10917 
  "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10918 
   operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10919 
 
10920 
(define_insn "*stfq_power2"
10921 
  [(set (match_operand:V2DF 0 "memory_operand" "")
10922 
        (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10923 
  "TARGET_POWER2
10924 
   && TARGET_HARD_FLOAT && TARGET_FPRS"
10925 
  "stfq%U0%X0 %1,%0")
10926 
 
10927 
 
10928 
(define_peephole2
10929 
  [(set (match_operand:DF 0 "memory_operand" "")
10930 
        (match_operand:DF 1 "gpc_reg_operand" ""))
10931 
   (set (match_operand:DF 2 "memory_operand" "")
10932 
        (match_operand:DF 3 "gpc_reg_operand" ""))]
10933 
  "TARGET_POWER2
10934 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10935 
   && registers_ok_for_quad_peep (operands[1], operands[3])
10936 
   && mems_ok_for_quad_peep (operands[0], operands[2])"
10937 
  [(set (match_dup 0)
10938 
        (match_dup 1))]
10939 
  "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10940 
   operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10941 
 
10942 
;; After inserting conditional returns we can sometimes have
10943 
;; unnecessary register moves.  Unfortunately we cannot have a
10944 
;; modeless peephole here, because some single SImode sets have early
10945 
;; clobber outputs.  Although those sets expand to multi-ppc-insn
10946 
;; sequences, using get_attr_length here will smash the operands
10947 
;; array.  Neither is there an early_cobbler_p predicate.
10948 
;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10949 
(define_peephole2
10950 
  [(set (match_operand:DF 0 "gpc_reg_operand" "")
10951 
        (match_operand:DF 1 "any_operand" ""))
10952 
   (set (match_operand:DF 2 "gpc_reg_operand" "")
10953 
        (match_dup 0))]
10954 
  "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10955 
   && peep2_reg_dead_p (2, operands[0])"
10956 
  [(set (match_dup 2) (match_dup 1))])
10957 
 
10958 
(define_peephole2
10959 
  [(set (match_operand:SF 0 "gpc_reg_operand" "")
10960 
        (match_operand:SF 1 "any_operand" ""))
10961 
   (set (match_operand:SF 2 "gpc_reg_operand" "")
10962 
        (match_dup 0))]
10963 
  "peep2_reg_dead_p (2, operands[0])"
10964 
  [(set (match_dup 2) (match_dup 1))])
10965 
 
10966 
 
10967 
;; TLS support.
10968 
 
10969 
;; Mode attributes for different ABIs.
10970 
(define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10971 
(define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10972 
(define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10973 
(define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10974 
 
10975 
(define_insn_and_split "tls_gd_aix"
10976 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10977 
        (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10978 
              (match_operand 4 "" "g")))
10979 
   (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10980 
                    (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10981 
                   UNSPEC_TLSGD)
10982 
   (clobber (reg:SI LR_REGNO))]
10983 
  "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10984 
  "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10985 
  "&& TARGET_TLS_MARKERS"
10986 
  [(set (match_dup 0)
10987 
        (unspec:TLSmode [(match_dup 1)
10988 
                         (match_dup 2)]
10989 
                        UNSPEC_TLSGD))
10990 
   (parallel [(set (match_dup 0)
10991 
                   (call (mem:TLSmode (match_dup 3))
10992 
                         (match_dup 4)))
10993 
              (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10994 
              (clobber (reg:SI LR_REGNO))])]
10995 
  ""
10996 
  [(set_attr "type" "two")
10997 
   (set_attr "length" "12")])
10998 
 
10999 
(define_insn_and_split "tls_gd_sysv"
11000 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11001 
        (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11002 
              (match_operand 4 "" "g")))
11003 
   (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11004 
                    (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11005 
                   UNSPEC_TLSGD)
11006 
   (clobber (reg:SI LR_REGNO))]
11007 
  "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11008 
{
11009 
  if (flag_pic)
11010 
    {
11011 
      if (TARGET_SECURE_PLT && flag_pic == 2)
11012 
        return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11013 
      else
11014 
        return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11015 
    }
11016 
  else
11017 
    return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11018 
}
11019 
  "&& TARGET_TLS_MARKERS"
11020 
  [(set (match_dup 0)
11021 
        (unspec:TLSmode [(match_dup 1)
11022 
                         (match_dup 2)]
11023 
                        UNSPEC_TLSGD))
11024 
   (parallel [(set (match_dup 0)
11025 
                   (call (mem:TLSmode (match_dup 3))
11026 
                         (match_dup 4)))
11027 
              (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11028 
              (clobber (reg:SI LR_REGNO))])]
11029 
  ""
11030 
  [(set_attr "type" "two")
11031 
   (set_attr "length" "8")])
11032 
 
11033 
(define_insn "*tls_gd"
11034 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11035 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11036 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11037 
                        UNSPEC_TLSGD))]
11038 
  "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11039 
  "addi %0,%1,%2@got@tlsgd"
11040 
  [(set_attr "length" "4")])
11041 
 
11042 
(define_insn "*tls_gd_call_aix"
11043 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11044 
        (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11045 
              (match_operand 2 "" "g")))
11046 
   (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11047 
                   UNSPEC_TLSGD)
11048 
   (clobber (reg:SI LR_REGNO))]
11049 
  "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11050 
  "bl %z1(%3@tlsgd)\;%."
11051 
  [(set_attr "type" "branch")
11052 
   (set_attr "length" "8")])
11053 
 
11054 
(define_insn "*tls_gd_call_sysv"
11055 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11056 
        (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11057 
              (match_operand 2 "" "g")))
11058 
   (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11059 
                   UNSPEC_TLSGD)
11060 
   (clobber (reg:SI LR_REGNO))]
11061 
  "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11062 
{
11063 
  if (flag_pic)
11064 
    {
11065 
      if (TARGET_SECURE_PLT && flag_pic == 2)
11066 
        return "bl %z1+32768(%3@tlsgd)@plt";
11067 
      return "bl %z1(%3@tlsgd)@plt";
11068 
    }
11069 
  return "bl %z1(%3@tlsgd)";
11070 
}
11071 
  [(set_attr "type" "branch")
11072 
   (set_attr "length" "4")])
11073 
 
11074 
(define_insn_and_split "tls_ld_aix"
11075 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11076 
        (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11077 
              (match_operand 3 "" "g")))
11078 
   (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11079 
                   UNSPEC_TLSLD)
11080 
   (clobber (reg:SI LR_REGNO))]
11081 
  "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11082 
  "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
11083 
  "&& TARGET_TLS_MARKERS"
11084 
  [(set (match_dup 0)
11085 
        (unspec:TLSmode [(match_dup 1)]
11086 
                        UNSPEC_TLSLD))
11087 
   (parallel [(set (match_dup 0)
11088 
                   (call (mem:TLSmode (match_dup 2))
11089 
                         (match_dup 3)))
11090 
              (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11091 
              (clobber (reg:SI LR_REGNO))])]
11092 
  ""
11093 
  [(set_attr "length" "12")])
11094 
 
11095 
(define_insn_and_split "tls_ld_sysv"
11096 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11097 
        (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11098 
              (match_operand 3 "" "g")))
11099 
   (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11100 
                   UNSPEC_TLSLD)
11101 
   (clobber (reg:SI LR_REGNO))]
11102 
  "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11103 
{
11104 
  if (flag_pic)
11105 
    {
11106 
      if (TARGET_SECURE_PLT && flag_pic == 2)
11107 
        return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11108 
      else
11109 
        return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11110 
    }
11111 
  else
11112 
    return "addi %0,%1,%&@got@tlsld\;bl %z2";
11113 
}
11114 
  "&& TARGET_TLS_MARKERS"
11115 
  [(set (match_dup 0)
11116 
        (unspec:TLSmode [(match_dup 1)]
11117 
                        UNSPEC_TLSLD))
11118 
   (parallel [(set (match_dup 0)
11119 
                   (call (mem:TLSmode (match_dup 2))
11120 
                         (match_dup 3)))
11121 
              (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11122 
              (clobber (reg:SI LR_REGNO))])]
11123 
  ""
11124 
  [(set_attr "length" "8")])
11125 
 
11126 
(define_insn "*tls_ld"
11127 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11128 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11129 
                        UNSPEC_TLSLD))]
11130 
  "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11131 
  "addi %0,%1,%&@got@tlsld"
11132 
  [(set_attr "length" "4")])
11133 
 
11134 
(define_insn "*tls_ld_call_aix"
11135 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11136 
        (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11137 
              (match_operand 2 "" "g")))
11138 
   (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11139 
   (clobber (reg:SI LR_REGNO))]
11140 
  "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11141 
  "bl %z1(%&@tlsld)\;%."
11142 
  [(set_attr "type" "branch")
11143 
   (set_attr "length" "8")])
11144 
 
11145 
(define_insn "*tls_ld_call_sysv"
11146 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11147 
        (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11148 
              (match_operand 2 "" "g")))
11149 
   (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11150 
   (clobber (reg:SI LR_REGNO))]
11151 
  "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11152 
{
11153 
  if (flag_pic)
11154 
    {
11155 
      if (TARGET_SECURE_PLT && flag_pic == 2)
11156 
        return "bl %z1+32768(%&@tlsld)@plt";
11157 
      return "bl %z1(%&@tlsld)@plt";
11158 
    }
11159 
  return "bl %z1(%&@tlsld)";
11160 
}
11161 
  [(set_attr "type" "branch")
11162 
   (set_attr "length" "4")])
11163 
 
11164 
(define_insn "tls_dtprel_"
11165 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11166 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11167 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11168 
                        UNSPEC_TLSDTPREL))]
11169 
  "HAVE_AS_TLS"
11170 
  "addi %0,%1,%2@dtprel")
11171 
 
11172 
(define_insn "tls_dtprel_ha_"
11173 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11174 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11175 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11176 
                        UNSPEC_TLSDTPRELHA))]
11177 
  "HAVE_AS_TLS"
11178 
  "addis %0,%1,%2@dtprel@ha")
11179 
 
11180 
(define_insn "tls_dtprel_lo_"
11181 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11182 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11183 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11184 
                        UNSPEC_TLSDTPRELLO))]
11185 
  "HAVE_AS_TLS"
11186 
  "addi %0,%1,%2@dtprel@l")
11187 
 
11188 
(define_insn "tls_got_dtprel_"
11189 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11190 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11191 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11192 
                        UNSPEC_TLSGOTDTPREL))]
11193 
  "HAVE_AS_TLS"
11194 
  "l %0,%2@got@dtprel(%1)")
11195 
 
11196 
(define_insn "tls_tprel_"
11197 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11198 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11199 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11200 
                        UNSPEC_TLSTPREL))]
11201 
  "HAVE_AS_TLS"
11202 
  "addi %0,%1,%2@tprel")
11203 
 
11204 
(define_insn "tls_tprel_ha_"
11205 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11206 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11207 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11208 
                        UNSPEC_TLSTPRELHA))]
11209 
  "HAVE_AS_TLS"
11210 
  "addis %0,%1,%2@tprel@ha")
11211 
 
11212 
(define_insn "tls_tprel_lo_"
11213 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11214 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11215 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11216 
                        UNSPEC_TLSTPRELLO))]
11217 
  "HAVE_AS_TLS"
11218 
  "addi %0,%1,%2@tprel@l")
11219 
 
11220 
;; "b" output constraint here and on tls_tls input to support linker tls
11221 
;; optimization.  The linker may edit the instructions emitted by a
11222 
;; tls_got_tprel/tls_tls pair to addis,addi.
11223 
(define_insn "tls_got_tprel_"
11224 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11225 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11226 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11227 
                        UNSPEC_TLSGOTTPREL))]
11228 
  "HAVE_AS_TLS"
11229 
  "l %0,%2@got@tprel(%1)")
11230 
 
11231 
(define_insn "tls_tls_"
11232 
  [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11233 
        (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11234 
                         (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11235 
                        UNSPEC_TLSTLS))]
11236 
  "HAVE_AS_TLS"
11237 
  "add %0,%1,%2@tls")
11238 
 
11239 
 
11240 
;; Next come insns related to the calling sequence.
11241 
;;
11242 
;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11243 
;; We move the back-chain and decrement the stack pointer.
11244 
 
11245 
(define_expand "allocate_stack"
11246 
  [(set (match_operand 0 "gpc_reg_operand" "")
11247 
        (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11248 
   (set (reg 1)
11249 
        (minus (reg 1) (match_dup 1)))]
11250 
  ""
11251 
  "
11252 
{ rtx chain = gen_reg_rtx (Pmode);
11253 
  rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11254 
  rtx neg_op0;
11255 
  rtx insn, par, set, mem;
11256 
 
11257 
  emit_move_insn (chain, stack_bot);
11258 
 
11259 
  /* Check stack bounds if necessary.  */
11260 
  if (crtl->limit_stack)
11261 
    {
11262 
      rtx available;
11263 
      available = expand_binop (Pmode, sub_optab,
11264 
                                stack_pointer_rtx, stack_limit_rtx,
11265 
                                NULL_RTX, 1, OPTAB_WIDEN);
11266 
      emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11267 
    }
11268 
 
11269 
  if (GET_CODE (operands[1]) != CONST_INT
11270 
      || INTVAL (operands[1]) < -32767
11271 
      || INTVAL (operands[1]) > 32768)
11272 
    {
11273 
      neg_op0 = gen_reg_rtx (Pmode);
11274 
      if (TARGET_32BIT)
11275 
        emit_insn (gen_negsi2 (neg_op0, operands[1]));
11276 
      else
11277 
        emit_insn (gen_negdi2 (neg_op0, operands[1]));
11278 
    }
11279 
  else
11280 
    neg_op0 = GEN_INT (- INTVAL (operands[1]));
11281 
 
11282 
  insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11283 
                                       : gen_movdi_di_update_stack))
11284 
                        (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11285 
                         chain));
11286 
  /* Since we didn't use gen_frame_mem to generate the MEM, grab
11287 
     it now and set the alias set/attributes. The above gen_*_update
11288 
     calls will generate a PARALLEL with the MEM set being the first
11289 
     operation. */
11290 
  par = PATTERN (insn);
11291 
  gcc_assert (GET_CODE (par) == PARALLEL);
11292 
  set = XVECEXP (par, 0, 0);
11293 
  gcc_assert (GET_CODE (set) == SET);
11294 
  mem = SET_DEST (set);
11295 
  gcc_assert (MEM_P (mem));
11296 
  MEM_NOTRAP_P (mem) = 1;
11297 
  set_mem_alias_set (mem, get_frame_alias_set ());
11298 
 
11299 
  emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11300 
  DONE;
11301 
}")
11302 
 
11303 
;; These patterns say how to save and restore the stack pointer.  We need not
11304 
;; save the stack pointer at function level since we are careful to
11305 
;; preserve the backchain.  At block level, we have to restore the backchain
11306 
;; when we restore the stack pointer.
11307 
;;
11308 
;; For nonlocal gotos, we must save both the stack pointer and its
11309 
;; backchain and restore both.  Note that in the nonlocal case, the
11310 
;; save area is a memory location.
11311 
 
11312 
(define_expand "save_stack_function"
11313 
  [(match_operand 0 "any_operand" "")
11314 
   (match_operand 1 "any_operand" "")]
11315 
  ""
11316 
  "DONE;")
11317 
 
11318 
(define_expand "restore_stack_function"
11319 
  [(match_operand 0 "any_operand" "")
11320 
   (match_operand 1 "any_operand" "")]
11321 
  ""
11322 
  "DONE;")
11323 
 
11324 
;; Adjust stack pointer (op0) to a new value (op1).
11325 
;; First copy old stack backchain to new location, and ensure that the
11326 
;; scheduler won't reorder the sp assignment before the backchain write.
11327 
(define_expand "restore_stack_block"
11328 
  [(set (match_dup 2) (match_dup 3))
11329 
   (set (match_dup 4) (match_dup 2))
11330 
   (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11331 
   (set (match_operand 0 "register_operand" "")
11332 
        (match_operand 1 "register_operand" ""))]
11333 
  ""
11334 
  "
11335 
{
11336 
  operands[1] = force_reg (Pmode, operands[1]);
11337 
  operands[2] = gen_reg_rtx (Pmode);
11338 
  operands[3] = gen_frame_mem (Pmode, operands[0]);
11339 
  operands[4] = gen_frame_mem (Pmode, operands[1]);
11340 
  operands[5] = gen_frame_mem (BLKmode, operands[0]);
11341 
}")
11342 
 
11343 
(define_expand "save_stack_nonlocal"
11344 
  [(set (match_dup 3) (match_dup 4))
11345 
   (set (match_operand 0 "memory_operand" "") (match_dup 3))
11346 
   (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11347 
  ""
11348 
  "
11349 
{
11350 
  int units_per_word = (TARGET_32BIT) ? 4 : 8;
11351 
 
11352 
  /* Copy the backchain to the first word, sp to the second.  */
11353 
  operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11354 
  operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11355 
  operands[3] = gen_reg_rtx (Pmode);
11356 
  operands[4] = gen_frame_mem (Pmode, operands[1]);
11357 
}")
11358 
 
11359 
(define_expand "restore_stack_nonlocal"
11360 
  [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11361 
   (set (match_dup 3) (match_dup 4))
11362 
   (set (match_dup 5) (match_dup 2))
11363 
   (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11364 
   (set (match_operand 0 "register_operand" "") (match_dup 3))]
11365 
  ""
11366 
  "
11367 
{
11368 
  int units_per_word = (TARGET_32BIT) ? 4 : 8;
11369 
 
11370 
  /* Restore the backchain from the first word, sp from the second.  */
11371 
  operands[2] = gen_reg_rtx (Pmode);
11372 
  operands[3] = gen_reg_rtx (Pmode);
11373 
  operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11374 
  operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11375 
  operands[5] = gen_frame_mem (Pmode, operands[3]);
11376 
  operands[6] = gen_frame_mem (BLKmode, operands[0]);
11377 
}")
11378 
 
11379 
;; TOC register handling.
11380 
 
11381 
;; Code to initialize the TOC register...
11382 
 
11383 
(define_insn "load_toc_aix_si"
11384 
  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11385 
                   (unspec:SI [(const_int 0)] UNSPEC_TOC))
11386 
              (use (reg:SI 2))])]
11387 
  "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11388 
  "*
11389 
{
11390 
  char buf[30];
11391 
  ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11392 
  operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11393 
  operands[2] = gen_rtx_REG (Pmode, 2);
11394 
  return \"{l|lwz} %0,%1(%2)\";
11395 
}"
11396 
  [(set_attr "type" "load")])
11397 
 
11398 
(define_insn "load_toc_aix_di"
11399 
  [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11400 
                   (unspec:DI [(const_int 0)] UNSPEC_TOC))
11401 
              (use (reg:DI 2))])]
11402 
  "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11403 
  "*
11404 
{
11405 
  char buf[30];
11406 
#ifdef TARGET_RELOCATABLE
11407 
  ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11408 
                               !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11409 
#else
11410 
  ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11411 
#endif
11412 
  if (TARGET_ELF)
11413 
    strcat (buf, \"@toc\");
11414 
  operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11415 
  operands[2] = gen_rtx_REG (Pmode, 2);
11416 
  return \"ld %0,%1(%2)\";
11417 
}"
11418 
  [(set_attr "type" "load")])
11419 
 
11420 
(define_insn "load_toc_v4_pic_si"
11421 
  [(set (reg:SI LR_REGNO)
11422 
        (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11423 
  "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11424 
  "bl _GLOBAL_OFFSET_TABLE_@local-4"
11425 
  [(set_attr "type" "branch")
11426 
   (set_attr "length" "4")])
11427 
 
11428 
(define_insn "load_toc_v4_PIC_1"
11429 
  [(set (reg:SI LR_REGNO)
11430 
        (match_operand:SI 0 "immediate_operand" "s"))
11431 
   (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11432 
  "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11433 
   && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11434 
  "bcl 20,31,%0\\n%0:"
11435 
  [(set_attr "type" "branch")
11436 
   (set_attr "length" "4")])
11437 
 
11438 
(define_insn "load_toc_v4_PIC_1b"
11439 
  [(set (reg:SI LR_REGNO)
11440 
        (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11441 
                    (label_ref (match_operand 1 "" ""))]
11442 
                UNSPEC_TOCPTR))
11443 
   (match_dup 1)]
11444 
  "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11445 
  "bcl 20,31,$+8\;.long %0-$"
11446 
  [(set_attr "type" "branch")
11447 
   (set_attr "length" "8")])
11448 
 
11449 
(define_insn "load_toc_v4_PIC_2"
11450 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11451 
        (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11452 
                   (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11453 
                             (match_operand:SI 3 "immediate_operand" "s")))))]
11454 
  "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11455 
  "{l|lwz} %0,%2-%3(%1)"
11456 
  [(set_attr "type" "load")])
11457 
 
11458 
(define_insn "load_toc_v4_PIC_3b"
11459 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
11460 
        (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11461 
                 (high:SI
11462 
                   (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11463 
                             (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11464 
  "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11465 
  "{cau|addis} %0,%1,%2-%3@ha")
11466 
 
11467 
(define_insn "load_toc_v4_PIC_3c"
11468 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11469 
        (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11470 
                   (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11471 
                             (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11472 
  "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11473 
  "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
11474 
 
11475 
;; If the TOC is shared over a translation unit, as happens with all
11476 
;; the kinds of PIC that we support, we need to restore the TOC
11477 
;; pointer only when jumping over units of translation.
11478 
;; On Darwin, we need to reload the picbase.
11479 
 
11480 
(define_expand "builtin_setjmp_receiver"
11481 
  [(use (label_ref (match_operand 0 "" "")))]
11482 
  "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11483 
   || (TARGET_TOC && TARGET_MINIMAL_TOC)
11484 
   || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11485 
  "
11486 
{
11487 
#if TARGET_MACHO
11488 
  if (DEFAULT_ABI == ABI_DARWIN)
11489 
    {
11490 
      rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11491 
      rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11492 
      rtx tmplabrtx;
11493 
      char tmplab[20];
11494 
 
11495 
      crtl->uses_pic_offset_table = 1;
11496 
      ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11497 
                                  CODE_LABEL_NUMBER (operands[0]));
11498 
      tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11499 
 
11500 
      emit_insn (gen_load_macho_picbase (tmplabrtx));
11501 
      emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11502 
      emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11503 
    }
11504 
  else
11505 
#endif
11506 
    rs6000_emit_load_toc_table (FALSE);
11507 
  DONE;
11508 
}")
11509 
 
11510 
;; Elf specific ways of loading addresses for non-PIC code.
11511 
;; The output of this could be r0, but we make a very strong
11512 
;; preference for a base register because it will usually
11513 
;; be needed there.
11514 
(define_insn "elf_high"
11515 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11516 
        (high:SI (match_operand 1 "" "")))]
11517 
  "TARGET_ELF && ! TARGET_64BIT"
11518 
  "{liu|lis} %0,%1@ha")
11519 
 
11520 
(define_insn "elf_low"
11521 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11522 
        (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11523 
                   (match_operand 2 "" "")))]
11524 
   "TARGET_ELF && ! TARGET_64BIT"
11525 
   "@
11526 
    {cal|la} %0,%2@l(%1)
11527 
    {ai|addic} %0,%1,%K2")
11528 
 
11529 
;; A function pointer under AIX is a pointer to a data area whose first word
11530 
;; contains the actual address of the function, whose second word contains a
11531 
;; pointer to its TOC, and whose third word contains a value to place in the
11532 
;; static chain register (r11).  Note that if we load the static chain, our
11533 
;; "trampoline" need not have any executable code.
11534 
 
11535 
(define_expand "call_indirect_aix32"
11536 
  [(set (match_dup 2)
11537 
        (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11538 
   (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11539 
        (reg:SI 2))
11540 
   (set (reg:SI 11)
11541 
        (mem:SI (plus:SI (match_dup 0)
11542 
                         (const_int 8))))
11543 
   (parallel [(call (mem:SI (match_dup 2))
11544 
                    (match_operand 1 "" ""))
11545 
              (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11546 
              (use (reg:SI 11))
11547 
              (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11548 
              (clobber (reg:SI LR_REGNO))])]
11549 
  "TARGET_32BIT"
11550 
  "
11551 
{ operands[2] = gen_reg_rtx (SImode); }")
11552 
 
11553 
(define_expand "call_indirect_aix64"
11554 
  [(set (match_dup 2)
11555 
        (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11556 
   (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11557 
        (reg:DI 2))
11558 
   (set (reg:DI 11)
11559 
        (mem:DI (plus:DI (match_dup 0)
11560 
                         (const_int 16))))
11561 
   (parallel [(call (mem:SI (match_dup 2))
11562 
                    (match_operand 1 "" ""))
11563 
              (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11564 
              (use (reg:DI 11))
11565 
              (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11566 
              (clobber (reg:SI LR_REGNO))])]
11567 
  "TARGET_64BIT"
11568 
  "
11569 
{ operands[2] = gen_reg_rtx (DImode); }")
11570 
 
11571 
(define_expand "call_value_indirect_aix32"
11572 
  [(set (match_dup 3)
11573 
        (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11574 
   (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11575 
        (reg:SI 2))
11576 
   (set (reg:SI 11)
11577 
        (mem:SI (plus:SI (match_dup 1)
11578 
                         (const_int 8))))
11579 
   (parallel [(set (match_operand 0 "" "")
11580 
                   (call (mem:SI (match_dup 3))
11581 
                         (match_operand 2 "" "")))
11582 
              (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11583 
              (use (reg:SI 11))
11584 
              (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11585 
              (clobber (reg:SI LR_REGNO))])]
11586 
  "TARGET_32BIT"
11587 
  "
11588 
{ operands[3] = gen_reg_rtx (SImode); }")
11589 
 
11590 
(define_expand "call_value_indirect_aix64"
11591 
  [(set (match_dup 3)
11592 
        (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11593 
   (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11594 
        (reg:DI 2))
11595 
   (set (reg:DI 11)
11596 
        (mem:DI (plus:DI (match_dup 1)
11597 
                         (const_int 16))))
11598 
   (parallel [(set (match_operand 0 "" "")
11599 
                   (call (mem:SI (match_dup 3))
11600 
                         (match_operand 2 "" "")))
11601 
              (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11602 
              (use (reg:DI 11))
11603 
              (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11604 
              (clobber (reg:SI LR_REGNO))])]
11605 
  "TARGET_64BIT"
11606 
  "
11607 
{ operands[3] = gen_reg_rtx (DImode); }")
11608 
 
11609 
;; Now the definitions for the call and call_value insns
11610 
(define_expand "call"
11611 
  [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11612 
                    (match_operand 1 "" ""))
11613 
              (use (match_operand 2 "" ""))
11614 
              (clobber (reg:SI LR_REGNO))])]
11615 
  ""
11616 
  "
11617 
{
11618 
#if TARGET_MACHO
11619 
  if (MACHOPIC_INDIRECT)
11620 
    operands[0] = machopic_indirect_call_target (operands[0]);
11621 
#endif
11622 
 
11623 
  gcc_assert (GET_CODE (operands[0]) == MEM);
11624 
  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11625 
 
11626 
  operands[0] = XEXP (operands[0], 0);
11627 
 
11628 
  if (GET_CODE (operands[0]) != SYMBOL_REF
11629 
      || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11630 
      || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11631 
    {
11632 
      if (INTVAL (operands[2]) & CALL_LONG)
11633 
        operands[0] = rs6000_longcall_ref (operands[0]);
11634 
 
11635 
      switch (DEFAULT_ABI)
11636 
        {
11637 
        case ABI_V4:
11638 
        case ABI_DARWIN:
11639 
          operands[0] = force_reg (Pmode, operands[0]);
11640 
          break;
11641 
 
11642 
        case ABI_AIX:
11643 
          /* AIX function pointers are really pointers to a three word
11644 
             area.  */
11645 
          emit_call_insn (TARGET_32BIT
11646 
                          ? gen_call_indirect_aix32 (force_reg (SImode,
11647 
                                                                operands[0]),
11648 
                                                     operands[1])
11649 
                          : gen_call_indirect_aix64 (force_reg (DImode,
11650 
                                                                operands[0]),
11651 
                                                     operands[1]));
11652 
          DONE;
11653 
 
11654 
        default:
11655 
          gcc_unreachable ();
11656 
        }
11657 
    }
11658 
}")
11659 
 
11660 
(define_expand "call_value"
11661 
  [(parallel [(set (match_operand 0 "" "")
11662 
                   (call (mem:SI (match_operand 1 "address_operand" ""))
11663 
                         (match_operand 2 "" "")))
11664 
              (use (match_operand 3 "" ""))
11665 
              (clobber (reg:SI LR_REGNO))])]
11666 
  ""
11667 
  "
11668 
{
11669 
#if TARGET_MACHO
11670 
  if (MACHOPIC_INDIRECT)
11671 
    operands[1] = machopic_indirect_call_target (operands[1]);
11672 
#endif
11673 
 
11674 
  gcc_assert (GET_CODE (operands[1]) == MEM);
11675 
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11676 
 
11677 
  operands[1] = XEXP (operands[1], 0);
11678 
 
11679 
  if (GET_CODE (operands[1]) != SYMBOL_REF
11680 
      || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11681 
      || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11682 
    {
11683 
      if (INTVAL (operands[3]) & CALL_LONG)
11684 
        operands[1] = rs6000_longcall_ref (operands[1]);
11685 
 
11686 
      switch (DEFAULT_ABI)
11687 
        {
11688 
        case ABI_V4:
11689 
        case ABI_DARWIN:
11690 
          operands[1] = force_reg (Pmode, operands[1]);
11691 
          break;
11692 
 
11693 
        case ABI_AIX:
11694 
          /* AIX function pointers are really pointers to a three word
11695 
             area.  */
11696 
          emit_call_insn (TARGET_32BIT
11697 
                          ? gen_call_value_indirect_aix32 (operands[0],
11698 
                                                           force_reg (SImode,
11699 
                                                                      operands[1]),
11700 
                                                           operands[2])
11701 
                          : gen_call_value_indirect_aix64 (operands[0],
11702 
                                                           force_reg (DImode,
11703 
                                                                      operands[1]),
11704 
                                                           operands[2]));
11705 
          DONE;
11706 
 
11707 
        default:
11708 
          gcc_unreachable ();
11709 
        }
11710 
    }
11711 
}")
11712 
 
11713 
;; Call to function in current module.  No TOC pointer reload needed.
11714 
;; Operand2 is nonzero if we are using the V.4 calling sequence and
11715 
;; either the function was not prototyped, or it was prototyped as a
11716 
;; variable argument function.  It is > 0 if FP registers were passed
11717 
;; and < 0 if they were not.
11718 
 
11719 
(define_insn "*call_local32"
11720 
  [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11721 
         (match_operand 1 "" "g,g"))
11722 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
11723 
   (clobber (reg:SI LR_REGNO))]
11724 
  "(INTVAL (operands[2]) & CALL_LONG) == 0"
11725 
  "*
11726 
{
11727 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11728 
    output_asm_insn (\"crxor 6,6,6\", operands);
11729 
 
11730 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11731 
    output_asm_insn (\"creqv 6,6,6\", operands);
11732 
 
11733 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11734 
}"
11735 
  [(set_attr "type" "branch")
11736 
   (set_attr "length" "4,8")])
11737 
 
11738 
(define_insn "*call_local64"
11739 
  [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11740 
         (match_operand 1 "" "g,g"))
11741 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
11742 
   (clobber (reg:SI LR_REGNO))]
11743 
  "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11744 
  "*
11745 
{
11746 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11747 
    output_asm_insn (\"crxor 6,6,6\", operands);
11748 
 
11749 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11750 
    output_asm_insn (\"creqv 6,6,6\", operands);
11751 
 
11752 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11753 
}"
11754 
  [(set_attr "type" "branch")
11755 
   (set_attr "length" "4,8")])
11756 
 
11757 
(define_insn "*call_value_local32"
11758 
  [(set (match_operand 0 "" "")
11759 
        (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11760 
              (match_operand 2 "" "g,g")))
11761 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
11762 
   (clobber (reg:SI LR_REGNO))]
11763 
  "(INTVAL (operands[3]) & CALL_LONG) == 0"
11764 
  "*
11765 
{
11766 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11767 
    output_asm_insn (\"crxor 6,6,6\", operands);
11768 
 
11769 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11770 
    output_asm_insn (\"creqv 6,6,6\", operands);
11771 
 
11772 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11773 
}"
11774 
  [(set_attr "type" "branch")
11775 
   (set_attr "length" "4,8")])
11776 
 
11777 
 
11778 
(define_insn "*call_value_local64"
11779 
  [(set (match_operand 0 "" "")
11780 
        (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11781 
              (match_operand 2 "" "g,g")))
11782 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
11783 
   (clobber (reg:SI LR_REGNO))]
11784 
  "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11785 
  "*
11786 
{
11787 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11788 
    output_asm_insn (\"crxor 6,6,6\", operands);
11789 
 
11790 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11791 
    output_asm_insn (\"creqv 6,6,6\", operands);
11792 
 
11793 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11794 
}"
11795 
  [(set_attr "type" "branch")
11796 
   (set_attr "length" "4,8")])
11797 
 
11798 
;; Call to function which may be in another module.  Restore the TOC
11799 
;; pointer (r2) after the call unless this is System V.
11800 
;; Operand2 is nonzero if we are using the V.4 calling sequence and
11801 
;; either the function was not prototyped, or it was prototyped as a
11802 
;; variable argument function.  It is > 0 if FP registers were passed
11803 
;; and < 0 if they were not.
11804 
 
11805 
(define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11806 
  [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11807 
                 (match_operand 1 "" "g,g"))
11808 
   (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11809 
   (use (reg:SI 11))
11810 
   (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11811 
   (clobber (reg:SI LR_REGNO))]
11812 
  "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11813 
  "#"
11814 
  "&& reload_completed"
11815 
  [(set (reg:SI 2)
11816 
        (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11817 
   (parallel [(call (mem:SI (match_dup 0))
11818 
                    (match_dup 1))
11819 
              (use (reg:SI 2))
11820 
              (use (reg:SI 11))
11821 
              (set (reg:SI 2)
11822 
                   (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11823 
              (clobber (reg:SI LR_REGNO))])]
11824 
  ""
11825 
  [(set_attr "type" "jmpreg")
11826 
   (set_attr "length" "12")])
11827 
 
11828 
(define_insn "*call_indirect_nonlocal_aix32"
11829 
  [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11830 
         (match_operand 1 "" "g,g"))
11831 
   (use (reg:SI 2))
11832 
   (use (reg:SI 11))
11833 
   (set (reg:SI 2)
11834 
        (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11835 
   (clobber (reg:SI LR_REGNO))]
11836 
  "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11837 
  "b%T0l\;{l|lwz} 2,20(1)"
11838 
  [(set_attr "type" "jmpreg")
11839 
   (set_attr "length" "8")])
11840 
 
11841 
(define_insn "*call_nonlocal_aix32"
11842 
  [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11843 
         (match_operand 1 "" "g"))
11844 
   (use (match_operand:SI 2 "immediate_operand" "O"))
11845 
   (clobber (reg:SI LR_REGNO))]
11846 
  "TARGET_32BIT
11847 
   && DEFAULT_ABI == ABI_AIX
11848 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
11849 
  "bl %z0\;%."
11850 
  [(set_attr "type" "branch")
11851 
   (set_attr "length" "8")])
11852 
 
11853 
(define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11854 
  [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11855 
                 (match_operand 1 "" "g,g"))
11856 
   (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11857 
                         (const_int 8))))
11858 
   (use (reg:DI 11))
11859 
   (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11860 
   (clobber (reg:SI LR_REGNO))]
11861 
  "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11862 
  "#"
11863 
  "&& reload_completed"
11864 
  [(set (reg:DI 2)
11865 
        (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11866 
   (parallel [(call (mem:SI (match_dup 0))
11867 
                    (match_dup 1))
11868 
              (use (reg:DI 2))
11869 
              (use (reg:DI 11))
11870 
              (set (reg:DI 2)
11871 
                   (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11872 
              (clobber (reg:SI LR_REGNO))])]
11873 
  ""
11874 
  [(set_attr "type" "jmpreg")
11875 
   (set_attr "length" "12")])
11876 
 
11877 
(define_insn "*call_indirect_nonlocal_aix64"
11878 
  [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11879 
         (match_operand 1 "" "g,g"))
11880 
   (use (reg:DI 2))
11881 
   (use (reg:DI 11))
11882 
   (set (reg:DI 2)
11883 
        (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11884 
   (clobber (reg:SI LR_REGNO))]
11885 
  "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11886 
  "b%T0l\;ld 2,40(1)"
11887 
  [(set_attr "type" "jmpreg")
11888 
   (set_attr "length" "8")])
11889 
 
11890 
(define_insn "*call_nonlocal_aix64"
11891 
  [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11892 
         (match_operand 1 "" "g"))
11893 
   (use (match_operand:SI 2 "immediate_operand" "O"))
11894 
   (clobber (reg:SI LR_REGNO))]
11895 
  "TARGET_64BIT
11896 
   && DEFAULT_ABI == ABI_AIX
11897 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
11898 
  "bl %z0\;%."
11899 
  [(set_attr "type" "branch")
11900 
   (set_attr "length" "8")])
11901 
 
11902 
(define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11903 
  [(set (match_operand 0 "" "")
11904 
        (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11905 
                      (match_operand 2 "" "g,g")))
11906 
        (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11907 
                              (const_int 4))))
11908 
        (use (reg:SI 11))
11909 
        (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11910 
        (clobber (reg:SI LR_REGNO))]
11911 
  "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11912 
  "#"
11913 
  "&& reload_completed"
11914 
  [(set (reg:SI 2)
11915 
        (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11916 
   (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11917 
                                       (match_dup 2)))
11918 
              (use (reg:SI 2))
11919 
              (use (reg:SI 11))
11920 
              (set (reg:SI 2)
11921 
                   (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11922 
              (clobber (reg:SI LR_REGNO))])]
11923 
  ""
11924 
  [(set_attr "type" "jmpreg")
11925 
   (set_attr "length" "12")])
11926 
 
11927 
(define_insn "*call_value_indirect_nonlocal_aix32"
11928 
  [(set (match_operand 0 "" "")
11929 
        (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11930 
              (match_operand 2 "" "g,g")))
11931 
   (use (reg:SI 2))
11932 
   (use (reg:SI 11))
11933 
   (set (reg:SI 2)
11934 
        (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11935 
   (clobber (reg:SI LR_REGNO))]
11936 
  "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11937 
  "b%T1l\;{l|lwz} 2,20(1)"
11938 
  [(set_attr "type" "jmpreg")
11939 
   (set_attr "length" "8")])
11940 
 
11941 
(define_insn "*call_value_nonlocal_aix32"
11942 
  [(set (match_operand 0 "" "")
11943 
        (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11944 
              (match_operand 2 "" "g")))
11945 
   (use (match_operand:SI 3 "immediate_operand" "O"))
11946 
   (clobber (reg:SI LR_REGNO))]
11947 
  "TARGET_32BIT
11948 
   && DEFAULT_ABI == ABI_AIX
11949 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
11950 
  "bl %z1\;%."
11951 
  [(set_attr "type" "branch")
11952 
   (set_attr "length" "8")])
11953 
 
11954 
(define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11955 
  [(set (match_operand 0 "" "")
11956 
        (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11957 
                      (match_operand 2 "" "g,g")))
11958 
        (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11959 
                              (const_int 8))))
11960 
        (use (reg:DI 11))
11961 
        (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11962 
        (clobber (reg:SI LR_REGNO))]
11963 
  "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11964 
  "#"
11965 
  "&& reload_completed"
11966 
  [(set (reg:DI 2)
11967 
        (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11968 
   (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11969 
                                       (match_dup 2)))
11970 
              (use (reg:DI 2))
11971 
              (use (reg:DI 11))
11972 
              (set (reg:DI 2)
11973 
                   (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11974 
              (clobber (reg:SI LR_REGNO))])]
11975 
  ""
11976 
  [(set_attr "type" "jmpreg")
11977 
   (set_attr "length" "12")])
11978 
 
11979 
(define_insn "*call_value_indirect_nonlocal_aix64"
11980 
  [(set (match_operand 0 "" "")
11981 
        (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11982 
              (match_operand 2 "" "g,g")))
11983 
   (use (reg:DI 2))
11984 
   (use (reg:DI 11))
11985 
   (set (reg:DI 2)
11986 
        (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11987 
   (clobber (reg:SI LR_REGNO))]
11988 
  "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11989 
  "b%T1l\;ld 2,40(1)"
11990 
  [(set_attr "type" "jmpreg")
11991 
   (set_attr "length" "8")])
11992 
 
11993 
(define_insn "*call_value_nonlocal_aix64"
11994 
  [(set (match_operand 0 "" "")
11995 
        (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11996 
              (match_operand 2 "" "g")))
11997 
   (use (match_operand:SI 3 "immediate_operand" "O"))
11998 
   (clobber (reg:SI LR_REGNO))]
11999 
  "TARGET_64BIT
12000 
   && DEFAULT_ABI == ABI_AIX
12001 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
12002 
  "bl %z1\;%."
12003 
  [(set_attr "type" "branch")
12004 
   (set_attr "length" "8")])
12005 
 
12006 
;; A function pointer under System V is just a normal pointer
12007 
;; operands[0] is the function pointer
12008 
;; operands[1] is the stack size to clean up
12009 
;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12010 
;; which indicates how to set cr1
12011 
 
12012 
(define_insn "*call_indirect_nonlocal_sysv"
12013 
  [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12014 
         (match_operand 1 "" "g,g,g,g"))
12015 
   (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12016 
   (clobber (reg:SI LR_REGNO))]
12017 
  "DEFAULT_ABI == ABI_V4
12018 
   || DEFAULT_ABI == ABI_DARWIN"
12019 
{
12020 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12021 
    output_asm_insn ("crxor 6,6,6", operands);
12022 
 
12023 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12024 
    output_asm_insn ("creqv 6,6,6", operands);
12025 
 
12026 
  return "b%T0l";
12027 
}
12028 
  [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12029 
   (set_attr "length" "4,4,8,8")])
12030 
 
12031 
(define_insn_and_split "*call_nonlocal_sysv"
12032 
  [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12033 
         (match_operand 1 "" "g,g"))
12034 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
12035 
   (clobber (reg:SI LR_REGNO))]
12036 
  "(DEFAULT_ABI == ABI_DARWIN
12037 
   || (DEFAULT_ABI == ABI_V4
12038 
       && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12039 
{
12040 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12041 
    output_asm_insn ("crxor 6,6,6", operands);
12042 
 
12043 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12044 
    output_asm_insn ("creqv 6,6,6", operands);
12045 
 
12046 
#if TARGET_MACHO
12047 
  return output_call(insn, operands, 0, 2);
12048 
#else
12049 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
12050 
    {
12051 
      gcc_assert (!TARGET_SECURE_PLT);
12052 
      return "bl %z0@plt";
12053 
    }
12054 
  else
12055 
    return "bl %z0";
12056 
#endif
12057 
}
12058 
  "DEFAULT_ABI == ABI_V4
12059 
   && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12060 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
12061 
  [(parallel [(call (mem:SI (match_dup 0))
12062 
                    (match_dup 1))
12063 
              (use (match_dup 2))
12064 
              (use (match_dup 3))
12065 
              (clobber (reg:SI LR_REGNO))])]
12066 
{
12067 
  operands[3] = pic_offset_table_rtx;
12068 
}
12069 
  [(set_attr "type" "branch,branch")
12070 
   (set_attr "length" "4,8")])
12071 
 
12072 
(define_insn "*call_nonlocal_sysv_secure"
12073 
  [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12074 
         (match_operand 1 "" "g,g"))
12075 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
12076 
   (use (match_operand:SI 3 "register_operand" "r,r"))
12077 
   (clobber (reg:SI LR_REGNO))]
12078 
  "(DEFAULT_ABI == ABI_V4
12079 
    && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12080 
    && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12081 
{
12082 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12083 
    output_asm_insn ("crxor 6,6,6", operands);
12084 
 
12085 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12086 
    output_asm_insn ("creqv 6,6,6", operands);
12087 
 
12088 
  if (flag_pic == 2)
12089 
    /* The magic 32768 offset here and in the other sysv call insns
12090 
       corresponds to the offset of r30 in .got2, as given by LCTOC1.
12091 
       See sysv4.h:toc_section.  */
12092 
    return "bl %z0+32768@plt";
12093 
  else
12094 
    return "bl %z0@plt";
12095 
}
12096 
  [(set_attr "type" "branch,branch")
12097 
   (set_attr "length" "4,8")])
12098 
 
12099 
(define_insn "*call_value_indirect_nonlocal_sysv"
12100 
  [(set (match_operand 0 "" "")
12101 
        (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12102 
              (match_operand 2 "" "g,g,g,g")))
12103 
   (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12104 
   (clobber (reg:SI LR_REGNO))]
12105 
  "DEFAULT_ABI == ABI_V4
12106 
   || DEFAULT_ABI == ABI_DARWIN"
12107 
{
12108 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12109 
    output_asm_insn ("crxor 6,6,6", operands);
12110 
 
12111 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12112 
    output_asm_insn ("creqv 6,6,6", operands);
12113 
 
12114 
  return "b%T1l";
12115 
}
12116 
  [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12117 
   (set_attr "length" "4,4,8,8")])
12118 
 
12119 
(define_insn_and_split "*call_value_nonlocal_sysv"
12120 
  [(set (match_operand 0 "" "")
12121 
        (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12122 
              (match_operand 2 "" "g,g")))
12123 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
12124 
   (clobber (reg:SI LR_REGNO))]
12125 
  "(DEFAULT_ABI == ABI_DARWIN
12126 
   || (DEFAULT_ABI == ABI_V4
12127 
       && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12128 
{
12129 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12130 
    output_asm_insn ("crxor 6,6,6", operands);
12131 
 
12132 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12133 
    output_asm_insn ("creqv 6,6,6", operands);
12134 
 
12135 
#if TARGET_MACHO
12136 
  return output_call(insn, operands, 1, 3);
12137 
#else
12138 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
12139 
    {
12140 
      gcc_assert (!TARGET_SECURE_PLT);
12141 
      return "bl %z1@plt";
12142 
    }
12143 
  else
12144 
    return "bl %z1";
12145 
#endif
12146 
}
12147 
  "DEFAULT_ABI == ABI_V4
12148 
   && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12149 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
12150 
  [(parallel [(set (match_dup 0)
12151 
                   (call (mem:SI (match_dup 1))
12152 
                         (match_dup 2)))
12153 
              (use (match_dup 3))
12154 
              (use (match_dup 4))
12155 
              (clobber (reg:SI LR_REGNO))])]
12156 
{
12157 
  operands[4] = pic_offset_table_rtx;
12158 
}
12159 
  [(set_attr "type" "branch,branch")
12160 
   (set_attr "length" "4,8")])
12161 
 
12162 
(define_insn "*call_value_nonlocal_sysv_secure"
12163 
  [(set (match_operand 0 "" "")
12164 
        (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12165 
              (match_operand 2 "" "g,g")))
12166 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
12167 
   (use (match_operand:SI 4 "register_operand" "r,r"))
12168 
   (clobber (reg:SI LR_REGNO))]
12169 
  "(DEFAULT_ABI == ABI_V4
12170 
    && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12171 
    && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12172 
{
12173 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12174 
    output_asm_insn ("crxor 6,6,6", operands);
12175 
 
12176 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12177 
    output_asm_insn ("creqv 6,6,6", operands);
12178 
 
12179 
  if (flag_pic == 2)
12180 
    return "bl %z1+32768@plt";
12181 
  else
12182 
    return "bl %z1@plt";
12183 
}
12184 
  [(set_attr "type" "branch,branch")
12185 
   (set_attr "length" "4,8")])
12186 
 
12187 
;; Call subroutine returning any type.
12188 
(define_expand "untyped_call"
12189 
  [(parallel [(call (match_operand 0 "" "")
12190 
                    (const_int 0))
12191 
              (match_operand 1 "" "")
12192 
              (match_operand 2 "" "")])]
12193 
  ""
12194 
  "
12195 
{
12196 
  int i;
12197 
 
12198 
  emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12199 
 
12200 
  for (i = 0; i < XVECLEN (operands[2], 0); i++)
12201 
    {
12202 
      rtx set = XVECEXP (operands[2], 0, i);
12203 
      emit_move_insn (SET_DEST (set), SET_SRC (set));
12204 
    }
12205 
 
12206 
  /* The optimizer does not know that the call sets the function value
12207 
     registers we stored in the result block.  We avoid problems by
12208 
     claiming that all hard registers are used and clobbered at this
12209 
     point.  */
12210 
  emit_insn (gen_blockage ());
12211 
 
12212 
  DONE;
12213 
}")
12214 
 
12215 
;; sibling call patterns
12216 
(define_expand "sibcall"
12217 
  [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12218 
                    (match_operand 1 "" ""))
12219 
              (use (match_operand 2 "" ""))
12220 
              (use (reg:SI LR_REGNO))
12221 
              (return)])]
12222 
  ""
12223 
  "
12224 
{
12225 
#if TARGET_MACHO
12226 
  if (MACHOPIC_INDIRECT)
12227 
    operands[0] = machopic_indirect_call_target (operands[0]);
12228 
#endif
12229 
 
12230 
  gcc_assert (GET_CODE (operands[0]) == MEM);
12231 
  gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12232 
 
12233 
  operands[0] = XEXP (operands[0], 0);
12234 
}")
12235 
 
12236 
;; this and similar patterns must be marked as using LR, otherwise
12237 
;; dataflow will try to delete the store into it.  This is true
12238 
;; even when the actual reg to jump to is in CTR, when LR was
12239 
;; saved and restored around the PIC-setting BCL.
12240 
(define_insn "*sibcall_local32"
12241 
  [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12242 
         (match_operand 1 "" "g,g"))
12243 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
12244 
   (use (reg:SI LR_REGNO))
12245 
   (return)]
12246 
  "(INTVAL (operands[2]) & CALL_LONG) == 0"
12247 
  "*
12248 
{
12249 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12250 
    output_asm_insn (\"crxor 6,6,6\", operands);
12251 
 
12252 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12253 
    output_asm_insn (\"creqv 6,6,6\", operands);
12254 
 
12255 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12256 
}"
12257 
  [(set_attr "type" "branch")
12258 
   (set_attr "length" "4,8")])
12259 
 
12260 
(define_insn "*sibcall_local64"
12261 
  [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12262 
         (match_operand 1 "" "g,g"))
12263 
   (use (match_operand:SI 2 "immediate_operand" "O,n"))
12264 
   (use (reg:SI LR_REGNO))
12265 
   (return)]
12266 
  "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12267 
  "*
12268 
{
12269 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12270 
    output_asm_insn (\"crxor 6,6,6\", operands);
12271 
 
12272 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12273 
    output_asm_insn (\"creqv 6,6,6\", operands);
12274 
 
12275 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12276 
}"
12277 
  [(set_attr "type" "branch")
12278 
   (set_attr "length" "4,8")])
12279 
 
12280 
(define_insn "*sibcall_value_local32"
12281 
  [(set (match_operand 0 "" "")
12282 
        (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12283 
              (match_operand 2 "" "g,g")))
12284 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
12285 
   (use (reg:SI LR_REGNO))
12286 
   (return)]
12287 
  "(INTVAL (operands[3]) & CALL_LONG) == 0"
12288 
  "*
12289 
{
12290 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12291 
    output_asm_insn (\"crxor 6,6,6\", operands);
12292 
 
12293 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12294 
    output_asm_insn (\"creqv 6,6,6\", operands);
12295 
 
12296 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12297 
}"
12298 
  [(set_attr "type" "branch")
12299 
   (set_attr "length" "4,8")])
12300 
 
12301 
 
12302 
(define_insn "*sibcall_value_local64"
12303 
  [(set (match_operand 0 "" "")
12304 
        (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12305 
              (match_operand 2 "" "g,g")))
12306 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
12307 
   (use (reg:SI LR_REGNO))
12308 
   (return)]
12309 
  "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12310 
  "*
12311 
{
12312 
  if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12313 
    output_asm_insn (\"crxor 6,6,6\", operands);
12314 
 
12315 
  else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12316 
    output_asm_insn (\"creqv 6,6,6\", operands);
12317 
 
12318 
  return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12319 
}"
12320 
  [(set_attr "type" "branch")
12321 
   (set_attr "length" "4,8")])
12322 
 
12323 
(define_insn "*sibcall_nonlocal_aix32"
12324 
  [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12325 
         (match_operand 1 "" "g"))
12326 
   (use (match_operand:SI 2 "immediate_operand" "O"))
12327 
   (use (reg:SI LR_REGNO))
12328 
   (return)]
12329 
  "TARGET_32BIT
12330 
   && DEFAULT_ABI == ABI_AIX
12331 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
12332 
  "b %z0"
12333 
  [(set_attr "type" "branch")
12334 
   (set_attr "length" "4")])
12335 
 
12336 
(define_insn "*sibcall_nonlocal_aix64"
12337 
  [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12338 
         (match_operand 1 "" "g"))
12339 
   (use (match_operand:SI 2 "immediate_operand" "O"))
12340 
   (use (reg:SI LR_REGNO))
12341 
   (return)]
12342 
  "TARGET_64BIT
12343 
   && DEFAULT_ABI == ABI_AIX
12344 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
12345 
  "b %z0"
12346 
  [(set_attr "type" "branch")
12347 
   (set_attr "length" "4")])
12348 
 
12349 
(define_insn "*sibcall_value_nonlocal_aix32"
12350 
  [(set (match_operand 0 "" "")
12351 
        (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12352 
              (match_operand 2 "" "g")))
12353 
   (use (match_operand:SI 3 "immediate_operand" "O"))
12354 
   (use (reg:SI LR_REGNO))
12355 
   (return)]
12356 
  "TARGET_32BIT
12357 
   && DEFAULT_ABI == ABI_AIX
12358 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
12359 
  "b %z1"
12360 
  [(set_attr "type" "branch")
12361 
   (set_attr "length" "4")])
12362 
 
12363 
(define_insn "*sibcall_value_nonlocal_aix64"
12364 
  [(set (match_operand 0 "" "")
12365 
        (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12366 
              (match_operand 2 "" "g")))
12367 
   (use (match_operand:SI 3 "immediate_operand" "O"))
12368 
   (use (reg:SI LR_REGNO))
12369 
   (return)]
12370 
  "TARGET_64BIT
12371 
   && DEFAULT_ABI == ABI_AIX
12372 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
12373 
  "b %z1"
12374 
  [(set_attr "type" "branch")
12375 
   (set_attr "length" "4")])
12376 
 
12377 
(define_insn "*sibcall_nonlocal_sysv"
12378 
  [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12379 
         (match_operand 1 "" ""))
12380 
   (use (match_operand 2 "immediate_operand" "O,n"))
12381 
   (use (reg:SI LR_REGNO))
12382 
   (return)]
12383 
  "(DEFAULT_ABI == ABI_DARWIN
12384 
     || DEFAULT_ABI == ABI_V4)
12385 
   && (INTVAL (operands[2]) & CALL_LONG) == 0"
12386 
  "*
12387 
{
12388 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12389 
    output_asm_insn (\"crxor 6,6,6\", operands);
12390 
 
12391 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12392 
    output_asm_insn (\"creqv 6,6,6\", operands);
12393 
 
12394 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
12395 
    {
12396 
      gcc_assert (!TARGET_SECURE_PLT);
12397 
      return \"b %z0@plt\";
12398 
    }
12399 
  else
12400 
    return \"b %z0\";
12401 
}"
12402 
  [(set_attr "type" "branch,branch")
12403 
   (set_attr "length" "4,8")])
12404 
 
12405 
(define_expand "sibcall_value"
12406 
  [(parallel [(set (match_operand 0 "register_operand" "")
12407 
                (call (mem:SI (match_operand 1 "address_operand" ""))
12408 
                      (match_operand 2 "" "")))
12409 
              (use (match_operand 3 "" ""))
12410 
              (use (reg:SI LR_REGNO))
12411 
              (return)])]
12412 
  ""
12413 
  "
12414 
{
12415 
#if TARGET_MACHO
12416 
  if (MACHOPIC_INDIRECT)
12417 
    operands[1] = machopic_indirect_call_target (operands[1]);
12418 
#endif
12419 
 
12420 
  gcc_assert (GET_CODE (operands[1]) == MEM);
12421 
  gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12422 
 
12423 
  operands[1] = XEXP (operands[1], 0);
12424 
}")
12425 
 
12426 
(define_insn "*sibcall_value_nonlocal_sysv"
12427 
  [(set (match_operand 0 "" "")
12428 
        (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12429 
              (match_operand 2 "" "")))
12430 
   (use (match_operand:SI 3 "immediate_operand" "O,n"))
12431 
   (use (reg:SI LR_REGNO))
12432 
   (return)]
12433 
  "(DEFAULT_ABI == ABI_DARWIN
12434 
       || DEFAULT_ABI == ABI_V4)
12435 
   && (INTVAL (operands[3]) & CALL_LONG) == 0"
12436 
  "*
12437 
{
12438 
  if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12439 
    output_asm_insn (\"crxor 6,6,6\", operands);
12440 
 
12441 
  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12442 
    output_asm_insn (\"creqv 6,6,6\", operands);
12443 
 
12444 
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
12445 
    {
12446 
      gcc_assert (!TARGET_SECURE_PLT);
12447 
      return \"b %z1@plt\";
12448 
    }
12449 
  else
12450 
    return \"b %z1\";
12451 
}"
12452 
  [(set_attr "type" "branch,branch")
12453 
   (set_attr "length" "4,8")])
12454 
 
12455 
(define_expand "sibcall_epilogue"
12456 
  [(use (const_int 0))]
12457 
  "TARGET_SCHED_PROLOG"
12458 
  "
12459 
{
12460 
      rs6000_emit_epilogue (TRUE);
12461 
      DONE;
12462 
}")
12463 
 
12464 
;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12465 
;; all of memory.  This blocks insns from being moved across this point.
12466 
 
12467 
(define_insn "blockage"
12468 
  [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12469 
  ""
12470 
  "")
12471 
 
12472 
(define_insn "probe_stack"
12473 
  [(set (match_operand 0 "memory_operand" "=m")
12474 
        (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12475 
  ""
12476 
  "{st%U0%X0|stw%U0%X0} 0,%0"
12477 
  [(set_attr "type" "store")
12478 
   (set_attr "length" "4")])
12479 
 
12480 
;; Compare insns are next.  Note that the RS/6000 has two types of compares,
12481 
;; signed & unsigned, and one type of branch.
12482 
;;
12483 
;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12484 
;; insns, and branches.
12485 
 
12486 
(define_expand "cbranch4"
12487 
  [(use (match_operator 0 "rs6000_cbranch_operator"
12488 
         [(match_operand:GPR 1 "gpc_reg_operand" "")
12489 
          (match_operand:GPR 2 "reg_or_short_operand" "")]))
12490 
   (use (match_operand 3 ""))]
12491 
  ""
12492 
  "
12493 
{
12494 
  /* Take care of the possibility that operands[2] might be negative but
12495 
     this might be a logical operation.  That insn doesn't exist.  */
12496 
  if (GET_CODE (operands[2]) == CONST_INT
12497 
      && INTVAL (operands[2]) < 0)
12498 
    {
12499 
      operands[2] = force_reg (mode, operands[2]);
12500 
      operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12501 
                                    GET_MODE (operands[0]),
12502 
                                    operands[1], operands[2]);
12503 
   }
12504 
 
12505 
  rs6000_emit_cbranch (mode, operands);
12506 
  DONE;
12507 
}")
12508 
 
12509 
(define_expand "cbranch4"
12510 
  [(use (match_operator 0 "rs6000_cbranch_operator"
12511 
         [(match_operand:FP 1 "gpc_reg_operand" "")
12512 
          (match_operand:FP 2 "gpc_reg_operand" "")]))
12513 
   (use (match_operand 3 ""))]
12514 
  ""
12515 
  "
12516 
{
12517 
  rs6000_emit_cbranch (mode, operands);
12518 
  DONE;
12519 
}")
12520 
 
12521 
(define_expand "cstore4"
12522 
  [(use (match_operator 1 "rs6000_cbranch_operator"
12523 
         [(match_operand:GPR 2 "gpc_reg_operand" "")
12524 
          (match_operand:GPR 3 "reg_or_short_operand" "")]))
12525 
   (clobber (match_operand:SI 0 "register_operand"))]
12526 
  ""
12527 
  "
12528 
{
12529 
  /* Take care of the possibility that operands[3] might be negative but
12530 
     this might be a logical operation.  That insn doesn't exist.  */
12531 
  if (GET_CODE (operands[3]) == CONST_INT
12532 
      && INTVAL (operands[3]) < 0)
12533 
    {
12534 
      operands[3] = force_reg (mode, operands[3]);
12535 
      operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12536 
                                    GET_MODE (operands[1]),
12537 
                                    operands[2], operands[3]);
12538 
    }
12539 
 
12540 
  /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12541 
     For SEQ, likewise, except that comparisons with zero should be done
12542 
     with an scc insns.  However, due to the order that combine see the
12543 
     resulting insns, we must, in fact, allow SEQ for integers.  Fail in
12544 
     the cases we don't want to handle or are best handled by portable
12545 
     code.  */
12546 
  if (GET_CODE (operands[1]) == NE)
12547 
    FAIL;
12548 
  if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12549 
       || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12550 
      && operands[3] == const0_rtx)
12551 
    FAIL;
12552 
  rs6000_emit_sCOND (mode, operands);
12553 
  DONE;
12554 
}")
12555 
 
12556 
(define_expand "cstore4"
12557 
  [(use (match_operator 1 "rs6000_cbranch_operator"
12558 
         [(match_operand:FP 2 "gpc_reg_operand" "")
12559 
          (match_operand:FP 3 "gpc_reg_operand" "")]))
12560 
   (clobber (match_operand:SI 0 "register_operand"))]
12561 
  ""
12562 
  "
12563 
{
12564 
  rs6000_emit_sCOND (mode, operands);
12565 
  DONE;
12566 
}")
12567 
 
12568 
 
12569 
(define_expand "stack_protect_set"
12570 
  [(match_operand 0 "memory_operand" "")
12571 
   (match_operand 1 "memory_operand" "")]
12572 
  ""
12573 
{
12574 
#ifdef TARGET_THREAD_SSP_OFFSET
12575 
  rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12576 
  rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12577 
  operands[1] = gen_rtx_MEM (Pmode, addr);
12578 
#endif
12579 
  if (TARGET_64BIT)
12580 
    emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12581 
  else
12582 
    emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12583 
  DONE;
12584 
})
12585 
 
12586 
(define_insn "stack_protect_setsi"
12587 
  [(set (match_operand:SI 0 "memory_operand" "=m")
12588 
        (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12589 
   (set (match_scratch:SI 2 "=&r") (const_int 0))]
12590 
  "TARGET_32BIT"
12591 
  "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12592 
  [(set_attr "type" "three")
12593 
   (set_attr "length" "12")])
12594 
 
12595 
(define_insn "stack_protect_setdi"
12596 
  [(set (match_operand:DI 0 "memory_operand" "=m")
12597 
        (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12598 
   (set (match_scratch:DI 2 "=&r") (const_int 0))]
12599 
  "TARGET_64BIT"
12600 
  "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12601 
  [(set_attr "type" "three")
12602 
   (set_attr "length" "12")])
12603 
 
12604 
(define_expand "stack_protect_test"
12605 
  [(match_operand 0 "memory_operand" "")
12606 
   (match_operand 1 "memory_operand" "")
12607 
   (match_operand 2 "" "")]
12608 
  ""
12609 
{
12610 
  rtx test, op0, op1;
12611 
#ifdef TARGET_THREAD_SSP_OFFSET
12612 
  rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12613 
  rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12614 
  operands[1] = gen_rtx_MEM (Pmode, addr);
12615 
#endif
12616 
  op0 = operands[0];
12617 
  op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12618 
  test = gen_rtx_EQ (VOIDmode, op0, op1);
12619 
  emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12620 
  DONE;
12621 
})
12622 
 
12623 
(define_insn "stack_protect_testsi"
12624 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12625 
        (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12626 
                      (match_operand:SI 2 "memory_operand" "m,m")]
12627 
                     UNSPEC_SP_TEST))
12628 
   (set (match_scratch:SI 4 "=r,r") (const_int 0))
12629 
   (clobber (match_scratch:SI 3 "=&r,&r"))]
12630 
  "TARGET_32BIT"
12631 
  "@
12632 
   {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12633 
   {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12634 
  [(set_attr "length" "16,20")])
12635 
 
12636 
(define_insn "stack_protect_testdi"
12637 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12638 
        (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12639 
                      (match_operand:DI 2 "memory_operand" "m,m")]
12640 
                     UNSPEC_SP_TEST))
12641 
   (set (match_scratch:DI 4 "=r,r") (const_int 0))
12642 
   (clobber (match_scratch:DI 3 "=&r,&r"))]
12643 
  "TARGET_64BIT"
12644 
  "@
12645 
   ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12646 
   ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12647 
  [(set_attr "length" "16,20")])
12648 
 
12649 
 
12650 
;; Here are the actual compare insns.
12651 
(define_insn "*cmp_internal1"
12652 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12653 
        (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12654 
                    (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12655 
  ""
12656 
  "{cmp%I2|cmp%I2} %0,%1,%2"
12657 
  [(set_attr "type" "cmp")])
12658 
 
12659 
;; If we are comparing a register for equality with a large constant,
12660 
;; we can do this with an XOR followed by a compare.  But this is profitable
12661 
;; only if the large constant is only used for the comparison (and in this
12662 
;; case we already have a register to reuse as scratch).
12663 
;;
12664 
;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12665 
;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12666 
 
12667 
(define_peephole2
12668 
  [(set (match_operand:SI 0 "register_operand")
12669 
        (match_operand:SI 1 "logical_const_operand" ""))
12670 
   (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12671 
                       [(match_dup 0)
12672 
                        (match_operand:SI 2 "logical_const_operand" "")]))
12673 
   (set (match_operand:CC 4 "cc_reg_operand" "")
12674 
        (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12675 
                    (match_dup 0)))
12676 
   (set (pc)
12677 
        (if_then_else (match_operator 6 "equality_operator"
12678 
                       [(match_dup 4) (const_int 0)])
12679 
                      (match_operand 7 "" "")
12680 
                      (match_operand 8 "" "")))]
12681 
  "peep2_reg_dead_p (3, operands[0])
12682 
   && peep2_reg_dead_p (4, operands[4])"
12683 
 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12684 
  (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12685 
  (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12686 
 
12687 
{
12688 
  /* Get the constant we are comparing against, and see what it looks like
12689 
     when sign-extended from 16 to 32 bits.  Then see what constant we could
12690 
     XOR with SEXTC to get the sign-extended value.  */
12691 
  rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12692 
                                              SImode,
12693 
                                              operands[1], operands[2]);
12694 
  HOST_WIDE_INT c = INTVAL (cnst);
12695 
  HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12696 
  HOST_WIDE_INT xorv = c ^ sextc;
12697 
 
12698 
  operands[9] = GEN_INT (xorv);
12699 
  operands[10] = GEN_INT (sextc);
12700 
})
12701 
 
12702 
(define_insn "*cmpsi_internal2"
12703 
  [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12704 
        (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12705 
                       (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12706 
  ""
12707 
  "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12708 
  [(set_attr "type" "cmp")])
12709 
 
12710 
(define_insn "*cmpdi_internal2"
12711 
  [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12712 
        (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12713 
                       (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12714 
  ""
12715 
  "cmpld%I2 %0,%1,%b2"
12716 
  [(set_attr "type" "cmp")])
12717 
 
12718 
;; The following two insns don't exist as single insns, but if we provide
12719 
;; them, we can swap an add and compare, which will enable us to overlap more
12720 
;; of the required delay between a compare and branch.  We generate code for
12721 
;; them by splitting.
12722 
 
12723 
(define_insn ""
12724 
  [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12725 
        (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12726 
                    (match_operand:SI 2 "short_cint_operand" "i")))
12727 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12728 
        (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12729 
  ""
12730 
  "#"
12731 
  [(set_attr "length" "8")])
12732 
 
12733 
(define_insn ""
12734 
  [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12735 
        (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12736 
                       (match_operand:SI 2 "u_short_cint_operand" "i")))
12737 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12738 
        (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12739 
  ""
12740 
  "#"
12741 
  [(set_attr "length" "8")])
12742 
 
12743 
(define_split
12744 
  [(set (match_operand:CC 3 "cc_reg_operand" "")
12745 
        (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12746 
                    (match_operand:SI 2 "short_cint_operand" "")))
12747 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12748 
        (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12749 
  ""
12750 
  [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12751 
   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12752 
 
12753 
(define_split
12754 
  [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12755 
        (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12756 
                       (match_operand:SI 2 "u_short_cint_operand" "")))
12757 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
12758 
        (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12759 
  ""
12760 
  [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12761 
   (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12762 
 
12763 
(define_insn "*cmpsf_internal1"
12764 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12765 
        (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12766 
                      (match_operand:SF 2 "gpc_reg_operand" "f")))]
12767 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12768 
  "fcmpu %0,%1,%2"
12769 
  [(set_attr "type" "fpcompare")])
12770 
 
12771 
(define_insn "*cmpdf_internal1"
12772 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12773 
        (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12774 
                      (match_operand:DF 2 "gpc_reg_operand" "d")))]
12775 
  "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12776 
   && !VECTOR_UNIT_VSX_P (DFmode)"
12777 
  "fcmpu %0,%1,%2"
12778 
  [(set_attr "type" "fpcompare")])
12779 
 
12780 
;; Only need to compare second words if first words equal
12781 
(define_insn "*cmptf_internal1"
12782 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12783 
        (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12784 
                      (match_operand:TF 2 "gpc_reg_operand" "d")))]
12785 
  "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12786 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12787 
  "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12788 
  [(set_attr "type" "fpcompare")
12789 
   (set_attr "length" "12")])
12790 
 
12791 
(define_insn_and_split "*cmptf_internal2"
12792 
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12793 
        (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12794 
                      (match_operand:TF 2 "gpc_reg_operand" "d")))
12795 
    (clobber (match_scratch:DF 3 "=d"))
12796 
    (clobber (match_scratch:DF 4 "=d"))
12797 
    (clobber (match_scratch:DF 5 "=d"))
12798 
    (clobber (match_scratch:DF 6 "=d"))
12799 
    (clobber (match_scratch:DF 7 "=d"))
12800 
    (clobber (match_scratch:DF 8 "=d"))
12801 
    (clobber (match_scratch:DF 9 "=d"))
12802 
    (clobber (match_scratch:DF 10 "=d"))]
12803 
  "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12804 
   && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12805 
  "#"
12806 
  "&& reload_completed"
12807 
  [(set (match_dup 3) (match_dup 13))
12808 
   (set (match_dup 4) (match_dup 14))
12809 
   (set (match_dup 9) (abs:DF (match_dup 5)))
12810 
   (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12811 
   (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12812 
                           (label_ref (match_dup 11))
12813 
                           (pc)))
12814 
   (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12815 
   (set (pc) (label_ref (match_dup 12)))
12816 
   (match_dup 11)
12817 
   (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12818 
   (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12819 
   (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12820 
   (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12821 
   (match_dup 12)]
12822 
{
12823 
  REAL_VALUE_TYPE rv;
12824 
  const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12825 
  const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12826 
 
12827 
  operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12828 
  operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12829 
  operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12830 
  operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12831 
  operands[11] = gen_label_rtx ();
12832 
  operands[12] = gen_label_rtx ();
12833 
  real_inf (&rv);
12834 
  operands[13] = force_const_mem (DFmode,
12835 
                                  CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12836 
  operands[14] = force_const_mem (DFmode,
12837 
                                  CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12838 
                                                                DFmode));
12839 
  if (TARGET_TOC)
12840 
    {
12841 
      operands[13] = gen_const_mem (DFmode,
12842 
                                    create_TOC_reference (XEXP (operands[13], 0)));
12843 
      operands[14] = gen_const_mem (DFmode,
12844 
                                    create_TOC_reference (XEXP (operands[14], 0)));
12845 
      set_mem_alias_set (operands[13], get_TOC_alias_set ());
12846 
      set_mem_alias_set (operands[14], get_TOC_alias_set ());
12847 
    }
12848 
})
12849 
 
12850 
;; Now we have the scc insns.  We can do some combinations because of the
12851 
;; way the machine works.
12852 
;;
12853 
;; Note that this is probably faster if we can put an insn between the
12854 
;; mfcr and rlinm, but this is tricky.  Let's leave it for now.  In most
12855 
;; cases the insns below which don't use an intermediate CR field will
12856 
;; be used instead.
12857 
(define_insn ""
12858 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12859 
        (match_operator:SI 1 "scc_comparison_operator"
12860 
                           [(match_operand 2 "cc_reg_operand" "y")
12861 
                            (const_int 0)]))]
12862 
  ""
12863 
  "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12864 
  [(set (attr "type")
12865 
     (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12866 
                (const_string "mfcrf")
12867 
           ]
12868 
        (const_string "mfcr")))
12869 
   (set_attr "length" "8")])
12870 
 
12871 
;; Same as above, but get the GT bit.
12872 
(define_insn "move_from_CR_gt_bit"
12873 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12874 
        (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12875 
  "TARGET_HARD_FLOAT && !TARGET_FPRS"
12876 
  "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12877 
  [(set_attr "type" "mfcr")
12878 
   (set_attr "length" "8")])
12879 
 
12880 
;; Same as above, but get the OV/ORDERED bit.
12881 
(define_insn "move_from_CR_ov_bit"
12882 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12883 
        (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12884 
  "TARGET_ISEL"
12885 
  "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12886 
  [(set_attr "type" "mfcr")
12887 
   (set_attr "length" "8")])
12888 
 
12889 
(define_insn ""
12890 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12891 
        (match_operator:DI 1 "scc_comparison_operator"
12892 
                           [(match_operand 2 "cc_reg_operand" "y")
12893 
                            (const_int 0)]))]
12894 
  "TARGET_POWERPC64"
12895 
  "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12896 
  [(set (attr "type")
12897 
     (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12898 
                (const_string "mfcrf")
12899 
           ]
12900 
        (const_string "mfcr")))
12901 
   (set_attr "length" "8")])
12902 
 
12903 
(define_insn ""
12904 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12905 
        (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12906 
                                       [(match_operand 2 "cc_reg_operand" "y,y")
12907 
                                        (const_int 0)])
12908 
                    (const_int 0)))
12909 
   (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12910 
        (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12911 
  "TARGET_32BIT"
12912 
  "@
12913 
   mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12914 
   #"
12915 
  [(set_attr "type" "delayed_compare")
12916 
   (set_attr "length" "8,16")])
12917 
 
12918 
(define_split
12919 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12920 
        (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12921 
                                       [(match_operand 2 "cc_reg_operand" "")
12922 
                                        (const_int 0)])
12923 
                    (const_int 0)))
12924 
   (set (match_operand:SI 3 "gpc_reg_operand" "")
12925 
        (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12926 
  "TARGET_32BIT && reload_completed"
12927 
  [(set (match_dup 3)
12928 
        (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12929 
   (set (match_dup 0)
12930 
        (compare:CC (match_dup 3)
12931 
                    (const_int 0)))]
12932 
  "")
12933 
 
12934 
(define_insn ""
12935 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12936 
        (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12937 
                                      [(match_operand 2 "cc_reg_operand" "y")
12938 
                                       (const_int 0)])
12939 
                   (match_operand:SI 3 "const_int_operand" "n")))]
12940 
  ""
12941 
  "*
12942 
{
12943 
  int is_bit = ccr_bit (operands[1], 1);
12944 
  int put_bit = 31 - (INTVAL (operands[3]) & 31);
12945 
  int count;
12946 
 
12947 
  if (is_bit >= put_bit)
12948 
    count = is_bit - put_bit;
12949 
  else
12950 
    count = 32 - (put_bit - is_bit);
12951 
 
12952 
  operands[4] = GEN_INT (count);
12953 
  operands[5] = GEN_INT (put_bit);
12954 
 
12955 
  return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12956 
}"
12957 
  [(set (attr "type")
12958 
     (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12959 
                (const_string "mfcrf")
12960 
           ]
12961 
        (const_string "mfcr")))
12962 
   (set_attr "length" "8")])
12963 
 
12964 
(define_insn ""
12965 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12966 
        (compare:CC
12967 
         (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12968 
                                       [(match_operand 2 "cc_reg_operand" "y,y")
12969 
                                        (const_int 0)])
12970 
                    (match_operand:SI 3 "const_int_operand" "n,n"))
12971 
         (const_int 0)))
12972 
   (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12973 
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12974 
                   (match_dup 3)))]
12975 
  ""
12976 
  "*
12977 
{
12978 
  int is_bit = ccr_bit (operands[1], 1);
12979 
  int put_bit = 31 - (INTVAL (operands[3]) & 31);
12980 
  int count;
12981 
 
12982 
  /* Force split for non-cc0 compare.  */
12983 
  if (which_alternative == 1)
12984 
     return \"#\";
12985 
 
12986 
  if (is_bit >= put_bit)
12987 
    count = is_bit - put_bit;
12988 
  else
12989 
    count = 32 - (put_bit - is_bit);
12990 
 
12991 
  operands[5] = GEN_INT (count);
12992 
  operands[6] = GEN_INT (put_bit);
12993 
 
12994 
  return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12995 
}"
12996 
  [(set_attr "type" "delayed_compare")
12997 
   (set_attr "length" "8,16")])
12998 
 
12999 
(define_split
13000 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13001 
        (compare:CC
13002 
         (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13003 
                                       [(match_operand 2 "cc_reg_operand" "")
13004 
                                        (const_int 0)])
13005 
                    (match_operand:SI 3 "const_int_operand" ""))
13006 
         (const_int 0)))
13007 
   (set (match_operand:SI 4 "gpc_reg_operand" "")
13008 
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13009 
                   (match_dup 3)))]
13010 
  "reload_completed"
13011 
  [(set (match_dup 4)
13012 
        (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13013 
                   (match_dup 3)))
13014 
   (set (match_dup 0)
13015 
        (compare:CC (match_dup 4)
13016 
                    (const_int 0)))]
13017 
  "")
13018 
 
13019 
;; There is a 3 cycle delay between consecutive mfcr instructions
13020 
;; so it is useful to combine 2 scc instructions to use only one mfcr.
13021 
 
13022 
(define_peephole
13023 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13024 
        (match_operator:SI 1 "scc_comparison_operator"
13025 
                           [(match_operand 2 "cc_reg_operand" "y")
13026 
                            (const_int 0)]))
13027 
   (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13028 
        (match_operator:SI 4 "scc_comparison_operator"
13029 
                           [(match_operand 5 "cc_reg_operand" "y")
13030 
                            (const_int 0)]))]
13031 
  "REGNO (operands[2]) != REGNO (operands[5])"
13032 
  "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13033 
  [(set_attr "type" "mfcr")
13034 
   (set_attr "length" "12")])
13035 
 
13036 
(define_peephole
13037 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13038 
        (match_operator:DI 1 "scc_comparison_operator"
13039 
                           [(match_operand 2 "cc_reg_operand" "y")
13040 
                            (const_int 0)]))
13041 
   (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13042 
        (match_operator:DI 4 "scc_comparison_operator"
13043 
                           [(match_operand 5 "cc_reg_operand" "y")
13044 
                            (const_int 0)]))]
13045 
  "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13046 
  "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13047 
  [(set_attr "type" "mfcr")
13048 
   (set_attr "length" "12")])
13049 
 
13050 
;; There are some scc insns that can be done directly, without a compare.
13051 
;; These are faster because they don't involve the communications between
13052 
;; the FXU and branch units.   In fact, we will be replacing all of the
13053 
;; integer scc insns here or in the portable methods in emit_store_flag.
13054 
;;
13055 
;; Also support (neg (scc ..)) since that construct is used to replace
13056 
;; branches, (plus (scc ..) ..) since that construct is common and
13057 
;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13058 
;; cases where it is no more expensive than (neg (scc ..)).
13059 
 
13060 
;; Have reload force a constant into a register for the simple insns that
13061 
;; otherwise won't accept constants.  We do this because it is faster than
13062 
;; the cmp/mfcr sequence we would otherwise generate.
13063 
 
13064 
(define_mode_attr scc_eq_op2 [(SI "rKLI")
13065 
                              (DI "rKJI")])
13066 
 
13067 
(define_insn_and_split "*eq"
13068 
  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13069 
        (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13070 
                (match_operand:GPR 2 "scc_eq_operand" "")))]
13071 
  "!TARGET_POWER"
13072 
  "#"
13073 
  "!TARGET_POWER"
13074 
  [(set (match_dup 0)
13075 
        (clz:GPR (match_dup 3)))
13076 
   (set (match_dup 0)
13077 
        (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13078 
  {
13079 
    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13080 
      {
13081 
        /* Use output operand as intermediate.  */
13082 
        operands[3] = operands[0];
13083 
 
13084 
        if (logical_operand (operands[2], mode))
13085 
          emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13086 
                                  gen_rtx_XOR (mode,
13087 
                                               operands[1], operands[2])));
13088 
        else
13089 
          emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13090 
                                  gen_rtx_PLUS (mode, operands[1],
13091 
                                                negate_rtx (mode,
13092 
                                                            operands[2]))));
13093 
      }
13094 
    else
13095 
      operands[3] = operands[1];
13096 
 
13097 
    operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (mode)));
13098 
  })
13099 
 
13100 
(define_insn_and_split "*eq_compare"
13101 
  [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13102 
        (compare:CC
13103 
         (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13104 
               (match_operand:P 2 "scc_eq_operand" ""))
13105 
         (const_int 0)))
13106 
   (set (match_operand:P 0 "gpc_reg_operand" "=r")
13107 
        (eq:P (match_dup 1) (match_dup 2)))]
13108 
  "!TARGET_POWER && optimize_size"
13109 
  "#"
13110 
  "!TARGET_POWER && optimize_size"
13111 
  [(set (match_dup 0)
13112 
        (clz:P (match_dup 4)))
13113 
   (parallel [(set (match_dup 3)
13114 
                   (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13115 
                               (const_int 0)))
13116 
              (set (match_dup 0)
13117 
                   (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13118 
  {
13119 
    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13120 
      {
13121 
        /* Use output operand as intermediate.  */
13122 
        operands[4] = operands[0];
13123 
 
13124 
        if (logical_operand (operands[2], mode))
13125 
          emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13126 
                                  gen_rtx_XOR (mode,
13127 
                                               operands[1], operands[2])));
13128 
        else
13129 
          emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13130 
                                  gen_rtx_PLUS (mode, operands[1],
13131 
                                                negate_rtx (mode,
13132 
                                                            operands[2]))));
13133 
      }
13134 
    else
13135 
      operands[4] = operands[1];
13136 
 
13137 
    operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (mode)));
13138 
  })
13139 
 
13140 
(define_insn "*eqsi_power"
13141 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13142 
        (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13143 
               (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13144 
   (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13145 
  "TARGET_POWER"
13146 
  "@
13147 
   xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13148 
   {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13149 
   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13150 
   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13151 
   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13152 
  [(set_attr "type" "three,two,three,three,three")
13153 
   (set_attr "length" "12,8,12,12,12")])
13154 
 
13155 
;; We have insns of the form shown by the first define_insn below.  If
13156 
;; there is something inside the comparison operation, we must split it.
13157 
(define_split
13158 
  [(set (match_operand:SI 0 "gpc_reg_operand" "")
13159 
        (plus:SI (match_operator 1 "comparison_operator"
13160 
                                 [(match_operand:SI 2 "" "")
13161 
                                  (match_operand:SI 3
13162 
                                                    "reg_or_cint_operand" "")])
13163 
                 (match_operand:SI 4 "gpc_reg_operand" "")))
13164 
   (clobber (match_operand:SI 5 "register_operand" ""))]
13165 
  "! gpc_reg_operand (operands[2], SImode)"
13166 
  [(set (match_dup 5) (match_dup 2))
13167 
   (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13168 
                               (match_dup 4)))])
13169 
 
13170 
(define_insn "*plus_eqsi"
13171 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13172 
        (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13173 
                        (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13174 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13175 
  "TARGET_32BIT"
13176 
  "@
13177 
   xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13178 
   {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13179 
   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13180 
   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13181 
   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13182 
  [(set_attr "type" "three,two,three,three,three")
13183 
   (set_attr "length" "12,8,12,12,12")])
13184 
 
13185 
(define_insn "*compare_plus_eqsi"
13186 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13187 
        (compare:CC
13188 
         (plus:SI
13189 
          (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13190 
                 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13191 
          (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13192 
         (const_int 0)))
13193 
   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13194 
  "TARGET_32BIT && optimize_size"
13195 
  "@
13196 
   xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13197 
   {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13198 
   {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13199 
   {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13200 
   {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13201 
   #
13202 
   #
13203 
   #
13204 
   #
13205 
   #"
13206 
  [(set_attr "type" "compare")
13207 
   (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13208 
 
13209 
(define_split
13210 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13211 
        (compare:CC
13212 
         (plus:SI
13213 
          (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13214 
                 (match_operand:SI 2 "scc_eq_operand" ""))
13215 
          (match_operand:SI 3 "gpc_reg_operand" ""))
13216 
         (const_int 0)))
13217 
   (clobber (match_scratch:SI 4 ""))]
13218 
  "TARGET_32BIT && optimize_size && reload_completed"
13219 
  [(set (match_dup 4)
13220 
        (plus:SI (eq:SI (match_dup 1)
13221 
                 (match_dup 2))
13222 
          (match_dup 3)))
13223 
   (set (match_dup 0)
13224 
        (compare:CC (match_dup 4)
13225 
                    (const_int 0)))]
13226 
  "")
13227 
 
13228 
(define_insn "*plus_eqsi_compare"
13229 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13230 
        (compare:CC
13231 
         (plus:SI
13232 
          (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13233 
                 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13234 
          (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13235 
         (const_int 0)))
13236 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13237 
        (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13238 
  "TARGET_32BIT && optimize_size"
13239 
  "@
13240 
   xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13241 
   {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13242 
   {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13243 
   {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13244 
   {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13245 
   #
13246 
   #
13247 
   #
13248 
   #
13249 
   #"
13250 
  [(set_attr "type" "compare")
13251 
   (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13252 
 
13253 
(define_split
13254 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13255 
        (compare:CC
13256 
         (plus:SI
13257 
          (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13258 
                 (match_operand:SI 2 "scc_eq_operand" ""))
13259 
          (match_operand:SI 3 "gpc_reg_operand" ""))
13260 
         (const_int 0)))
13261 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13262 
        (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13263 
  "TARGET_32BIT && optimize_size && reload_completed"
13264 
  [(set (match_dup 0)
13265 
        (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13266 
   (set (match_dup 4)
13267 
        (compare:CC (match_dup 0)
13268 
                    (const_int 0)))]
13269 
  "")
13270 
 
13271 
(define_insn "*neg_eq0"
13272 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13273 
        (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13274 
                     (const_int 0))))]
13275 
  ""
13276 
  "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13277 
  [(set_attr "type" "two")
13278 
   (set_attr "length" "8")])
13279 
 
13280 
(define_insn_and_split "*neg_eq"
13281 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13282 
        (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13283 
                     (match_operand:P 2 "scc_eq_operand" ""))))]
13284 
  ""
13285 
  "#"
13286 
  ""
13287 
  [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13288 
  {
13289 
    if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13290 
      {
13291 
        /* Use output operand as intermediate.  */
13292 
        operands[3] = operands[0];
13293 
 
13294 
        if (logical_operand (operands[2], mode))
13295 
          emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13296 
                                  gen_rtx_XOR (mode,
13297 
                                               operands[1], operands[2])));
13298 
        else
13299 
          emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13300 
                                  gen_rtx_PLUS (mode, operands[1],
13301 
                                                negate_rtx (mode,
13302 
                                                            operands[2]))));
13303 
      }
13304 
    else
13305 
      operands[3] = operands[1];
13306 
  })
13307 
 
13308 
;; Simplify (ne X (const_int 0)) on the PowerPC.  No need to on the Power,
13309 
;; since it nabs/sr is just as fast.
13310 
(define_insn "*ne0si"
13311 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13312 
        (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13313 
                     (const_int 31)))
13314 
   (clobber (match_scratch:SI 2 "=&r"))]
13315 
  "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13316 
  "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13317 
  [(set_attr "type" "two")
13318 
   (set_attr "length" "8")])
13319 
 
13320 
(define_insn "*ne0di"
13321 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13322 
        (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13323 
                     (const_int 63)))
13324 
   (clobber (match_scratch:DI 2 "=&r"))]
13325 
  "TARGET_64BIT"
13326 
  "addic %2,%1,-1\;subfe %0,%2,%1"
13327 
  [(set_attr "type" "two")
13328 
   (set_attr "length" "8")])
13329 
 
13330 
;; This is what (plus (ne X (const_int 0)) Y) looks like.
13331 
(define_insn "*plus_ne0si"
13332 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13333 
        (plus:SI (lshiftrt:SI
13334 
                  (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13335 
                  (const_int 31))
13336 
                 (match_operand:SI 2 "gpc_reg_operand" "r")))
13337 
   (clobber (match_scratch:SI 3 "=&r"))]
13338 
  "TARGET_32BIT"
13339 
  "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13340 
  [(set_attr "type" "two")
13341 
   (set_attr "length" "8")])
13342 
 
13343 
(define_insn "*plus_ne0di"
13344 
  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13345 
        (plus:DI (lshiftrt:DI
13346 
                  (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13347 
                  (const_int 63))
13348 
                 (match_operand:DI 2 "gpc_reg_operand" "r")))
13349 
   (clobber (match_scratch:DI 3 "=&r"))]
13350 
  "TARGET_64BIT"
13351 
  "addic %3,%1,-1\;addze %0,%2"
13352 
  [(set_attr "type" "two")
13353 
   (set_attr "length" "8")])
13354 
 
13355 
(define_insn "*compare_plus_ne0si"
13356 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13357 
        (compare:CC
13358 
         (plus:SI (lshiftrt:SI
13359 
                   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13360 
                   (const_int 31))
13361 
                  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13362 
         (const_int 0)))
13363 
   (clobber (match_scratch:SI 3 "=&r,&r"))
13364 
   (clobber (match_scratch:SI 4 "=X,&r"))]
13365 
  "TARGET_32BIT"
13366 
  "@
13367 
   {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13368 
   #"
13369 
  [(set_attr "type" "compare")
13370 
   (set_attr "length" "8,12")])
13371 
 
13372 
(define_split
13373 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13374 
        (compare:CC
13375 
         (plus:SI (lshiftrt:SI
13376 
                   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13377 
                   (const_int 31))
13378 
                  (match_operand:SI 2 "gpc_reg_operand" ""))
13379 
         (const_int 0)))
13380 
   (clobber (match_scratch:SI 3 ""))
13381 
   (clobber (match_scratch:SI 4 ""))]
13382 
  "TARGET_32BIT && reload_completed"
13383 
  [(parallel [(set (match_dup 3)
13384 
                   (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13385 
                                         (const_int 31))
13386 
                            (match_dup 2)))
13387 
              (clobber (match_dup 4))])
13388 
   (set (match_dup 0)
13389 
        (compare:CC (match_dup 3)
13390 
                    (const_int 0)))]
13391 
  "")
13392 
 
13393 
(define_insn "*compare_plus_ne0di"
13394 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13395 
        (compare:CC
13396 
         (plus:DI (lshiftrt:DI
13397 
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13398 
                   (const_int 63))
13399 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13400 
         (const_int 0)))
13401 
   (clobber (match_scratch:DI 3 "=&r,&r"))]
13402 
  "TARGET_64BIT"
13403 
  "@
13404 
   addic %3,%1,-1\;addze. %3,%2
13405 
   #"
13406 
  [(set_attr "type" "compare")
13407 
   (set_attr "length" "8,12")])
13408 
 
13409 
(define_split
13410 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13411 
        (compare:CC
13412 
         (plus:DI (lshiftrt:DI
13413 
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13414 
                   (const_int 63))
13415 
                  (match_operand:DI 2 "gpc_reg_operand" ""))
13416 
         (const_int 0)))
13417 
   (clobber (match_scratch:DI 3 ""))]
13418 
  "TARGET_64BIT && reload_completed"
13419 
  [(set (match_dup 3)
13420 
        (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13421 
                   (const_int 63))
13422 
                  (match_dup 2)))
13423 
   (set (match_dup 0)
13424 
        (compare:CC (match_dup 3)
13425 
                    (const_int 0)))]
13426 
  "")
13427 
 
13428 
(define_insn "*plus_ne0si_compare"
13429 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13430 
        (compare:CC
13431 
         (plus:SI (lshiftrt:SI
13432 
                   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13433 
                   (const_int 31))
13434 
                  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13435 
         (const_int 0)))
13436 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13437 
        (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13438 
                 (match_dup 2)))
13439 
   (clobber (match_scratch:SI 3 "=&r,&r"))]
13440 
  "TARGET_32BIT"
13441 
  "@
13442 
   {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13443 
   #"
13444 
  [(set_attr "type" "compare")
13445 
   (set_attr "length" "8,12")])
13446 
 
13447 
(define_split
13448 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13449 
        (compare:CC
13450 
         (plus:SI (lshiftrt:SI
13451 
                   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13452 
                   (const_int 31))
13453 
                  (match_operand:SI 2 "gpc_reg_operand" ""))
13454 
         (const_int 0)))
13455 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13456 
        (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13457 
                 (match_dup 2)))
13458 
   (clobber (match_scratch:SI 3 ""))]
13459 
  "TARGET_32BIT && reload_completed"
13460 
  [(parallel [(set (match_dup 0)
13461 
        (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13462 
                 (match_dup 2)))
13463 
   (clobber (match_dup 3))])
13464 
   (set (match_dup 4)
13465 
        (compare:CC (match_dup 0)
13466 
                    (const_int 0)))]
13467 
  "")
13468 
 
13469 
(define_insn "*plus_ne0di_compare"
13470 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13471 
        (compare:CC
13472 
         (plus:DI (lshiftrt:DI
13473 
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13474 
                   (const_int 63))
13475 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13476 
         (const_int 0)))
13477 
   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13478 
        (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13479 
                 (match_dup 2)))
13480 
   (clobber (match_scratch:DI 3 "=&r,&r"))]
13481 
  "TARGET_64BIT"
13482 
  "@
13483 
   addic %3,%1,-1\;addze. %0,%2
13484 
   #"
13485 
  [(set_attr "type" "compare")
13486 
   (set_attr "length" "8,12")])
13487 
 
13488 
(define_split
13489 
  [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13490 
        (compare:CC
13491 
         (plus:DI (lshiftrt:DI
13492 
                   (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13493 
                   (const_int 63))
13494 
                  (match_operand:DI 2 "gpc_reg_operand" ""))
13495 
         (const_int 0)))
13496 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
13497 
        (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13498 
                 (match_dup 2)))
13499 
   (clobber (match_scratch:DI 3 ""))]
13500 
  "TARGET_64BIT && reload_completed"
13501 
  [(parallel [(set (match_dup 0)
13502 
        (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13503 
                 (match_dup 2)))
13504 
   (clobber (match_dup 3))])
13505 
   (set (match_dup 4)
13506 
        (compare:CC (match_dup 0)
13507 
                    (const_int 0)))]
13508 
  "")
13509 
 
13510 
(define_insn ""
13511 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13512 
        (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13513 
               (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13514 
   (clobber (match_scratch:SI 3 "=r,X"))]
13515 
  "TARGET_POWER"
13516 
  "@
13517 
   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13518 
   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13519 
  [(set_attr "length" "12")])
13520 
 
13521 
(define_insn ""
13522 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13523 
        (compare:CC
13524 
         (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13525 
                (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13526 
         (const_int 0)))
13527 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13528 
        (le:SI (match_dup 1) (match_dup 2)))
13529 
   (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13530 
  "TARGET_POWER"
13531 
  "@
13532 
   doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13533 
   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13534 
   #
13535 
   #"
13536 
  [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13537 
   (set_attr "length" "12,12,16,16")])
13538 
 
13539 
(define_split
13540 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13541 
        (compare:CC
13542 
         (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13543 
                (match_operand:SI 2 "reg_or_short_operand" ""))
13544 
         (const_int 0)))
13545 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13546 
        (le:SI (match_dup 1) (match_dup 2)))
13547 
   (clobber (match_scratch:SI 3 ""))]
13548 
  "TARGET_POWER && reload_completed"
13549 
  [(parallel [(set (match_dup 0)
13550 
        (le:SI (match_dup 1) (match_dup 2)))
13551 
   (clobber (match_dup 3))])
13552 
   (set (match_dup 4)
13553 
        (compare:CC (match_dup 0)
13554 
                    (const_int 0)))]
13555 
  "")
13556 
 
13557 
(define_insn ""
13558 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13559 
        (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13560 
                        (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13561 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13562 
  "TARGET_POWER"
13563 
  "@
13564 
   doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13565 
   {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13566 
  [(set_attr "length" "12")])
13567 
 
13568 
(define_insn ""
13569 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13570 
        (compare:CC
13571 
         (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13572 
                         (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13573 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13574 
         (const_int 0)))
13575 
   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13576 
  "TARGET_POWER"
13577 
  "@
13578 
   doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13579 
   {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13580 
   #
13581 
   #"
13582 
  [(set_attr "type" "compare")
13583 
   (set_attr "length" "12,12,16,16")])
13584 
 
13585 
(define_split
13586 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13587 
        (compare:CC
13588 
         (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13589 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
13590 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13591 
         (const_int 0)))
13592 
   (clobber (match_scratch:SI 4 ""))]
13593 
  "TARGET_POWER && reload_completed"
13594 
  [(set (match_dup 4)
13595 
        (plus:SI (le:SI (match_dup 1) (match_dup 2))
13596 
                 (match_dup 3)))
13597 
   (set (match_dup 0)
13598 
        (compare:CC (match_dup 4)
13599 
                    (const_int 0)))]
13600 
  "")
13601 
 
13602 
(define_insn ""
13603 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13604 
        (compare:CC
13605 
         (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13606 
                         (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13607 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13608 
         (const_int 0)))
13609 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13610 
        (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13611 
  "TARGET_POWER"
13612 
  "@
13613 
   doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13614 
   {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13615 
   #
13616 
   #"
13617 
  [(set_attr "type" "compare")
13618 
   (set_attr "length" "12,12,16,16")])
13619 
 
13620 
(define_split
13621 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13622 
        (compare:CC
13623 
         (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13624 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
13625 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13626 
         (const_int 0)))
13627 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13628 
        (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13629 
  "TARGET_POWER && reload_completed"
13630 
  [(set (match_dup 0)
13631 
        (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13632 
   (set (match_dup 4)
13633 
        (compare:CC (match_dup 0)
13634 
                    (const_int 0)))]
13635 
  "")
13636 
 
13637 
(define_insn ""
13638 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13639 
        (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13640 
                       (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13641 
  "TARGET_POWER"
13642 
  "@
13643 
   doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13644 
   {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13645 
  [(set_attr "length" "12")])
13646 
 
13647 
(define_insn "*leu"
13648 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13649 
        (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13650 
               (match_operand:P 2 "reg_or_short_operand" "rI")))]
13651 
  ""
13652 
  "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13653 
  [(set_attr "type" "three")
13654 
   (set_attr "length" "12")])
13655 
 
13656 
(define_insn "*leu_compare"
13657 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13658 
        (compare:CC
13659 
         (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13660 
                (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13661 
         (const_int 0)))
13662 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13663 
        (leu:P (match_dup 1) (match_dup 2)))]
13664 
  ""
13665 
  "@
13666 
   {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13667 
   #"
13668 
  [(set_attr "type" "compare")
13669 
   (set_attr "length" "12,16")])
13670 
 
13671 
(define_split
13672 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13673 
        (compare:CC
13674 
         (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13675 
                (match_operand:P 2 "reg_or_short_operand" ""))
13676 
         (const_int 0)))
13677 
   (set (match_operand:P 0 "gpc_reg_operand" "")
13678 
        (leu:P (match_dup 1) (match_dup 2)))]
13679 
  "reload_completed"
13680 
  [(set (match_dup 0)
13681 
        (leu:P (match_dup 1) (match_dup 2)))
13682 
   (set (match_dup 3)
13683 
        (compare:CC (match_dup 0)
13684 
                    (const_int 0)))]
13685 
  "")
13686 
 
13687 
(define_insn "*plus_leu"
13688 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13689 
        (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13690 
                       (match_operand:P 2 "reg_or_short_operand" "rI"))
13691 
                (match_operand:P 3 "gpc_reg_operand" "r")))]
13692 
  ""
13693 
  "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13694 
  [(set_attr "type" "two")
13695 
   (set_attr "length" "8")])
13696 
 
13697 
(define_insn ""
13698 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13699 
        (compare:CC
13700 
         (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13701 
                          (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13702 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13703 
         (const_int 0)))
13704 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
13705 
  "TARGET_32BIT"
13706 
  "@
13707 
   {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13708 
   #"
13709 
  [(set_attr "type" "compare")
13710 
   (set_attr "length" "8,12")])
13711 
 
13712 
(define_split
13713 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13714 
        (compare:CC
13715 
         (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13716 
                          (match_operand:SI 2 "reg_or_short_operand" ""))
13717 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13718 
         (const_int 0)))
13719 
   (clobber (match_scratch:SI 4 ""))]
13720 
  "TARGET_32BIT && reload_completed"
13721 
  [(set (match_dup 4)
13722 
        (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13723 
                  (match_dup 3)))
13724 
   (set (match_dup 0)
13725 
        (compare:CC (match_dup 4)
13726 
                    (const_int 0)))]
13727 
  "")
13728 
 
13729 
(define_insn ""
13730 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13731 
        (compare:CC
13732 
         (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13733 
                          (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13734 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13735 
         (const_int 0)))
13736 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13737 
        (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13738 
  "TARGET_32BIT"
13739 
  "@
13740 
   {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13741 
   #"
13742 
  [(set_attr "type" "compare")
13743 
   (set_attr "length" "8,12")])
13744 
 
13745 
(define_split
13746 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13747 
        (compare:CC
13748 
         (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13749 
                          (match_operand:SI 2 "reg_or_short_operand" ""))
13750 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13751 
         (const_int 0)))
13752 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13753 
        (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13754 
  "TARGET_32BIT && reload_completed"
13755 
  [(set (match_dup 0)
13756 
        (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13757 
   (set (match_dup 4)
13758 
        (compare:CC (match_dup 0)
13759 
                    (const_int 0)))]
13760 
  "")
13761 
 
13762 
(define_insn "*neg_leu"
13763 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13764 
        (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13765 
                      (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13766 
  ""
13767 
  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13768 
   [(set_attr "type" "three")
13769 
    (set_attr "length" "12")])
13770 
 
13771 
(define_insn "*and_neg_leu"
13772 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13773 
        (and:P (neg:P
13774 
                 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13775 
                        (match_operand:P 2 "reg_or_short_operand" "rI")))
13776 
                (match_operand:P 3 "gpc_reg_operand" "r")))]
13777 
  ""
13778 
  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13779 
  [(set_attr "type" "three")
13780 
   (set_attr "length" "12")])
13781 
 
13782 
(define_insn ""
13783 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13784 
        (compare:CC
13785 
         (and:SI (neg:SI
13786 
                  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13787 
                          (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13788 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13789 
         (const_int 0)))
13790 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
13791 
  "TARGET_32BIT"
13792 
  "@
13793 
   {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13794 
   #"
13795 
  [(set_attr "type" "compare")
13796 
   (set_attr "length" "12,16")])
13797 
 
13798 
(define_split
13799 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13800 
        (compare:CC
13801 
         (and:SI (neg:SI
13802 
                  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13803 
                          (match_operand:SI 2 "reg_or_short_operand" "")))
13804 
                 (match_operand:SI 3 "gpc_reg_operand" ""))
13805 
         (const_int 0)))
13806 
   (clobber (match_scratch:SI 4 ""))]
13807 
  "TARGET_32BIT && reload_completed"
13808 
  [(set (match_dup 4)
13809 
        (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13810 
                (match_dup 3)))
13811 
   (set (match_dup 0)
13812 
        (compare:CC (match_dup 4)
13813 
                    (const_int 0)))]
13814 
  "")
13815 
 
13816 
(define_insn ""
13817 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13818 
        (compare:CC
13819 
         (and:SI (neg:SI
13820 
                  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13821 
                          (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13822 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13823 
         (const_int 0)))
13824 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13825 
        (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13826 
  "TARGET_32BIT"
13827 
  "@
13828 
   {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13829 
   #"
13830 
  [(set_attr "type" "compare")
13831 
   (set_attr "length" "12,16")])
13832 
 
13833 
(define_split
13834 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13835 
        (compare:CC
13836 
         (and:SI (neg:SI
13837 
                  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13838 
                          (match_operand:SI 2 "reg_or_short_operand" "")))
13839 
                 (match_operand:SI 3 "gpc_reg_operand" ""))
13840 
         (const_int 0)))
13841 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13842 
        (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13843 
  "TARGET_32BIT && reload_completed"
13844 
  [(set (match_dup 0)
13845 
        (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13846 
                (match_dup 3)))
13847 
   (set (match_dup 4)
13848 
        (compare:CC (match_dup 0)
13849 
                    (const_int 0)))]
13850 
  "")
13851 
 
13852 
(define_insn ""
13853 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13854 
        (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13855 
               (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13856 
  "TARGET_POWER"
13857 
  "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13858 
   [(set_attr "length" "12")])
13859 
 
13860 
(define_insn ""
13861 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13862 
        (compare:CC
13863 
         (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13864 
                (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13865 
         (const_int 0)))
13866 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13867 
        (lt:SI (match_dup 1) (match_dup 2)))]
13868 
  "TARGET_POWER"
13869 
  "@
13870 
   doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13871 
   #"
13872 
  [(set_attr "type" "delayed_compare")
13873 
   (set_attr "length" "12,16")])
13874 
 
13875 
(define_split
13876 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13877 
        (compare:CC
13878 
         (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13879 
                (match_operand:SI 2 "reg_or_short_operand" ""))
13880 
         (const_int 0)))
13881 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13882 
        (lt:SI (match_dup 1) (match_dup 2)))]
13883 
  "TARGET_POWER && reload_completed"
13884 
  [(set (match_dup 0)
13885 
        (lt:SI (match_dup 1) (match_dup 2)))
13886 
   (set (match_dup 3)
13887 
        (compare:CC (match_dup 0)
13888 
                    (const_int 0)))]
13889 
  "")
13890 
 
13891 
(define_insn ""
13892 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13893 
        (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13894 
                        (match_operand:SI 2 "reg_or_short_operand" "rI"))
13895 
                 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13896 
  "TARGET_POWER"
13897 
  "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13898 
  [(set_attr "length" "12")])
13899 
 
13900 
(define_insn ""
13901 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13902 
        (compare:CC
13903 
         (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13904 
                         (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13905 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13906 
         (const_int 0)))
13907 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
13908 
  "TARGET_POWER"
13909 
  "@
13910 
   doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13911 
   #"
13912 
  [(set_attr "type" "compare")
13913 
   (set_attr "length" "12,16")])
13914 
 
13915 
(define_split
13916 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13917 
        (compare:CC
13918 
         (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13919 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
13920 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13921 
         (const_int 0)))
13922 
   (clobber (match_scratch:SI 4 ""))]
13923 
  "TARGET_POWER && reload_completed"
13924 
  [(set (match_dup 4)
13925 
        (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13926 
                 (match_dup 3)))
13927 
   (set (match_dup 0)
13928 
        (compare:CC (match_dup 4)
13929 
                    (const_int 0)))]
13930 
  "")
13931 
 
13932 
(define_insn ""
13933 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13934 
        (compare:CC
13935 
         (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13936 
                         (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13937 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13938 
         (const_int 0)))
13939 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13940 
        (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13941 
  "TARGET_POWER"
13942 
  "@
13943 
   doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13944 
   #"
13945 
  [(set_attr "type" "compare")
13946 
   (set_attr "length" "12,16")])
13947 
 
13948 
(define_split
13949 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13950 
        (compare:CC
13951 
         (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13952 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
13953 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
13954 
         (const_int 0)))
13955 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
13956 
        (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13957 
  "TARGET_POWER && reload_completed"
13958 
  [(set (match_dup 0)
13959 
        (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13960 
   (set (match_dup 4)
13961 
        (compare:CC (match_dup 0)
13962 
                    (const_int 0)))]
13963 
  "")
13964 
 
13965 
(define_insn ""
13966 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13967 
        (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13968 
                       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13969 
  "TARGET_POWER"
13970 
  "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13971 
  [(set_attr "length" "12")])
13972 
 
13973 
(define_insn_and_split "*ltu"
13974 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13975 
        (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13976 
               (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13977 
  ""
13978 
  "#"
13979 
  ""
13980 
  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13981 
   (set (match_dup 0) (neg:P (match_dup 0)))]
13982 
  "")
13983 
 
13984 
(define_insn_and_split "*ltu_compare"
13985 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13986 
        (compare:CC
13987 
         (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13988 
                (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13989 
         (const_int 0)))
13990 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13991 
        (ltu:P (match_dup 1) (match_dup 2)))]
13992 
  ""
13993 
  "#"
13994 
  ""
13995 
  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13996 
   (parallel [(set (match_dup 3)
13997 
                   (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13998 
              (set (match_dup 0) (neg:P (match_dup 0)))])]
13999 
  "")
14000 
 
14001 
(define_insn_and_split "*plus_ltu"
14002 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14003 
        (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14004 
                       (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14005 
                (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14006 
  ""
14007 
  "#"
14008 
  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14009 
  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14010 
   (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14011 
  "")
14012 
 
14013 
(define_insn_and_split "*plus_ltu_compare"
14014 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14015 
        (compare:CC
14016 
         (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14017 
                        (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14018 
                 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14019 
         (const_int 0)))
14020 
   (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14021 
        (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14022 
  ""
14023 
  "#"
14024 
  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14025 
  [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14026 
   (parallel [(set (match_dup 4)
14027 
                   (compare:CC (minus:P (match_dup 3) (match_dup 0))
14028 
                               (const_int 0)))
14029 
              (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14030 
  "")
14031 
 
14032 
(define_insn "*neg_ltu"
14033 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14034 
        (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14035 
                      (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14036 
  ""
14037 
  "@
14038 
   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14039 
   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14040 
  [(set_attr "type" "two")
14041 
   (set_attr "length" "8")])
14042 
 
14043 
(define_insn ""
14044 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14045 
        (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14046 
               (match_operand:SI 2 "reg_or_short_operand" "rI")))
14047 
   (clobber (match_scratch:SI 3 "=r"))]
14048 
  "TARGET_POWER"
14049 
  "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14050 
   [(set_attr "length" "12")])
14051 
 
14052 
(define_insn ""
14053 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14054 
        (compare:CC
14055 
         (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14056 
                (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14057 
         (const_int 0)))
14058 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14059 
        (ge:SI (match_dup 1) (match_dup 2)))
14060 
   (clobber (match_scratch:SI 3 "=r,r"))]
14061 
  "TARGET_POWER"
14062 
  "@
14063 
   doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14064 
   #"
14065 
  [(set_attr "type" "compare")
14066 
   (set_attr "length" "12,16")])
14067 
 
14068 
(define_split
14069 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14070 
        (compare:CC
14071 
         (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14072 
                (match_operand:SI 2 "reg_or_short_operand" ""))
14073 
         (const_int 0)))
14074 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
14075 
        (ge:SI (match_dup 1) (match_dup 2)))
14076 
   (clobber (match_scratch:SI 3 ""))]
14077 
  "TARGET_POWER && reload_completed"
14078 
  [(parallel [(set (match_dup 0)
14079 
                   (ge:SI (match_dup 1) (match_dup 2)))
14080 
              (clobber (match_dup 3))])
14081 
   (set (match_dup 4)
14082 
        (compare:CC (match_dup 0)
14083 
                    (const_int 0)))]
14084 
  "")
14085 
 
14086 
(define_insn ""
14087 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14088 
        (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14089 
                        (match_operand:SI 2 "reg_or_short_operand" "rI"))
14090 
                 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14091 
  "TARGET_POWER"
14092 
  "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14093 
  [(set_attr "length" "12")])
14094 
 
14095 
(define_insn ""
14096 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14097 
        (compare:CC
14098 
         (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14099 
                         (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14100 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14101 
         (const_int 0)))
14102 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
14103 
  "TARGET_POWER"
14104 
  "@
14105 
   doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14106 
   #"
14107 
  [(set_attr "type" "compare")
14108 
   (set_attr "length" "12,16")])
14109 
 
14110 
(define_split
14111 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14112 
        (compare:CC
14113 
         (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14114 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
14115 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
14116 
         (const_int 0)))
14117 
   (clobber (match_scratch:SI 4 ""))]
14118 
  "TARGET_POWER && reload_completed"
14119 
  [(set (match_dup 4)
14120 
        (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14121 
                 (match_dup 3)))
14122 
   (set (match_dup 0)
14123 
        (compare:CC (match_dup 4)
14124 
                    (const_int 0)))]
14125 
  "")
14126 
 
14127 
(define_insn ""
14128 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14129 
        (compare:CC
14130 
         (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14131 
                         (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14132 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14133 
         (const_int 0)))
14134 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14135 
        (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14136 
  "TARGET_POWER"
14137 
  "@
14138 
   doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14139 
   #"
14140 
  [(set_attr "type" "compare")
14141 
   (set_attr "length" "12,16")])
14142 
 
14143 
(define_split
14144 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14145 
        (compare:CC
14146 
         (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14147 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
14148 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
14149 
         (const_int 0)))
14150 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
14151 
        (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14152 
  "TARGET_POWER && reload_completed"
14153 
  [(set (match_dup 0)
14154 
        (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14155 
   (set (match_dup 4)
14156 
        (compare:CC (match_dup 0)
14157 
                    (const_int 0)))]
14158 
  "")
14159 
 
14160 
(define_insn ""
14161 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14162 
        (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14163 
                       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14164 
  "TARGET_POWER"
14165 
  "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14166 
  [(set_attr "length" "12")])
14167 
 
14168 
(define_insn "*geu"
14169 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14170 
        (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14171 
               (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14172 
  ""
14173 
  "@
14174 
   {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14175 
   {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14176 
  [(set_attr "type" "three")
14177 
   (set_attr "length" "12")])
14178 
 
14179 
(define_insn "*geu_compare"
14180 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14181 
        (compare:CC
14182 
         (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14183 
                (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14184 
         (const_int 0)))
14185 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14186 
        (geu:P (match_dup 1) (match_dup 2)))]
14187 
  ""
14188 
  "@
14189 
   {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14190 
   {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14191 
   #
14192 
   #"
14193 
  [(set_attr "type" "compare")
14194 
   (set_attr "length" "12,12,16,16")])
14195 
 
14196 
(define_split
14197 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14198 
        (compare:CC
14199 
         (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14200 
                (match_operand:P 2 "reg_or_neg_short_operand" ""))
14201 
         (const_int 0)))
14202 
   (set (match_operand:P 0 "gpc_reg_operand" "")
14203 
        (geu:P (match_dup 1) (match_dup 2)))]
14204 
  "reload_completed"
14205 
  [(set (match_dup 0)
14206 
        (geu:P (match_dup 1) (match_dup 2)))
14207 
   (set (match_dup 3)
14208 
        (compare:CC (match_dup 0)
14209 
                    (const_int 0)))]
14210 
  "")
14211 
 
14212 
(define_insn "*plus_geu"
14213 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14214 
        (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14215 
                       (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14216 
                (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14217 
  ""
14218 
  "@
14219 
   {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14220 
   {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14221 
  [(set_attr "type" "two")
14222 
   (set_attr "length" "8")])
14223 
 
14224 
(define_insn ""
14225 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14226 
        (compare:CC
14227 
         (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14228 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14229 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14230 
         (const_int 0)))
14231 
   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14232 
  "TARGET_32BIT"
14233 
  "@
14234 
   {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14235 
   {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14236 
   #
14237 
   #"
14238 
  [(set_attr "type" "compare")
14239 
   (set_attr "length" "8,8,12,12")])
14240 
 
14241 
(define_split
14242 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14243 
        (compare:CC
14244 
         (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14245 
                          (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14246 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
14247 
         (const_int 0)))
14248 
   (clobber (match_scratch:SI 4 ""))]
14249 
  "TARGET_32BIT && reload_completed"
14250 
  [(set (match_dup 4)
14251 
        (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14252 
                  (match_dup 3)))
14253 
   (set (match_dup 0)
14254 
        (compare:CC (match_dup 4)
14255 
                    (const_int 0)))]
14256 
  "")
14257 
 
14258 
(define_insn ""
14259 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14260 
        (compare:CC
14261 
         (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14262 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14263 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14264 
         (const_int 0)))
14265 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14266 
        (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14267 
  "TARGET_32BIT"
14268 
  "@
14269 
   {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14270 
   {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14271 
   #
14272 
   #"
14273 
  [(set_attr "type" "compare")
14274 
   (set_attr "length" "8,8,12,12")])
14275 
 
14276 
(define_split
14277 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14278 
        (compare:CC
14279 
         (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14280 
                          (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14281 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
14282 
         (const_int 0)))
14283 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
14284 
        (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14285 
  "TARGET_32BIT && reload_completed"
14286 
  [(set (match_dup 0)
14287 
        (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14288 
   (set (match_dup 4)
14289 
        (compare:CC (match_dup 0)
14290 
                    (const_int 0)))]
14291 
  "")
14292 
 
14293 
(define_insn "*neg_geu"
14294 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14295 
        (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14296 
                      (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14297 
  ""
14298 
  "@
14299 
   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14300 
   {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14301 
  [(set_attr "type" "three")
14302 
   (set_attr "length" "12")])
14303 
 
14304 
(define_insn "*and_neg_geu"
14305 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14306 
        (and:P (neg:P
14307 
                 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14308 
                        (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14309 
                (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14310 
  ""
14311 
  "@
14312 
   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14313 
   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14314 
  [(set_attr "type" "three")
14315 
   (set_attr "length" "12")])
14316 
 
14317 
(define_insn ""
14318 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14319 
        (compare:CC
14320 
         (and:SI (neg:SI
14321 
                  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14322 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14323 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14324 
         (const_int 0)))
14325 
   (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14326 
  "TARGET_32BIT"
14327 
  "@
14328 
   {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14329 
   {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14330 
   #
14331 
   #"
14332 
  [(set_attr "type" "compare")
14333 
   (set_attr "length" "12,12,16,16")])
14334 
 
14335 
(define_split
14336 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14337 
        (compare:CC
14338 
         (and:SI (neg:SI
14339 
                  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14340 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14341 
                 (match_operand:SI 3 "gpc_reg_operand" ""))
14342 
         (const_int 0)))
14343 
   (clobber (match_scratch:SI 4 ""))]
14344 
  "TARGET_32BIT && reload_completed"
14345 
  [(set (match_dup 4)
14346 
        (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14347 
                (match_dup 3)))
14348 
   (set (match_dup 0)
14349 
        (compare:CC (match_dup 4)
14350 
                    (const_int 0)))]
14351 
  "")
14352 
 
14353 
(define_insn ""
14354 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14355 
        (compare:CC
14356 
         (and:SI (neg:SI
14357 
                  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14358 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14359 
                 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14360 
         (const_int 0)))
14361 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14362 
        (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14363 
  "TARGET_32BIT"
14364 
  "@
14365 
   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14366 
   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14367 
   #
14368 
   #"
14369 
  [(set_attr "type" "compare")
14370 
   (set_attr "length" "12,12,16,16")])
14371 
 
14372 
(define_split
14373 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14374 
        (compare:CC
14375 
         (and:SI (neg:SI
14376 
                  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14377 
                          (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14378 
                 (match_operand:SI 3 "gpc_reg_operand" ""))
14379 
         (const_int 0)))
14380 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
14381 
        (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14382 
  "TARGET_32BIT && reload_completed"
14383 
  [(set (match_dup 0)
14384 
        (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14385 
   (set (match_dup 4)
14386 
        (compare:CC (match_dup 0)
14387 
                    (const_int 0)))]
14388 
  "")
14389 
 
14390 
(define_insn ""
14391 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14392 
        (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14393 
               (match_operand:SI 2 "reg_or_short_operand" "r")))]
14394 
  "TARGET_POWER"
14395 
  "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14396 
  [(set_attr "length" "12")])
14397 
 
14398 
(define_insn ""
14399 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14400 
        (compare:CC
14401 
         (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14402 
                (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14403 
         (const_int 0)))
14404 
   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14405 
        (gt:SI (match_dup 1) (match_dup 2)))]
14406 
  "TARGET_POWER"
14407 
  "@
14408 
   doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14409 
   #"
14410 
  [(set_attr "type" "delayed_compare")
14411 
   (set_attr "length" "12,16")])
14412 
 
14413 
(define_split
14414 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14415 
        (compare:CC
14416 
         (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14417 
                (match_operand:SI 2 "reg_or_short_operand" ""))
14418 
         (const_int 0)))
14419 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
14420 
        (gt:SI (match_dup 1) (match_dup 2)))]
14421 
  "TARGET_POWER && reload_completed"
14422 
  [(set (match_dup 0)
14423 
        (gt:SI (match_dup 1) (match_dup 2)))
14424 
   (set (match_dup 3)
14425 
        (compare:CC (match_dup 0)
14426 
                    (const_int 0)))]
14427 
  "")
14428 
 
14429 
(define_insn "*plus_gt0"
14430 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14431 
        (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14432 
                      (const_int 0))
14433 
                 (match_operand:P 2 "gpc_reg_operand" "r")))]
14434 
  ""
14435 
  "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14436 
  [(set_attr "type" "three")
14437 
   (set_attr "length" "12")])
14438 
 
14439 
(define_insn ""
14440 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14441 
        (compare:CC
14442 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14443 
                         (const_int 0))
14444 
                  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14445 
         (const_int 0)))
14446 
   (clobber (match_scratch:SI 3 "=&r,&r"))]
14447 
  "TARGET_32BIT"
14448 
  "@
14449 
   {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14450 
   #"
14451 
  [(set_attr "type" "compare")
14452 
   (set_attr "length" "12,16")])
14453 
 
14454 
(define_split
14455 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14456 
        (compare:CC
14457 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14458 
                         (const_int 0))
14459 
                  (match_operand:SI 2 "gpc_reg_operand" ""))
14460 
         (const_int 0)))
14461 
   (clobber (match_scratch:SI 3 ""))]
14462 
  "TARGET_32BIT && reload_completed"
14463 
  [(set (match_dup 3)
14464 
        (plus:SI (gt:SI (match_dup 1) (const_int 0))
14465 
                  (match_dup 2)))
14466 
   (set (match_dup 0)
14467 
        (compare:CC (match_dup 3)
14468 
                    (const_int 0)))]
14469 
  "")
14470 
 
14471 
(define_insn ""
14472 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14473 
        (compare:CC
14474 
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14475 
                         (const_int 0))
14476 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14477 
         (const_int 0)))
14478 
   (clobber (match_scratch:DI 3 "=&r,&r"))]
14479 
  "TARGET_64BIT"
14480 
  "@
14481 
   addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14482 
   #"
14483 
  [(set_attr "type" "compare")
14484 
   (set_attr "length" "12,16")])
14485 
 
14486 
(define_split
14487 
  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14488 
        (compare:CC
14489 
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14490 
                         (const_int 0))
14491 
                  (match_operand:DI 2 "gpc_reg_operand" ""))
14492 
         (const_int 0)))
14493 
   (clobber (match_scratch:DI 3 ""))]
14494 
  "TARGET_64BIT && reload_completed"
14495 
  [(set (match_dup 3)
14496 
        (plus:DI (gt:DI (match_dup 1) (const_int 0))
14497 
                 (match_dup 2)))
14498 
   (set (match_dup 0)
14499 
        (compare:CC (match_dup 3)
14500 
                    (const_int 0)))]
14501 
  "")
14502 
 
14503 
(define_insn ""
14504 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14505 
        (compare:CC
14506 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14507 
                         (const_int 0))
14508 
                  (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14509 
         (const_int 0)))
14510 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14511 
        (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14512 
  "TARGET_32BIT"
14513 
  "@
14514 
   {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14515 
   #"
14516 
  [(set_attr "type" "compare")
14517 
   (set_attr "length" "12,16")])
14518 
 
14519 
(define_split
14520 
  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14521 
        (compare:CC
14522 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14523 
                         (const_int 0))
14524 
                  (match_operand:SI 2 "gpc_reg_operand" ""))
14525 
         (const_int 0)))
14526 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
14527 
        (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14528 
  "TARGET_32BIT && reload_completed"
14529 
  [(set (match_dup 0)
14530 
        (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14531 
   (set (match_dup 3)
14532 
        (compare:CC (match_dup 0)
14533 
                    (const_int 0)))]
14534 
  "")
14535 
 
14536 
(define_insn ""
14537 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14538 
        (compare:CC
14539 
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14540 
                         (const_int 0))
14541 
                  (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14542 
         (const_int 0)))
14543 
   (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14544 
        (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14545 
  "TARGET_64BIT"
14546 
  "@
14547 
   addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14548 
   #"
14549 
  [(set_attr "type" "compare")
14550 
   (set_attr "length" "12,16")])
14551 
 
14552 
(define_split
14553 
  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14554 
        (compare:CC
14555 
         (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14556 
                         (const_int 0))
14557 
                  (match_operand:DI 2 "gpc_reg_operand" ""))
14558 
         (const_int 0)))
14559 
   (set (match_operand:DI 0 "gpc_reg_operand" "")
14560 
        (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14561 
  "TARGET_64BIT && reload_completed"
14562 
  [(set (match_dup 0)
14563 
        (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14564 
   (set (match_dup 3)
14565 
        (compare:CC (match_dup 0)
14566 
                    (const_int 0)))]
14567 
  "")
14568 
 
14569 
(define_insn ""
14570 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14571 
        (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14572 
                        (match_operand:SI 2 "reg_or_short_operand" "r"))
14573 
                 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14574 
  "TARGET_POWER"
14575 
  "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14576 
  [(set_attr "length" "12")])
14577 
 
14578 
(define_insn ""
14579 
  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14580 
        (compare:CC
14581 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14582 
                         (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14583 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14584 
         (const_int 0)))
14585 
   (clobber (match_scratch:SI 4 "=&r,&r"))]
14586 
  "TARGET_POWER"
14587 
  "@
14588 
   doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14589 
   #"
14590 
  [(set_attr "type" "compare")
14591 
   (set_attr "length" "12,16")])
14592 
 
14593 
(define_split
14594 
  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14595 
        (compare:CC
14596 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14597 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
14598 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
14599 
         (const_int 0)))
14600 
   (clobber (match_scratch:SI 4 ""))]
14601 
  "TARGET_POWER && reload_completed"
14602 
  [(set (match_dup 4)
14603 
        (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14604 
   (set (match_dup 0)
14605 
        (compare:CC (match_dup 4)
14606 
                    (const_int 0)))]
14607 
  "")
14608 
 
14609 
(define_insn ""
14610 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14611 
        (compare:CC
14612 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14613 
                         (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14614 
                  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14615 
         (const_int 0)))
14616 
   (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14617 
        (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14618 
  "TARGET_POWER"
14619 
  "@
14620 
   doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14621 
   #"
14622 
  [(set_attr "type" "compare")
14623 
   (set_attr "length" "12,16")])
14624 
 
14625 
(define_split
14626 
  [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14627 
        (compare:CC
14628 
         (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14629 
                         (match_operand:SI 2 "reg_or_short_operand" ""))
14630 
                  (match_operand:SI 3 "gpc_reg_operand" ""))
14631 
         (const_int 0)))
14632 
   (set (match_operand:SI 0 "gpc_reg_operand" "")
14633 
        (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14634 
  "TARGET_POWER && reload_completed"
14635 
  [(set (match_dup 0)
14636 
        (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14637 
   (set (match_dup 4)
14638 
        (compare:CC (match_dup 0)
14639 
                    (const_int 0)))]
14640 
  "")
14641 
 
14642 
(define_insn ""
14643 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14644 
        (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14645 
                       (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14646 
  "TARGET_POWER"
14647 
  "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14648 
  [(set_attr "length" "12")])
14649 
 
14650 
(define_insn_and_split "*gtu"
14651 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14652 
        (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14653 
               (match_operand:P 2 "reg_or_short_operand" "rI")))]
14654 
  ""
14655 
  "#"
14656 
  ""
14657 
  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14658 
   (set (match_dup 0) (neg:P (match_dup 0)))]
14659 
  "")
14660 
 
14661 
(define_insn_and_split "*gtu_compare"
14662 
  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14663 
        (compare:CC
14664 
         (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14665 
                 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14666 
         (const_int 0)))
14667 
   (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14668 
        (gtu:P (match_dup 1) (match_dup 2)))]
14669 
  ""
14670 
  "#"
14671 
  ""
14672 
  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14673 
   (parallel [(set (match_dup 3)
14674 
                   (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14675 
              (set (match_dup 0) (neg:P (match_dup 0)))])]
14676 
  "")
14677 
 
14678 
(define_insn_and_split "*plus_gtu"
14679 
  [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14680 
        (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14681 
                       (match_operand:P 2 "reg_or_short_operand" "rI"))
14682 
                (match_operand:P 3 "reg_or_short_operand" "rI")))]
14683 
  ""
14684 
  "#"
14685 
  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14686 
  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14687 
   (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14688 
  "")
14689 
 
14690 
(define_insn_and_split "*plus_gtu_compare"
14691 
  [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14692 
        (compare:CC
14693 
         (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14694 
                        (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14695 
                 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14696 
         (const_int 0)))
14697 
   (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14698 
        (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14699 
  ""
14700 
  "#"
14701 
  "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14702 
  [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14703 
   (parallel [(set (match_dup 4)
14704 
                   (compare:CC (minus:P (match_dup 3) (match_dup 0))
14705 
                               (const_int 0)))
14706 
              (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14707 
  "")
14708 
 
14709 
(define_insn "*neg_gtu"
14710 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14711 
        (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14712 
                      (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14713 
  ""
14714 
  "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14715 
  [(set_attr "type" "two")
14716 
   (set_attr "length" "8")])
14717 
 
14718 
 
14719 
;; Define both directions of branch and return.  If we need a reload
14720 
;; register, we'd rather use CR0 since it is much easier to copy a
14721 
;; register CC value to there.
14722 
 
14723 
(define_insn ""
14724 
  [(set (pc)
14725 
        (if_then_else (match_operator 1 "branch_comparison_operator"
14726 
                                      [(match_operand 2
14727 
                                                      "cc_reg_operand" "y")
14728 
                                       (const_int 0)])
14729 
                      (label_ref (match_operand 0 "" ""))
14730 
                      (pc)))]
14731 
  ""
14732 
  "*
14733 
{
14734 
  return output_cbranch (operands[1], \"%l0\", 0, insn);
14735 
}"
14736 
  [(set_attr "type" "branch")])
14737 
 
14738 
(define_insn ""
14739 
  [(set (pc)
14740 
        (if_then_else (match_operator 0 "branch_comparison_operator"
14741 
                                      [(match_operand 1
14742 
                                                      "cc_reg_operand" "y")
14743 
                                       (const_int 0)])
14744 
                      (return)
14745 
                      (pc)))]
14746 
  "direct_return ()"
14747 
  "*
14748 
{
14749 
  return output_cbranch (operands[0], NULL, 0, insn);
14750 
}"
14751 
  [(set_attr "type" "jmpreg")
14752 
   (set_attr "length" "4")])
14753 
 
14754 
(define_insn ""
14755 
  [(set (pc)
14756 
        (if_then_else (match_operator 1 "branch_comparison_operator"
14757 
                                      [(match_operand 2
14758 
                                                      "cc_reg_operand" "y")
14759 
                                       (const_int 0)])
14760 
                      (pc)
14761 
                      (label_ref (match_operand 0 "" ""))))]
14762 
  ""
14763 
  "*
14764 
{
14765 
  return output_cbranch (operands[1], \"%l0\", 1, insn);
14766 
}"
14767 
  [(set_attr "type" "branch")])
14768 
 
14769 
(define_insn ""
14770 
  [(set (pc)
14771 
        (if_then_else (match_operator 0 "branch_comparison_operator"
14772 
                                      [(match_operand 1
14773 
                                                      "cc_reg_operand" "y")
14774 
                                       (const_int 0)])
14775 
                      (pc)
14776 
                      (return)))]
14777 
  "direct_return ()"
14778 
  "*
14779 
{
14780 
  return output_cbranch (operands[0], NULL, 1, insn);
14781 
}"
14782 
  [(set_attr "type" "jmpreg")
14783 
   (set_attr "length" "4")])
14784 
 
14785 
;; Logic on condition register values.
14786 
 
14787 
; This pattern matches things like
14788 
; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14789 
;                                          (eq:SI (reg:CCFP 68) (const_int 0)))
14790 
;                                  (const_int 1)))
14791 
; which are generated by the branch logic.
14792 
; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14793 
 
14794 
(define_insn "*cceq_ior_compare"
14795 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14796 
        (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14797 
                        [(match_operator:SI 2
14798 
                                      "branch_positive_comparison_operator"
14799 
                                      [(match_operand 3
14800 
                                                      "cc_reg_operand" "y,y")
14801 
                                       (const_int 0)])
14802 
                         (match_operator:SI 4
14803 
                                      "branch_positive_comparison_operator"
14804 
                                      [(match_operand 5
14805 
                                                      "cc_reg_operand" "0,y")
14806 
                                       (const_int 0)])])
14807 
                      (const_int 1)))]
14808 
  ""
14809 
  "cr%q1 %E0,%j2,%j4"
14810 
  [(set_attr "type" "cr_logical,delayed_cr")])
14811 
 
14812 
; Why is the constant -1 here, but 1 in the previous pattern?
14813 
; Because ~1 has all but the low bit set.
14814 
(define_insn ""
14815 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14816 
        (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14817 
                        [(not:SI (match_operator:SI 2
14818 
                                      "branch_positive_comparison_operator"
14819 
                                      [(match_operand 3
14820 
                                                      "cc_reg_operand" "y,y")
14821 
                                       (const_int 0)]))
14822 
                         (match_operator:SI 4
14823 
                                "branch_positive_comparison_operator"
14824 
                                [(match_operand 5
14825 
                                                "cc_reg_operand" "0,y")
14826 
                                 (const_int 0)])])
14827 
                      (const_int -1)))]
14828 
  ""
14829 
  "cr%q1 %E0,%j2,%j4"
14830 
  [(set_attr "type" "cr_logical,delayed_cr")])
14831 
 
14832 
(define_insn "*cceq_rev_compare"
14833 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14834 
        (compare:CCEQ (match_operator:SI 1
14835 
                                      "branch_positive_comparison_operator"
14836 
                                      [(match_operand 2
14837 
                                                      "cc_reg_operand" "0,y")
14838 
                                       (const_int 0)])
14839 
                      (const_int 0)))]
14840 
  ""
14841 
  "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14842 
  [(set_attr "type" "cr_logical,delayed_cr")])
14843 
 
14844 
;; If we are comparing the result of two comparisons, this can be done
14845 
;; using creqv or crxor.
14846 
 
14847 
(define_insn_and_split ""
14848 
  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14849 
        (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14850 
                              [(match_operand 2 "cc_reg_operand" "y")
14851 
                               (const_int 0)])
14852 
                      (match_operator 3 "branch_comparison_operator"
14853 
                              [(match_operand 4 "cc_reg_operand" "y")
14854 
                               (const_int 0)])))]
14855 
  ""
14856 
  "#"
14857 
  ""
14858 
  [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14859 
                                    (match_dup 5)))]
14860 
  "
14861 
{
14862 
  int positive_1, positive_2;
14863 
 
14864 
  positive_1 = branch_positive_comparison_operator (operands[1],
14865 
                                                    GET_MODE (operands[1]));
14866 
  positive_2 = branch_positive_comparison_operator (operands[3],
14867 
                                                    GET_MODE (operands[3]));
14868 
 
14869 
  if (! positive_1)
14870 
    operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14871 
                                                            GET_CODE (operands[1])),
14872 
                                  SImode,
14873 
                                  operands[2], const0_rtx);
14874 
  else if (GET_MODE (operands[1]) != SImode)
14875 
    operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14876 
                                  operands[2], const0_rtx);
14877 
 
14878 
  if (! positive_2)
14879 
    operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14880 
                                                            GET_CODE (operands[3])),
14881 
                                  SImode,
14882 
                                  operands[4], const0_rtx);
14883 
  else if (GET_MODE (operands[3]) != SImode)
14884 
    operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14885 
                                  operands[4], const0_rtx);
14886 
 
14887 
  if (positive_1 == positive_2)
14888 
    {
14889 
      operands[1] = gen_rtx_NOT (SImode, operands[1]);
14890 
      operands[5] = constm1_rtx;
14891 
    }
14892 
  else
14893 
    {
14894 
      operands[5] = const1_rtx;
14895 
    }
14896 
}")
14897 
 
14898 
;; Unconditional branch and return.
14899 
 
14900 
(define_insn "jump"
14901 
  [(set (pc)
14902 
        (label_ref (match_operand 0 "" "")))]
14903 
  ""
14904 
  "b %l0"
14905 
  [(set_attr "type" "branch")])
14906 
 
14907 
(define_insn "return"
14908 
  [(return)]
14909 
  "direct_return ()"
14910 
  "{br|blr}"
14911 
  [(set_attr "type" "jmpreg")])
14912 
 
14913 
(define_expand "indirect_jump"
14914 
  [(set (pc) (match_operand 0 "register_operand" ""))])
14915 
 
14916 
(define_insn "*indirect_jump"
14917 
  [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14918 
  ""
14919 
  "@
14920 
   bctr
14921 
   {br|blr}"
14922 
  [(set_attr "type" "jmpreg")])
14923 
 
14924 
;; Table jump for switch statements:
14925 
(define_expand "tablejump"
14926 
  [(use (match_operand 0 "" ""))
14927 
   (use (label_ref (match_operand 1 "" "")))]
14928 
  ""
14929 
  "
14930 
{
14931 
  if (TARGET_32BIT)
14932 
    emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14933 
  else
14934 
    emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14935 
  DONE;
14936 
}")
14937 
 
14938 
(define_expand "tablejumpsi"
14939 
  [(set (match_dup 3)
14940 
        (plus:SI (match_operand:SI 0 "" "")
14941 
                 (match_dup 2)))
14942 
   (parallel [(set (pc) (match_dup 3))
14943 
              (use (label_ref (match_operand 1 "" "")))])]
14944 
  "TARGET_32BIT"
14945 
  "
14946 
{ operands[0] = force_reg (SImode, operands[0]);
14947 
  operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14948 
  operands[3] = gen_reg_rtx (SImode);
14949 
}")
14950 
 
14951 
(define_expand "tablejumpdi"
14952 
  [(set (match_dup 4)
14953 
        (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14954 
   (set (match_dup 3)
14955 
        (plus:DI (match_dup 4)
14956 
                 (match_dup 2)))
14957 
   (parallel [(set (pc) (match_dup 3))
14958 
              (use (label_ref (match_operand 1 "" "")))])]
14959 
  "TARGET_64BIT"
14960 
  "
14961 
{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14962 
  operands[3] = gen_reg_rtx (DImode);
14963 
  operands[4] = gen_reg_rtx (DImode);
14964 
}")
14965 
 
14966 
(define_insn "*tablejump_internal1"
14967 
  [(set (pc)
14968 
        (match_operand:P 0 "register_operand" "c,*l"))
14969 
   (use (label_ref (match_operand 1 "" "")))]
14970 
  ""
14971 
  "@
14972 
   bctr
14973 
   {br|blr}"
14974 
  [(set_attr "type" "jmpreg")])
14975 
 
14976 
(define_insn "nop"
14977 
  [(const_int 0)]
14978 
  ""
14979 
  "{cror 0,0,0|nop}")
14980 
 
14981 
;; Define the subtract-one-and-jump insns, starting with the template
14982 
;; so loop.c knows what to generate.
14983 
 
14984 
(define_expand "doloop_end"
14985 
  [(use (match_operand 0 "" ""))        ; loop pseudo
14986 
   (use (match_operand 1 "" ""))        ; iterations; zero if unknown
14987 
   (use (match_operand 2 "" ""))        ; max iterations
14988 
   (use (match_operand 3 "" ""))        ; loop level
14989 
   (use (match_operand 4 "" ""))]       ; label
14990 
  ""
14991 
  "
14992 
{
14993 
  /* Only use this on innermost loops.  */
14994 
  if (INTVAL (operands[3]) > 1)
14995 
    FAIL;
14996 
  if (TARGET_64BIT)
14997 
    {
14998 
      if (GET_MODE (operands[0]) != DImode)
14999 
        FAIL;
15000 
      emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
15001 
    }
15002 
  else
15003 
    {
15004 
      if (GET_MODE (operands[0]) != SImode)
15005 
        FAIL;
15006 
      emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15007 
    }
15008 
  DONE;
15009 
}")
15010 
 
15011 
(define_expand "ctr"
15012 
  [(parallel [(set (pc)
15013 
                   (if_then_else (ne (match_operand:P 0 "register_operand" "")
15014 
                                     (const_int 1))
15015 
                                 (label_ref (match_operand 1 "" ""))
15016 
                                 (pc)))
15017 
              (set (match_dup 0)
15018 
                   (plus:P (match_dup 0)
15019 
                            (const_int -1)))
15020 
              (clobber (match_scratch:CC 2 ""))
15021 
              (clobber (match_scratch:P 3 ""))])]
15022 
  ""
15023 
  "")
15024 
 
15025 
;; We need to be able to do this for any operand, including MEM, or we
15026 
;; will cause reload to blow up since we don't allow output reloads on
15027 
;; JUMP_INSNs.
15028 
;; For the length attribute to be calculated correctly, the
15029 
;; label MUST be operand 0.
15030 
 
15031 
(define_insn "*ctr_internal1"
15032 
  [(set (pc)
15033 
        (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15034 
                          (const_int 1))
15035 
                      (label_ref (match_operand 0 "" ""))
15036 
                      (pc)))
15037 
   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15038 
        (plus:P (match_dup 1)
15039 
                 (const_int -1)))
15040 
   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15041 
   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15042 
  ""
15043 
  "*
15044 
{
15045 
  if (which_alternative != 0)
15046 
    return \"#\";
15047 
  else if (get_attr_length (insn) == 4)
15048 
    return \"{bdn|bdnz} %l0\";
15049 
  else
15050 
    return \"bdz $+8\;b %l0\";
15051 
}"
15052 
  [(set_attr "type" "branch")
15053 
   (set_attr "length" "*,12,16,16")])
15054 
 
15055 
(define_insn "*ctr_internal2"
15056 
  [(set (pc)
15057 
        (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15058 
                          (const_int 1))
15059 
                      (pc)
15060 
                      (label_ref (match_operand 0 "" ""))))
15061 
   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15062 
        (plus:P (match_dup 1)
15063 
                 (const_int -1)))
15064 
   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15065 
   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15066 
  ""
15067 
  "*
15068 
{
15069 
  if (which_alternative != 0)
15070 
    return \"#\";
15071 
  else if (get_attr_length (insn) == 4)
15072 
    return \"bdz %l0\";
15073 
  else
15074 
    return \"{bdn|bdnz} $+8\;b %l0\";
15075 
}"
15076 
  [(set_attr "type" "branch")
15077 
   (set_attr "length" "*,12,16,16")])
15078 
 
15079 
;; Similar but use EQ
15080 
 
15081 
(define_insn "*ctr_internal5"
15082 
  [(set (pc)
15083 
        (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15084 
                          (const_int 1))
15085 
                      (label_ref (match_operand 0 "" ""))
15086 
                      (pc)))
15087 
   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15088 
        (plus:P (match_dup 1)
15089 
                 (const_int -1)))
15090 
   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15091 
   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15092 
  ""
15093 
  "*
15094 
{
15095 
  if (which_alternative != 0)
15096 
    return \"#\";
15097 
  else if (get_attr_length (insn) == 4)
15098 
    return \"bdz %l0\";
15099 
  else
15100 
    return \"{bdn|bdnz} $+8\;b %l0\";
15101 
}"
15102 
  [(set_attr "type" "branch")
15103 
   (set_attr "length" "*,12,16,16")])
15104 
 
15105 
(define_insn "*ctr_internal6"
15106 
  [(set (pc)
15107 
        (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15108 
                          (const_int 1))
15109 
                      (pc)
15110 
                      (label_ref (match_operand 0 "" ""))))
15111 
   (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15112 
        (plus:P (match_dup 1)
15113 
                 (const_int -1)))
15114 
   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15115 
   (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15116 
  ""
15117 
  "*
15118 
{
15119 
  if (which_alternative != 0)
15120 
    return \"#\";
15121 
  else if (get_attr_length (insn) == 4)
15122 
    return \"{bdn|bdnz} %l0\";
15123 
  else
15124 
    return \"bdz $+8\;b %l0\";
15125 
}"
15126 
  [(set_attr "type" "branch")
15127 
   (set_attr "length" "*,12,16,16")])
15128 
 
15129 
;; Now the splitters if we could not allocate the CTR register
15130 
 
15131 
(define_split
15132 
  [(set (pc)
15133 
        (if_then_else (match_operator 2 "comparison_operator"
15134 
                                      [(match_operand:P 1 "gpc_reg_operand" "")
15135 
                                       (const_int 1)])
15136 
                      (match_operand 5 "" "")
15137 
                      (match_operand 6 "" "")))
15138 
   (set (match_operand:P 0 "gpc_reg_operand" "")
15139 
        (plus:P (match_dup 1) (const_int -1)))
15140 
   (clobber (match_scratch:CC 3 ""))
15141 
   (clobber (match_scratch:P 4 ""))]
15142 
  "reload_completed"
15143 
  [(parallel [(set (match_dup 3)
15144 
                   (compare:CC (plus:P (match_dup 1)
15145 
                                        (const_int -1))
15146 
                               (const_int 0)))
15147 
              (set (match_dup 0)
15148 
                   (plus:P (match_dup 1)
15149 
                            (const_int -1)))])
15150 
   (set (pc) (if_then_else (match_dup 7)
15151 
                           (match_dup 5)
15152 
                           (match_dup 6)))]
15153 
  "
15154 
{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15155 
                                operands[3], const0_rtx); }")
15156 
 
15157 
(define_split
15158 
  [(set (pc)
15159 
        (if_then_else (match_operator 2 "comparison_operator"
15160 
                                      [(match_operand:P 1 "gpc_reg_operand" "")
15161 
                                       (const_int 1)])
15162 
                      (match_operand 5 "" "")
15163 
                      (match_operand 6 "" "")))
15164 
   (set (match_operand:P 0 "nonimmediate_operand" "")
15165 
        (plus:P (match_dup 1) (const_int -1)))
15166 
   (clobber (match_scratch:CC 3 ""))
15167 
   (clobber (match_scratch:P 4 ""))]
15168 
  "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15169 
  [(parallel [(set (match_dup 3)
15170 
                   (compare:CC (plus:P (match_dup 1)
15171 
                                        (const_int -1))
15172 
                               (const_int 0)))
15173 
              (set (match_dup 4)
15174 
                   (plus:P (match_dup 1)
15175 
                            (const_int -1)))])
15176 
   (set (match_dup 0)
15177 
        (match_dup 4))
15178 
   (set (pc) (if_then_else (match_dup 7)
15179 
                           (match_dup 5)
15180 
                           (match_dup 6)))]
15181 
  "
15182 
{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15183 
                                operands[3], const0_rtx); }")
15184 
 
15185 
(define_insn "trap"
15186 
  [(trap_if (const_int 1) (const_int 0))]
15187 
  ""
15188 
  "{t 31,0,0|trap}"
15189 
  [(set_attr "type" "trap")])
15190 
 
15191 
(define_expand "ctrap4"
15192 
  [(trap_if (match_operator 0 "ordered_comparison_operator"
15193 
                            [(match_operand:GPR 1 "register_operand")
15194 
                             (match_operand:GPR 2 "reg_or_short_operand")])
15195 
            (match_operand 3 "zero_constant" ""))]
15196 
  ""
15197 
  "")
15198 
 
15199 
(define_insn ""
15200 
  [(trap_if (match_operator 0 "ordered_comparison_operator"
15201 
                            [(match_operand:GPR 1 "register_operand" "r")
15202 
                             (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15203 
            (const_int 0))]
15204 
  ""
15205 
  "{t|t}%V0%I2 %1,%2"
15206 
  [(set_attr "type" "trap")])
15207 
 
15208 
;; Insns related to generating the function prologue and epilogue.
15209 
 
15210 
(define_expand "prologue"
15211 
  [(use (const_int 0))]
15212 
  "TARGET_SCHED_PROLOG"
15213 
  "
15214 
{
15215 
      rs6000_emit_prologue ();
15216 
      DONE;
15217 
}")
15218 
 
15219 
(define_insn "*movesi_from_cr_one"
15220 
  [(match_parallel 0 "mfcr_operation"
15221 
                   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15222 
                         (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15223 
                                     (match_operand 3 "immediate_operand" "n")]
15224 
                          UNSPEC_MOVESI_FROM_CR))])]
15225 
  "TARGET_MFCRF"
15226 
  "*
15227 
{
15228 
  int mask = 0;
15229 
  int i;
15230 
  for (i = 0; i < XVECLEN (operands[0], 0); i++)
15231 
  {
15232 
    mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15233 
    operands[4] = GEN_INT (mask);
15234 
    output_asm_insn (\"mfcr %1,%4\", operands);
15235 
  }
15236 
  return \"\";
15237 
}"
15238 
  [(set_attr "type" "mfcrf")])
15239 
 
15240 
(define_insn "movesi_from_cr"
15241 
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15242 
        (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15243 
                    (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15244 
                    (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15245 
                    (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15246 
                   UNSPEC_MOVESI_FROM_CR))]
15247 
  ""
15248 
  "mfcr %0"
15249 
  [(set_attr "type" "mfcr")])
15250 
 
15251 
(define_insn "*stmw"
15252 
  [(match_parallel 0 "stmw_operation"
15253 
                   [(set (match_operand:SI 1 "memory_operand" "=m")
15254 
                         (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15255 
  "TARGET_MULTIPLE"
15256 
  "{stm|stmw} %2,%1"
15257 
  [(set_attr "type" "store_ux")])
15258 
 
15259 
(define_insn "*save_gpregs_"
15260 
  [(match_parallel 0 "any_parallel_operand"
15261 
                   [(clobber (reg:P 65))
15262 
                    (use (match_operand:P 1 "symbol_ref_operand" "s"))
15263 
                    (use (match_operand:P 2 "gpc_reg_operand" "r"))
15264 
                    (set (match_operand:P 3 "memory_operand" "=m")
15265 
                         (match_operand:P 4 "gpc_reg_operand" "r"))])]
15266 
  ""
15267 
  "bl %1"
15268 
  [(set_attr "type" "branch")
15269 
   (set_attr "length" "4")])
15270 
 
15271 
(define_insn "*save_fpregs_"
15272 
  [(match_parallel 0 "any_parallel_operand"
15273 
                   [(clobber (reg:P 65))
15274 
                    (use (match_operand:P 1 "symbol_ref_operand" "s"))
15275 
                    (use (match_operand:P 2 "gpc_reg_operand" "r"))
15276 
                    (set (match_operand:DF 3 "memory_operand" "=m")
15277 
                         (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15278 
  ""
15279 
  "bl %1"
15280 
  [(set_attr "type" "branch")
15281 
   (set_attr "length" "4")])
15282 
 
15283 
; These are to explain that changes to the stack pointer should
15284 
; not be moved over stores to stack memory.
15285 
(define_insn "stack_tie"
15286 
  [(set (match_operand:BLK 0 "memory_operand" "+m")
15287 
        (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15288 
  ""
15289 
  ""
15290 
  [(set_attr "length" "0")])
15291 
 
15292 
; Like stack_tie, but depend on both fp and sp based memory.
15293 
(define_insn "frame_tie"
15294 
  [(set (match_operand:BLK 0 "memory_operand" "+m")
15295 
        (unspec:BLK [(match_dup 0)
15296 
                     (match_operand:BLK 1 "memory_operand" "m")] UNSPEC_TIE))]
15297 
  ""
15298 
  ""
15299 
  [(set_attr "length" "0")])
15300 
 
15301 
 
15302 
(define_expand "epilogue"
15303 
  [(use (const_int 0))]
15304 
  "TARGET_SCHED_PROLOG"
15305 
  "
15306 
{
15307 
      rs6000_emit_epilogue (FALSE);
15308 
      DONE;
15309 
}")
15310 
 
15311 
; On some processors, doing the mtcrf one CC register at a time is
15312 
; faster (like on the 604e).  On others, doing them all at once is
15313 
; faster; for instance, on the 601 and 750.
15314 
 
15315 
(define_expand "movsi_to_cr_one"
15316 
  [(set (match_operand:CC 0 "cc_reg_operand" "")
15317 
        (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15318 
                    (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15319 
  ""
15320 
  "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15321 
 
15322 
(define_insn "*movsi_to_cr"
15323 
  [(match_parallel 0 "mtcrf_operation"
15324 
                   [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15325 
                         (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15326 
                                     (match_operand 3 "immediate_operand" "n")]
15327 
                                    UNSPEC_MOVESI_TO_CR))])]
15328 
 ""
15329 
 "*
15330 
{
15331 
  int mask = 0;
15332 
  int i;
15333 
  for (i = 0; i < XVECLEN (operands[0], 0); i++)
15334 
    mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15335 
  operands[4] = GEN_INT (mask);
15336 
  return \"mtcrf %4,%2\";
15337 
}"
15338 
  [(set_attr "type" "mtcr")])
15339 
 
15340 
(define_insn "*mtcrfsi"
15341 
  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15342 
        (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15343 
                    (match_operand 2 "immediate_operand" "n")]
15344 
                   UNSPEC_MOVESI_TO_CR))]
15345 
  "GET_CODE (operands[0]) == REG
15346 
   && CR_REGNO_P (REGNO (operands[0]))
15347 
   && GET_CODE (operands[2]) == CONST_INT
15348 
   && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15349 
  "mtcrf %R0,%1"
15350 
  [(set_attr "type" "mtcr")])
15351 
 
15352 
; The load-multiple instructions have similar properties.
15353 
; Note that "load_multiple" is a name known to the machine-independent
15354 
; code that actually corresponds to the PowerPC load-string.
15355 
 
15356 
(define_insn "*lmw"
15357 
  [(match_parallel 0 "lmw_operation"
15358 
                   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15359 
                         (match_operand:SI 2 "memory_operand" "m"))])]
15360 
  "TARGET_MULTIPLE"
15361 
  "{lm|lmw} %1,%2"
15362 
  [(set_attr "type" "load_ux")
15363 
   (set_attr "cell_micro" "always")])
15364 
 
15365 
(define_insn "*return_internal_"
15366 
  [(return)
15367 
   (use (match_operand:P 0 "register_operand" "lc"))]
15368 
  ""
15369 
  "b%T0"
15370 
  [(set_attr "type" "jmpreg")])
15371 
 
15372 
; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15373 
; stuff was in GCC.  Oh, and "any_parallel_operand" is a bit flexible...
15374 
 
15375 
(define_insn "*restore_gpregs_"
15376 
 [(match_parallel 0 "any_parallel_operand"
15377 
                  [(clobber (match_operand:P 1 "register_operand" "=l"))
15378 
                   (use (match_operand:P 2 "symbol_ref_operand" "s"))
15379 
                   (use (match_operand:P 3 "gpc_reg_operand" "r"))
15380 
                   (set (match_operand:P 4 "gpc_reg_operand" "=r")
15381 
                        (match_operand:P 5 "memory_operand" "m"))])]
15382 
 ""
15383 
 "bl %2"
15384 
 [(set_attr "type" "branch")
15385 
  (set_attr "length" "4")])
15386 
 
15387 
(define_insn "*return_and_restore_gpregs_"
15388 
 [(match_parallel 0 "any_parallel_operand"
15389 
                  [(return)
15390 
                   (clobber (match_operand:P 1 "register_operand" "=l"))
15391 
                   (use (match_operand:P 2 "symbol_ref_operand" "s"))
15392 
                   (use (match_operand:P 3 "gpc_reg_operand" "r"))
15393 
                   (set (match_operand:P 4 "gpc_reg_operand" "=r")
15394 
                        (match_operand:P 5 "memory_operand" "m"))])]
15395 
 ""
15396 
 "b %2"
15397 
 [(set_attr "type" "branch")
15398 
  (set_attr "length" "4")])
15399 
 
15400 
(define_insn "*return_and_restore_fpregs_"
15401 
 [(match_parallel 0 "any_parallel_operand"
15402 
                  [(return)
15403 
                   (clobber (match_operand:P 1 "register_operand" "=l"))
15404 
                   (use (match_operand:P 2 "symbol_ref_operand" "s"))
15405 
                   (use (match_operand:P 3 "gpc_reg_operand" "r"))
15406 
                   (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15407 
                        (match_operand:DF 5 "memory_operand" "m"))])]
15408 
 ""
15409 
 "b %2"
15410 
 [(set_attr "type" "branch")
15411 
  (set_attr "length" "4")])
15412 
 
15413 
(define_insn "*return_and_restore_fpregs_aix_"
15414 
 [(match_parallel 0 "any_parallel_operand"
15415 
                  [(return)
15416 
                   (use (match_operand:P 1 "register_operand" "l"))
15417 
                   (use (match_operand:P 2 "symbol_ref_operand" "s"))
15418 
                   (use (match_operand:P 3 "gpc_reg_operand" "r"))
15419 
                   (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15420 
                        (match_operand:DF 5 "memory_operand" "m"))])]
15421 
 ""
15422 
 "b %2"
15423 
 [(set_attr "type" "branch")
15424 
  (set_attr "length" "4")])
15425 
 
15426 
; This is used in compiling the unwind routines.
15427 
(define_expand "eh_return"
15428 
  [(use (match_operand 0 "general_operand" ""))]
15429 
  ""
15430 
  "
15431 
{
15432 
  if (TARGET_32BIT)
15433 
    emit_insn (gen_eh_set_lr_si (operands[0]));
15434 
  else
15435 
    emit_insn (gen_eh_set_lr_di (operands[0]));
15436 
  DONE;
15437 
}")
15438 
 
15439 
; We can't expand this before we know where the link register is stored.
15440 
(define_insn "eh_set_lr_"
15441 
  [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15442 
                    UNSPECV_EH_RR)
15443 
   (clobber (match_scratch:P 1 "=&b"))]
15444 
  ""
15445 
  "#")
15446 
 
15447 
(define_split
15448 
  [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15449 
   (clobber (match_scratch 1 ""))]
15450 
  "reload_completed"
15451 
  [(const_int 0)]
15452 
  "
15453 
{
15454 
  rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15455 
  DONE;
15456 
}")
15457 
 
15458 
(define_insn "prefetch"
15459 
  [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15460 
             (match_operand:SI 1 "const_int_operand" "n")
15461 
             (match_operand:SI 2 "const_int_operand" "n"))]
15462 
  "TARGET_POWERPC"
15463 
  "*
15464 
{
15465 
  if (GET_CODE (operands[0]) == REG)
15466 
    return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15467 
  return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15468 
}"
15469 
  [(set_attr "type" "load")])
15470 
 
15471 
(define_insn "bpermd_"
15472 
  [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15473 
        (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15474 
                   (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15475 
  "TARGET_POPCNTD"
15476 
  "bpermd %0,%1,%2"
15477 
  [(set_attr "type" "integer")])
15478 
 
15479 
 
15480 
 
15481 
(include "sync.md")
15482 
(include "vector.md")
15483 
(include "vsx.md")
15484 
(include "altivec.md")
15485 
(include "spe.md")
15486 
(include "dfp.md")
15487 
(include "paired.md")

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.