OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc2/] [gcc/] [testsuite/] [gcc.dg/] [pr43139.c] - Blame information for rev 298

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* PR target/43139 */
2
/* { dg-do compile { target fpic } } */
3
/* { dg-options "-g -O2 -fpic" } */
4
 
5
typedef double T1[10];
6
typedef double T2[10][10];
7
typedef int T3[10];
8
 
9
void __attribute__((noinline))
10
fn1 (void)
11
{
12
  asm volatile ("" : : : "memory");
13
}
14
 
15
void __attribute__((noinline))
16
fn2 (int x, ...)
17
{
18
  asm volatile ("" : : "r" (x) : "memory");
19
}
20
 
21
static void
22
bar (double v, double w, double x, double y, double z)
23
{
24
  double a;
25
  if (v / w < 200.0)
26
    {
27
      a = x + (y - x) * __builtin_exp (-v / w);
28
      fn2 (0);
29
      fn2 (1, a * 20.2 / z, z);
30
      fn1 ();
31
    }
32
}
33
 
34
static void
35
baz (T2 u, T2 v, T2 t, T2 x, T1 y, T3 z, double q, int j, int k)
36
{
37
  int i = z[k];
38
  if (u[i][j] > 0.0)
39
    bar (q, x[i][j], v[i][j], t[i][j], y[i]);
40
}
41
 
42
static T2 a, b, c, d;
43
static T1 e;
44
static T3 f;
45
 
46
void __attribute__((noinline))
47
test (int j, int k, double q)
48
{
49
  baz (a, b, c, d, e, f, q, j, k);
50
}
51
 
52
int
53
main (void)
54
{
55
  d[0][6] = 1.0;
56
  a[0][6] = 2.0;
57
  test (6, 7, 400.0);
58
  return 0;
59
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.