OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc2/] [gcc/] [testsuite/] [gcc.dg/] [vect/] [pr22480.c] - Blame information for rev 384

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
/* { dg-do compile } */
2
/* { dg-require-effective-target vect_shift } */
3
 
4
void
5
test_1 (void)
6
{
7
  static unsigned int bm[16];
8
  int j;
9
  for (j = 0; j < 16; j++)
10
    bm[j] <<= 8;
11
}
12
 
13
void
14
test_2 (int a)
15
{
16
  static unsigned int bm[16];
17
  int j;
18
  for (j = 0; j < 16; j++)
19
    bm[j] <<= a;
20
}
21
 
22
void
23
test_3 (void)
24
{
25
 static unsigned bm[16];
26
 int am[16];
27
 int j;
28
 for (j = 0; j < 16;j++)
29
   bm[j] <<= am[j];
30
}
31
 
32
/* { dg-final { cleanup-tree-dump "vect" } } */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.