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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc2/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-cell-6.c] - Blame information for rev 384

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/* { dg-do compile  } */
/* { dg-require-effective-target powerpc_altivec_ok } */
/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */
#include <altivec.h>
 
/* This used to ICE with reloading of a constant address. */
 
vector float f(void)
{
  vector float * a = (void*)16;
  return vec_lvlx (0, a);
}

Line No.	Rev	Author	Line
1	322	jeremybenn	`/* { dg-do compile } */`
2			`/* { dg-require-effective-target powerpc_altivec_ok } */`
3			`/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */`
4			`#include <altivec.h>`
5
6			`/* This used to ICE with reloading of a constant address. */`
7
8			`vector float f(void)`
9			`{`
10			`vector float * a = (void*)16;`
11			`return vec_lvlx (0, a);`
12			`}`

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc2/] [gcc/] [testsuite/] [gcc.target/] [powerpc/] [altivec-cell-6.c] - Blame information for rev 384