OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gcc-4.5.1/] [gcc-4.5.1-or32-1.0rc3/] [gcc/] [testsuite/] [gcc.dg/] [vmx/] [x-04.c] - Blame information for rev 516

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 298 jeremybenn
#include <altivec.h>
2
vector unsigned char
3
permute_128(vector unsigned char input)
4
{
5
  vector unsigned char result, new_bit;
6
 
7
  vector unsigned char select2 = ((vector unsigned char){2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2});
8
  vector unsigned char select3 = ((vector unsigned char){4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4});
9
  vector unsigned char select4 = ((vector unsigned char){8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8});
10
  vector unsigned char select5 = ((vector unsigned char){16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16});
11
  vector unsigned char select6 = ((vector unsigned char){32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32});
12
  vector unsigned char select7 = ((vector unsigned char){64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64});
13
  vector unsigned char select8 = ((vector unsigned char){128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128});
14
 
15
  vector unsigned char control1
16
    = ((vector unsigned char){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0});
17
  vector unsigned char control2
18
    = ((vector unsigned char){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0});
19
  vector unsigned char control3
20
    = ((vector unsigned char){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0});
21
  vector unsigned char control4
22
    = ((vector unsigned char){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0});
23
  vector unsigned char control5
24
    = ((vector unsigned char){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0});
25
  vector unsigned char control6
26
    = ((vector unsigned char){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0});
27
  vector unsigned char control7
28
    = ((vector unsigned char){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0});
29
  vector unsigned char control8
30
    = ((vector unsigned char){15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0});
31
  vector unsigned char rotate1 = ((vector unsigned char){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1});
32
  vector unsigned char rotate2 = ((vector unsigned char){3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3});
33
  vector unsigned char rotate3 = ((vector unsigned char){5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5});
34
  vector unsigned char rotate4 = ((vector unsigned char){7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7});
35
  vector unsigned char rotate5 = ((vector unsigned char){1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1});
36
  vector unsigned char rotate6 = ((vector unsigned char){3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3});
37
  vector unsigned char rotate7 = ((vector unsigned char){5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5});
38
  vector unsigned char rotate8 = ((vector unsigned char){7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7});
39
 
40
  result = vec_vperm(input, input, control1);
41
  result = vec_rl(result, rotate1);
42
 
43
  new_bit = vec_vperm(input, input, control2);
44
  new_bit = vec_rl(new_bit, rotate2);
45
  result = vec_sel(result, new_bit, select2);
46
 
47
  new_bit = vec_vperm(input, input, control3);
48
  new_bit = vec_rl(new_bit, rotate3);
49
  result = vec_sel(result, new_bit, select3);
50
 
51
  new_bit = vec_vperm(input, input, control4);
52
  new_bit = vec_rl(new_bit, rotate4);
53
  result = vec_sel(result, new_bit, select4);
54
 
55
  new_bit = vec_vperm(input, input, control5);
56
  new_bit = vec_rl(new_bit, rotate5);
57
  result = vec_sel(result, new_bit, select5);
58
 
59
  new_bit = vec_vperm(input, input, control6);
60
  new_bit = vec_rl(new_bit, rotate6);
61
  result = vec_sel(result, new_bit, select6);
62
 
63
  new_bit = vec_vperm(input, input, control7);
64
  new_bit = vec_rl(new_bit, rotate7);
65
  result = vec_sel(result, new_bit, select7);
66
 
67
  new_bit = vec_vperm(input, input, control8);
68
  new_bit = vec_rl(new_bit, rotate8);
69
  result = vec_sel(result, new_bit, select8);
70
 
71
  return result;
72
}
73
 
74
int main()
75
{
76
  vector unsigned char input
77
    = ((vector unsigned char){0,1,2,4,8,16,32,64,128,0,1,2,4,8,16,32});
78
  vector unsigned char result = permute_128(input);
79
  return 0;
80
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.