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1 24 jeremybenn
@section Relocations
2
BFD maintains relocations in much the same way it maintains
3
symbols: they are left alone until required, then read in
4
en-masse and translated into an internal form.  A common
5
routine @code{bfd_perform_relocation} acts upon the
6
canonical form to do the fixup.
7
 
8
Relocations are maintained on a per section basis,
9
while symbols are maintained on a per BFD basis.
10
 
11
All that a back end has to do to fit the BFD interface is to create
12
a @code{struct reloc_cache_entry} for each relocation
13
in a particular section, and fill in the right bits of the structures.
14
 
15
@menu
16
* typedef arelent::
17
* howto manager::
18
@end menu
19
 
20
 
21
@node typedef arelent, howto manager, Relocations, Relocations
22
@subsection typedef arelent
23
This is the structure of a relocation entry:
24
 
25
 
26
@example
27
 
28
typedef enum bfd_reloc_status
29
@{
30
  /* No errors detected.  */
31
  bfd_reloc_ok,
32
 
33
  /* The relocation was performed, but there was an overflow.  */
34
  bfd_reloc_overflow,
35
 
36
  /* The address to relocate was not within the section supplied.  */
37
  bfd_reloc_outofrange,
38
 
39
  /* Used by special functions.  */
40
  bfd_reloc_continue,
41
 
42
  /* Unsupported relocation size requested.  */
43
  bfd_reloc_notsupported,
44
 
45
  /* Unused.  */
46
  bfd_reloc_other,
47
 
48
  /* The symbol to relocate against was undefined.  */
49
  bfd_reloc_undefined,
50
 
51
  /* The relocation was performed, but may not be ok - presently
52
     generated only when linking i960 coff files with i960 b.out
53
     symbols.  If this type is returned, the error_message argument
54
     to bfd_perform_relocation will be set.  */
55
  bfd_reloc_dangerous
56
 @}
57
 bfd_reloc_status_type;
58
 
59
 
60
typedef struct reloc_cache_entry
61
@{
62
  /* A pointer into the canonical table of pointers.  */
63
  struct bfd_symbol **sym_ptr_ptr;
64
 
65
  /* offset in section.  */
66
  bfd_size_type address;
67
 
68
  /* addend for relocation value.  */
69
  bfd_vma addend;
70
 
71
  /* Pointer to how to perform the required relocation.  */
72
  reloc_howto_type *howto;
73
 
74
@}
75
arelent;
76
 
77
@end example
78
@strong{Description}@*
79
Here is a description of each of the fields within an @code{arelent}:
80
 
81
@itemize @bullet
82
 
83
@item
84
@code{sym_ptr_ptr}
85
@end itemize
86
The symbol table pointer points to a pointer to the symbol
87
associated with the relocation request.  It is the pointer
88
into the table returned by the back end's
89
@code{canonicalize_symtab} action. @xref{Symbols}. The symbol is
90
referenced through a pointer to a pointer so that tools like
91
the linker can fix up all the symbols of the same name by
92
modifying only one pointer. The relocation routine looks in
93
the symbol and uses the base of the section the symbol is
94
attached to and the value of the symbol as the initial
95
relocation offset. If the symbol pointer is zero, then the
96
section provided is looked up.
97
 
98
@itemize @bullet
99
 
100
@item
101
@code{address}
102
@end itemize
103
The @code{address} field gives the offset in bytes from the base of
104
the section data which owns the relocation record to the first
105
byte of relocatable information. The actual data relocated
106
will be relative to this point; for example, a relocation
107
type which modifies the bottom two bytes of a four byte word
108
would not touch the first byte pointed to in a big endian
109
world.
110
 
111
@itemize @bullet
112
 
113
@item
114
@code{addend}
115
@end itemize
116
The @code{addend} is a value provided by the back end to be added (!)
117
to the relocation offset. Its interpretation is dependent upon
118
the howto. For example, on the 68k the code:
119
 
120
@example
121
        char foo[];
122
        main()
123
                @{
124
                return foo[0x12345678];
125
                @}
126
@end example
127
 
128
Could be compiled into:
129
 
130
@example
131
        linkw fp,#-4
132
        moveb @@#12345678,d0
133
        extbl d0
134
        unlk fp
135
        rts
136
@end example
137
 
138
This could create a reloc pointing to @code{foo}, but leave the
139
offset in the data, something like:
140
 
141
@example
142
RELOCATION RECORDS FOR [.text]:
143
offset   type      value
144
00000006 32        _foo
145
 
146
00000000 4e56 fffc          ; linkw fp,#-4
147
00000004 1039 1234 5678     ; moveb @@#12345678,d0
148
0000000a 49c0               ; extbl d0
149
0000000c 4e5e               ; unlk fp
150
0000000e 4e75               ; rts
151
@end example
152
 
153
Using coff and an 88k, some instructions don't have enough
154
space in them to represent the full address range, and
155
pointers have to be loaded in two parts. So you'd get something like:
156
 
157
@example
158
        or.u     r13,r0,hi16(_foo+0x12345678)
159
        ld.b     r2,r13,lo16(_foo+0x12345678)
160
        jmp      r1
161
@end example
162
 
163
This should create two relocs, both pointing to @code{_foo}, and with
164
0x12340000 in their addend field. The data would consist of:
165
 
166
@example
167
RELOCATION RECORDS FOR [.text]:
168
offset   type      value
169
00000002 HVRT16    _foo+0x12340000
170
00000006 LVRT16    _foo+0x12340000
171
 
172
00000000 5da05678           ; or.u r13,r0,0x5678
173
00000004 1c4d5678           ; ld.b r2,r13,0x5678
174
00000008 f400c001           ; jmp r1
175
@end example
176
 
177
The relocation routine digs out the value from the data, adds
178
it to the addend to get the original offset, and then adds the
179
value of @code{_foo}. Note that all 32 bits have to be kept around
180
somewhere, to cope with carry from bit 15 to bit 16.
181
 
182
One further example is the sparc and the a.out format. The
183
sparc has a similar problem to the 88k, in that some
184
instructions don't have room for an entire offset, but on the
185
sparc the parts are created in odd sized lumps. The designers of
186
the a.out format chose to not use the data within the section
187
for storing part of the offset; all the offset is kept within
188
the reloc. Anything in the data should be ignored.
189
 
190
@example
191
        save %sp,-112,%sp
192
        sethi %hi(_foo+0x12345678),%g2
193
        ldsb [%g2+%lo(_foo+0x12345678)],%i0
194
        ret
195
        restore
196
@end example
197
 
198
Both relocs contain a pointer to @code{foo}, and the offsets
199
contain junk.
200
 
201
@example
202
RELOCATION RECORDS FOR [.text]:
203
offset   type      value
204
00000004 HI22      _foo+0x12345678
205
00000008 LO10      _foo+0x12345678
206
 
207
00000000 9de3bf90     ; save %sp,-112,%sp
208
00000004 05000000     ; sethi %hi(_foo+0),%g2
209
00000008 f048a000     ; ldsb [%g2+%lo(_foo+0)],%i0
210
0000000c 81c7e008     ; ret
211
00000010 81e80000     ; restore
212
@end example
213
 
214
@itemize @bullet
215
 
216
@item
217
@code{howto}
218
@end itemize
219
The @code{howto} field can be imagined as a
220
relocation instruction. It is a pointer to a structure which
221
contains information on what to do with all of the other
222
information in the reloc record and data section. A back end
223
would normally have a relocation instruction set and turn
224
relocations into pointers to the correct structure on input -
225
but it would be possible to create each howto field on demand.
226
 
227
@subsubsection @code{enum complain_overflow}
228
Indicates what sort of overflow checking should be done when
229
performing a relocation.
230
 
231
 
232
@example
233
 
234
enum complain_overflow
235
@{
236
  /* Do not complain on overflow.  */
237
  complain_overflow_dont,
238
 
239
  /* Complain if the value overflows when considered as a signed
240
     number one bit larger than the field.  ie. A bitfield of N bits
241
     is allowed to represent -2**n to 2**n-1.  */
242
  complain_overflow_bitfield,
243
 
244
  /* Complain if the value overflows when considered as a signed
245
     number.  */
246
  complain_overflow_signed,
247
 
248
  /* Complain if the value overflows when considered as an
249
     unsigned number.  */
250
  complain_overflow_unsigned
251
@};
252
@end example
253
@subsubsection @code{reloc_howto_type}
254
The @code{reloc_howto_type} is a structure which contains all the
255
information that libbfd needs to know to tie up a back end's data.
256
 
257
 
258
@example
259
struct bfd_symbol;             /* Forward declaration.  */
260
 
261
struct reloc_howto_struct
262
@{
263
  /*  The type field has mainly a documentary use - the back end can
264
      do what it wants with it, though normally the back end's
265
      external idea of what a reloc number is stored
266
      in this field.  For example, a PC relative word relocation
267
      in a coff environment has the type 023 - because that's
268
      what the outside world calls a R_PCRWORD reloc.  */
269
  unsigned int type;
270
 
271
  /*  The value the final relocation is shifted right by.  This drops
272
      unwanted data from the relocation.  */
273
  unsigned int rightshift;
274
 
275
  /*  The size of the item to be relocated.  This is *not* a
276
      power-of-two measure.  To get the number of bytes operated
277
      on by a type of relocation, use bfd_get_reloc_size.  */
278
  int size;
279
 
280
  /*  The number of bits in the item to be relocated.  This is used
281
      when doing overflow checking.  */
282
  unsigned int bitsize;
283
 
284
  /*  Notes that the relocation is relative to the location in the
285
      data section of the addend.  The relocation function will
286
      subtract from the relocation value the address of the location
287
      being relocated.  */
288
  bfd_boolean pc_relative;
289
 
290
  /*  The bit position of the reloc value in the destination.
291
      The relocated value is left shifted by this amount.  */
292
  unsigned int bitpos;
293
 
294
  /* What type of overflow error should be checked for when
295
     relocating.  */
296
  enum complain_overflow complain_on_overflow;
297
 
298
  /* If this field is non null, then the supplied function is
299
     called rather than the normal function.  This allows really
300
     strange relocation methods to be accommodated (e.g., i960 callj
301
     instructions).  */
302
  bfd_reloc_status_type (*special_function)
303
    (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
304
     bfd *, char **);
305
 
306
  /* The textual name of the relocation type.  */
307
  char *name;
308
 
309
  /* Some formats record a relocation addend in the section contents
310
     rather than with the relocation.  For ELF formats this is the
311
     distinction between USE_REL and USE_RELA (though the code checks
312
     for USE_REL == 1/0).  The value of this field is TRUE if the
313
     addend is recorded with the section contents; when performing a
314
     partial link (ld -r) the section contents (the data) will be
315
     modified.  The value of this field is FALSE if addends are
316
     recorded with the relocation (in arelent.addend); when performing
317
     a partial link the relocation will be modified.
318
     All relocations for all ELF USE_RELA targets should set this field
319
     to FALSE (values of TRUE should be looked on with suspicion).
320
     However, the converse is not true: not all relocations of all ELF
321
     USE_REL targets set this field to TRUE.  Why this is so is peculiar
322
     to each particular target.  For relocs that aren't used in partial
323
     links (e.g. GOT stuff) it doesn't matter what this is set to.  */
324
  bfd_boolean partial_inplace;
325
 
326
  /* src_mask selects the part of the instruction (or data) to be used
327
     in the relocation sum.  If the target relocations don't have an
328
     addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
329
     dst_mask to extract the addend from the section contents.  If
330
     relocations do have an addend in the reloc, eg. ELF USE_RELA, this
331
     field should be zero.  Non-zero values for ELF USE_RELA targets are
332
     bogus as in those cases the value in the dst_mask part of the
333
     section contents should be treated as garbage.  */
334
  bfd_vma src_mask;
335
 
336
  /* dst_mask selects which parts of the instruction (or data) are
337
     replaced with a relocated value.  */
338
  bfd_vma dst_mask;
339
 
340
  /* When some formats create PC relative instructions, they leave
341
     the value of the pc of the place being relocated in the offset
342
     slot of the instruction, so that a PC relative relocation can
343
     be made just by adding in an ordinary offset (e.g., sun3 a.out).
344
     Some formats leave the displacement part of an instruction
345
     empty (e.g., m88k bcs); this flag signals the fact.  */
346
  bfd_boolean pcrel_offset;
347
@};
348
 
349
@end example
350
@findex The HOWTO Macro
351
@subsubsection @code{The HOWTO Macro}
352
@strong{Description}@*
353
The HOWTO define is horrible and will go away.
354
@example
355
#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
356
  @{ (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC @}
357
@end example
358
 
359
@strong{Description}@*
360
And will be replaced with the totally magic way. But for the
361
moment, we are compatible, so do it this way.
362
@example
363
#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
364
  HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
365
         NAME, FALSE, 0, 0, IN)
366
 
367
@end example
368
 
369
@strong{Description}@*
370
This is used to fill in an empty howto entry in an array.
371
@example
372
#define EMPTY_HOWTO(C) \
373
  HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
374
         NULL, FALSE, 0, 0, FALSE)
375
 
376
@end example
377
 
378
@strong{Description}@*
379
Helper routine to turn a symbol into a relocation value.
380
@example
381
#define HOWTO_PREPARE(relocation, symbol)               \
382
  @{                                                     \
383
    if (symbol != NULL)                                 \
384
      @{                                                 \
385
        if (bfd_is_com_section (symbol->section))       \
386
          @{                                             \
387
            relocation = 0;                             \
388
          @}                                             \
389
        else                                            \
390
          @{                                             \
391
            relocation = symbol->value;                 \
392
          @}                                             \
393
      @}                                                 \
394
  @}
395
 
396
@end example
397
 
398
@findex bfd_get_reloc_size
399
@subsubsection @code{bfd_get_reloc_size}
400
@strong{Synopsis}
401
@example
402
unsigned int bfd_get_reloc_size (reloc_howto_type *);
403
@end example
404
@strong{Description}@*
405
For a reloc_howto_type that operates on a fixed number of bytes,
406
this returns the number of bytes operated on.
407
 
408
@findex arelent_chain
409
@subsubsection @code{arelent_chain}
410
@strong{Description}@*
411
How relocs are tied together in an @code{asection}:
412
@example
413
typedef struct relent_chain
414
@{
415
  arelent relent;
416
  struct relent_chain *next;
417
@}
418
arelent_chain;
419
 
420
@end example
421
 
422
@findex bfd_check_overflow
423
@subsubsection @code{bfd_check_overflow}
424
@strong{Synopsis}
425
@example
426
bfd_reloc_status_type bfd_check_overflow
427
   (enum complain_overflow how,
428
    unsigned int bitsize,
429
    unsigned int rightshift,
430
    unsigned int addrsize,
431
    bfd_vma relocation);
432
@end example
433
@strong{Description}@*
434
Perform overflow checking on @var{relocation} which has
435
@var{bitsize} significant bits and will be shifted right by
436
@var{rightshift} bits, on a machine with addresses containing
437
@var{addrsize} significant bits.  The result is either of
438
@code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
439
 
440
@findex bfd_perform_relocation
441
@subsubsection @code{bfd_perform_relocation}
442
@strong{Synopsis}
443
@example
444
bfd_reloc_status_type bfd_perform_relocation
445
   (bfd *abfd,
446
    arelent *reloc_entry,
447
    void *data,
448
    asection *input_section,
449
    bfd *output_bfd,
450
    char **error_message);
451
@end example
452
@strong{Description}@*
453
If @var{output_bfd} is supplied to this function, the
454
generated image will be relocatable; the relocations are
455
copied to the output file after they have been changed to
456
reflect the new state of the world. There are two ways of
457
reflecting the results of partial linkage in an output file:
458
by modifying the output data in place, and by modifying the
459
relocation record.  Some native formats (e.g., basic a.out and
460
basic coff) have no way of specifying an addend in the
461
relocation type, so the addend has to go in the output data.
462
This is no big deal since in these formats the output data
463
slot will always be big enough for the addend. Complex reloc
464
types with addends were invented to solve just this problem.
465
The @var{error_message} argument is set to an error message if
466
this return @code{bfd_reloc_dangerous}.
467
 
468
@findex bfd_install_relocation
469
@subsubsection @code{bfd_install_relocation}
470
@strong{Synopsis}
471
@example
472
bfd_reloc_status_type bfd_install_relocation
473
   (bfd *abfd,
474
    arelent *reloc_entry,
475
    void *data, bfd_vma data_start,
476
    asection *input_section,
477
    char **error_message);
478
@end example
479
@strong{Description}@*
480
This looks remarkably like @code{bfd_perform_relocation}, except it
481
does not expect that the section contents have been filled in.
482
I.e., it's suitable for use when creating, rather than applying
483
a relocation.
484
 
485
For now, this function should be considered reserved for the
486
assembler.
487
 
488
 
489
@node howto manager,  , typedef arelent, Relocations
490
@subsection The howto manager
491
When an application wants to create a relocation, but doesn't
492
know what the target machine might call it, it can find out by
493
using this bit of code.
494
 
495
@findex bfd_reloc_code_type
496
@subsubsection @code{bfd_reloc_code_type}
497
@strong{Description}@*
498
The insides of a reloc code.  The idea is that, eventually, there
499
will be one enumerator for every type of relocation we ever do.
500
Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll
501
return a howto pointer.
502
 
503
This does mean that the application must determine the correct
504
enumerator value; you can't get a howto pointer from a random set
505
of attributes.
506
 
507
Here are the possible values for @code{enum bfd_reloc_code_real}:
508
 
509
@deffn {} BFD_RELOC_64
510
@deffnx {} BFD_RELOC_32
511
@deffnx {} BFD_RELOC_26
512
@deffnx {} BFD_RELOC_24
513
@deffnx {} BFD_RELOC_16
514
@deffnx {} BFD_RELOC_14
515
@deffnx {} BFD_RELOC_8
516
Basic absolute relocations of N bits.
517
@end deffn
518
@deffn {} BFD_RELOC_64_PCREL
519
@deffnx {} BFD_RELOC_32_PCREL
520
@deffnx {} BFD_RELOC_24_PCREL
521
@deffnx {} BFD_RELOC_16_PCREL
522
@deffnx {} BFD_RELOC_12_PCREL
523
@deffnx {} BFD_RELOC_8_PCREL
524
PC-relative relocations.  Sometimes these are relative to the address
525
of the relocation itself; sometimes they are relative to the start of
526
the section containing the relocation.  It depends on the specific target.
527
 
528
The 24-bit relocation is used in some Intel 960 configurations.
529
@end deffn
530
@deffn {} BFD_RELOC_32_SECREL
531
Section relative relocations.  Some targets need this for DWARF2.
532
@end deffn
533
@deffn {} BFD_RELOC_32_GOT_PCREL
534
@deffnx {} BFD_RELOC_16_GOT_PCREL
535
@deffnx {} BFD_RELOC_8_GOT_PCREL
536
@deffnx {} BFD_RELOC_32_GOTOFF
537
@deffnx {} BFD_RELOC_16_GOTOFF
538
@deffnx {} BFD_RELOC_LO16_GOTOFF
539
@deffnx {} BFD_RELOC_HI16_GOTOFF
540
@deffnx {} BFD_RELOC_HI16_S_GOTOFF
541
@deffnx {} BFD_RELOC_8_GOTOFF
542
@deffnx {} BFD_RELOC_64_PLT_PCREL
543
@deffnx {} BFD_RELOC_32_PLT_PCREL
544
@deffnx {} BFD_RELOC_24_PLT_PCREL
545
@deffnx {} BFD_RELOC_16_PLT_PCREL
546
@deffnx {} BFD_RELOC_8_PLT_PCREL
547
@deffnx {} BFD_RELOC_64_PLTOFF
548
@deffnx {} BFD_RELOC_32_PLTOFF
549
@deffnx {} BFD_RELOC_16_PLTOFF
550
@deffnx {} BFD_RELOC_LO16_PLTOFF
551
@deffnx {} BFD_RELOC_HI16_PLTOFF
552
@deffnx {} BFD_RELOC_HI16_S_PLTOFF
553
@deffnx {} BFD_RELOC_8_PLTOFF
554
For ELF.
555
@end deffn
556
@deffn {} BFD_RELOC_68K_GLOB_DAT
557
@deffnx {} BFD_RELOC_68K_JMP_SLOT
558
@deffnx {} BFD_RELOC_68K_RELATIVE
559
Relocations used by 68K ELF.
560
@end deffn
561
@deffn {} BFD_RELOC_32_BASEREL
562
@deffnx {} BFD_RELOC_16_BASEREL
563
@deffnx {} BFD_RELOC_LO16_BASEREL
564
@deffnx {} BFD_RELOC_HI16_BASEREL
565
@deffnx {} BFD_RELOC_HI16_S_BASEREL
566
@deffnx {} BFD_RELOC_8_BASEREL
567
@deffnx {} BFD_RELOC_RVA
568
Linkage-table relative.
569
@end deffn
570
@deffn {} BFD_RELOC_8_FFnn
571
Absolute 8-bit relocation, but used to form an address like 0xFFnn.
572
@end deffn
573
@deffn {} BFD_RELOC_32_PCREL_S2
574
@deffnx {} BFD_RELOC_16_PCREL_S2
575
@deffnx {} BFD_RELOC_23_PCREL_S2
576
These PC-relative relocations are stored as word displacements --
577
i.e., byte displacements shifted right two bits.  The 30-bit word
578
displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
579
SPARC.  (SPARC tools generally refer to this as <<WDISP30>>.)  The
580
signed 16-bit displacement is used on the MIPS, and the 23-bit
581
displacement is used on the Alpha.
582
@end deffn
583
@deffn {} BFD_RELOC_HI22
584
@deffnx {} BFD_RELOC_LO10
585
High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
586
the target word.  These are used on the SPARC.
587
@end deffn
588
@deffn {} BFD_RELOC_GPREL16
589
@deffnx {} BFD_RELOC_GPREL32
590
For systems that allocate a Global Pointer register, these are
591
displacements off that register.  These relocation types are
592
handled specially, because the value the register will have is
593
decided relatively late.
594
@end deffn
595
@deffn {} BFD_RELOC_I960_CALLJ
596
Reloc types used for i960/b.out.
597
@end deffn
598
@deffn {} BFD_RELOC_NONE
599
@deffnx {} BFD_RELOC_SPARC_WDISP22
600
@deffnx {} BFD_RELOC_SPARC22
601
@deffnx {} BFD_RELOC_SPARC13
602
@deffnx {} BFD_RELOC_SPARC_GOT10
603
@deffnx {} BFD_RELOC_SPARC_GOT13
604
@deffnx {} BFD_RELOC_SPARC_GOT22
605
@deffnx {} BFD_RELOC_SPARC_PC10
606
@deffnx {} BFD_RELOC_SPARC_PC22
607
@deffnx {} BFD_RELOC_SPARC_WPLT30
608
@deffnx {} BFD_RELOC_SPARC_COPY
609
@deffnx {} BFD_RELOC_SPARC_GLOB_DAT
610
@deffnx {} BFD_RELOC_SPARC_JMP_SLOT
611
@deffnx {} BFD_RELOC_SPARC_RELATIVE
612
@deffnx {} BFD_RELOC_SPARC_UA16
613
@deffnx {} BFD_RELOC_SPARC_UA32
614
@deffnx {} BFD_RELOC_SPARC_UA64
615
SPARC ELF relocations.  There is probably some overlap with other
616
relocation types already defined.
617
@end deffn
618
@deffn {} BFD_RELOC_SPARC_BASE13
619
@deffnx {} BFD_RELOC_SPARC_BASE22
620
I think these are specific to SPARC a.out (e.g., Sun 4).
621
@end deffn
622
@deffn {} BFD_RELOC_SPARC_64
623
@deffnx {} BFD_RELOC_SPARC_10
624
@deffnx {} BFD_RELOC_SPARC_11
625
@deffnx {} BFD_RELOC_SPARC_OLO10
626
@deffnx {} BFD_RELOC_SPARC_HH22
627
@deffnx {} BFD_RELOC_SPARC_HM10
628
@deffnx {} BFD_RELOC_SPARC_LM22
629
@deffnx {} BFD_RELOC_SPARC_PC_HH22
630
@deffnx {} BFD_RELOC_SPARC_PC_HM10
631
@deffnx {} BFD_RELOC_SPARC_PC_LM22
632
@deffnx {} BFD_RELOC_SPARC_WDISP16
633
@deffnx {} BFD_RELOC_SPARC_WDISP19
634
@deffnx {} BFD_RELOC_SPARC_7
635
@deffnx {} BFD_RELOC_SPARC_6
636
@deffnx {} BFD_RELOC_SPARC_5
637
@deffnx {} BFD_RELOC_SPARC_DISP64
638
@deffnx {} BFD_RELOC_SPARC_PLT32
639
@deffnx {} BFD_RELOC_SPARC_PLT64
640
@deffnx {} BFD_RELOC_SPARC_HIX22
641
@deffnx {} BFD_RELOC_SPARC_LOX10
642
@deffnx {} BFD_RELOC_SPARC_H44
643
@deffnx {} BFD_RELOC_SPARC_M44
644
@deffnx {} BFD_RELOC_SPARC_L44
645
@deffnx {} BFD_RELOC_SPARC_REGISTER
646
SPARC64 relocations
647
@end deffn
648
@deffn {} BFD_RELOC_SPARC_REV32
649
SPARC little endian relocation
650
@end deffn
651
@deffn {} BFD_RELOC_SPARC_TLS_GD_HI22
652
@deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10
653
@deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD
654
@deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL
655
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22
656
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10
657
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD
658
@deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL
659
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22
660
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10
661
@deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD
662
@deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22
663
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10
664
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LD
665
@deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX
666
@deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD
667
@deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22
668
@deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10
669
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32
670
@deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64
671
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32
672
@deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64
673
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32
674
@deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64
675
SPARC TLS relocations
676
@end deffn
677
@deffn {} BFD_RELOC_SPU_IMM7
678
@deffnx {} BFD_RELOC_SPU_IMM8
679
@deffnx {} BFD_RELOC_SPU_IMM10
680
@deffnx {} BFD_RELOC_SPU_IMM10W
681
@deffnx {} BFD_RELOC_SPU_IMM16
682
@deffnx {} BFD_RELOC_SPU_IMM16W
683
@deffnx {} BFD_RELOC_SPU_IMM18
684
@deffnx {} BFD_RELOC_SPU_PCREL9a
685
@deffnx {} BFD_RELOC_SPU_PCREL9b
686
@deffnx {} BFD_RELOC_SPU_PCREL16
687
@deffnx {} BFD_RELOC_SPU_LO16
688
@deffnx {} BFD_RELOC_SPU_HI16
689
@deffnx {} BFD_RELOC_SPU_PPU32
690
@deffnx {} BFD_RELOC_SPU_PPU64
691
SPU Relocations.
692
@end deffn
693
@deffn {} BFD_RELOC_ALPHA_GPDISP_HI16
694
Alpha ECOFF and ELF relocations.  Some of these treat the symbol or
695
"addend" in some special way.
696
For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
697
writing; when reading, it will be the absolute section symbol.  The
698
addend is the displacement in bytes of the "lda" instruction from
699
the "ldah" instruction (which is at the address of this reloc).
700
@end deffn
701
@deffn {} BFD_RELOC_ALPHA_GPDISP_LO16
702
For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
703
with GPDISP_HI16 relocs.  The addend is ignored when writing the
704
relocations out, and is filled in with the file's GP value on
705
reading, for convenience.
706
@end deffn
707
@deffn {} BFD_RELOC_ALPHA_GPDISP
708
The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
709
relocation except that there is no accompanying GPDISP_LO16
710
relocation.
711
@end deffn
712
@deffn {} BFD_RELOC_ALPHA_LITERAL
713
@deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL
714
@deffnx {} BFD_RELOC_ALPHA_LITUSE
715
The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
716
the assembler turns it into a LDQ instruction to load the address of
717
the symbol, and then fills in a register in the real instruction.
718
 
719
The LITERAL reloc, at the LDQ instruction, refers to the .lita
720
section symbol.  The addend is ignored when writing, but is filled
721
in with the file's GP value on reading, for convenience, as with the
722
GPDISP_LO16 reloc.
723
 
724
The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
725
It should refer to the symbol to be referenced, as with 16_GOTOFF,
726
but it generates output not based on the position within the .got
727
section, but relative to the GP value chosen for the file during the
728
final link stage.
729
 
730
The LITUSE reloc, on the instruction using the loaded address, gives
731
information to the linker that it might be able to use to optimize
732
away some literal section references.  The symbol is ignored (read
733
as the absolute section symbol), and the "addend" indicates the type
734
of instruction using the register:
735
1 - "memory" fmt insn
736
2 - byte-manipulation (byte offset reg)
737
3 - jsr (target of branch)
738
@end deffn
739
@deffn {} BFD_RELOC_ALPHA_HINT
740
The HINT relocation indicates a value that should be filled into the
741
"hint" field of a jmp/jsr/ret instruction, for possible branch-
742
prediction logic which may be provided on some processors.
743
@end deffn
744
@deffn {} BFD_RELOC_ALPHA_LINKAGE
745
The LINKAGE relocation outputs a linkage pair in the object file,
746
which is filled by the linker.
747
@end deffn
748
@deffn {} BFD_RELOC_ALPHA_CODEADDR
749
The CODEADDR relocation outputs a STO_CA in the object file,
750
which is filled by the linker.
751
@end deffn
752
@deffn {} BFD_RELOC_ALPHA_GPREL_HI16
753
@deffnx {} BFD_RELOC_ALPHA_GPREL_LO16
754
The GPREL_HI/LO relocations together form a 32-bit offset from the
755
GP register.
756
@end deffn
757
@deffn {} BFD_RELOC_ALPHA_BRSGP
758
Like BFD_RELOC_23_PCREL_S2, except that the source and target must
759
share a common GP, and the target address is adjusted for
760
STO_ALPHA_STD_GPLOAD.
761
@end deffn
762
@deffn {} BFD_RELOC_ALPHA_TLSGD
763
@deffnx {} BFD_RELOC_ALPHA_TLSLDM
764
@deffnx {} BFD_RELOC_ALPHA_DTPMOD64
765
@deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16
766
@deffnx {} BFD_RELOC_ALPHA_DTPREL64
767
@deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16
768
@deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16
769
@deffnx {} BFD_RELOC_ALPHA_DTPREL16
770
@deffnx {} BFD_RELOC_ALPHA_GOTTPREL16
771
@deffnx {} BFD_RELOC_ALPHA_TPREL64
772
@deffnx {} BFD_RELOC_ALPHA_TPREL_HI16
773
@deffnx {} BFD_RELOC_ALPHA_TPREL_LO16
774
@deffnx {} BFD_RELOC_ALPHA_TPREL16
775
Alpha thread-local storage relocations.
776
@end deffn
777
@deffn {} BFD_RELOC_MIPS_JMP
778
Bits 27..2 of the relocation address shifted right 2 bits;
779
simple reloc otherwise.
780
@end deffn
781
@deffn {} BFD_RELOC_MIPS16_JMP
782
The MIPS16 jump instruction.
783
@end deffn
784
@deffn {} BFD_RELOC_MIPS16_GPREL
785
MIPS16 GP relative reloc.
786
@end deffn
787
@deffn {} BFD_RELOC_HI16
788
High 16 bits of 32-bit value; simple reloc.
789
@end deffn
790
@deffn {} BFD_RELOC_HI16_S
791
High 16 bits of 32-bit value but the low 16 bits will be sign
792
extended and added to form the final result.  If the low 16
793
bits form a negative number, we need to add one to the high value
794
to compensate for the borrow when the low bits are added.
795
@end deffn
796
@deffn {} BFD_RELOC_LO16
797
Low 16 bits.
798
@end deffn
799
@deffn {} BFD_RELOC_HI16_PCREL
800
High 16 bits of 32-bit pc-relative value
801
@end deffn
802
@deffn {} BFD_RELOC_HI16_S_PCREL
803
High 16 bits of 32-bit pc-relative value, adjusted
804
@end deffn
805
@deffn {} BFD_RELOC_LO16_PCREL
806
Low 16 bits of pc-relative value
807
@end deffn
808
@deffn {} BFD_RELOC_MIPS16_HI16
809
MIPS16 high 16 bits of 32-bit value.
810
@end deffn
811
@deffn {} BFD_RELOC_MIPS16_HI16_S
812
MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
813
extended and added to form the final result.  If the low 16
814
bits form a negative number, we need to add one to the high value
815
to compensate for the borrow when the low bits are added.
816
@end deffn
817
@deffn {} BFD_RELOC_MIPS16_LO16
818
MIPS16 low 16 bits.
819
@end deffn
820
@deffn {} BFD_RELOC_MIPS_LITERAL
821
Relocation against a MIPS literal section.
822
@end deffn
823
@deffn {} BFD_RELOC_MIPS_GOT16
824
@deffnx {} BFD_RELOC_MIPS_CALL16
825
@deffnx {} BFD_RELOC_MIPS_GOT_HI16
826
@deffnx {} BFD_RELOC_MIPS_GOT_LO16
827
@deffnx {} BFD_RELOC_MIPS_CALL_HI16
828
@deffnx {} BFD_RELOC_MIPS_CALL_LO16
829
@deffnx {} BFD_RELOC_MIPS_SUB
830
@deffnx {} BFD_RELOC_MIPS_GOT_PAGE
831
@deffnx {} BFD_RELOC_MIPS_GOT_OFST
832
@deffnx {} BFD_RELOC_MIPS_GOT_DISP
833
@deffnx {} BFD_RELOC_MIPS_SHIFT5
834
@deffnx {} BFD_RELOC_MIPS_SHIFT6
835
@deffnx {} BFD_RELOC_MIPS_INSERT_A
836
@deffnx {} BFD_RELOC_MIPS_INSERT_B
837
@deffnx {} BFD_RELOC_MIPS_DELETE
838
@deffnx {} BFD_RELOC_MIPS_HIGHEST
839
@deffnx {} BFD_RELOC_MIPS_HIGHER
840
@deffnx {} BFD_RELOC_MIPS_SCN_DISP
841
@deffnx {} BFD_RELOC_MIPS_REL16
842
@deffnx {} BFD_RELOC_MIPS_RELGOT
843
@deffnx {} BFD_RELOC_MIPS_JALR
844
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32
845
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32
846
@deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64
847
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64
848
@deffnx {} BFD_RELOC_MIPS_TLS_GD
849
@deffnx {} BFD_RELOC_MIPS_TLS_LDM
850
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16
851
@deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16
852
@deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL
853
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL32
854
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL64
855
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16
856
@deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16
857
MIPS ELF relocations.
858
@end deffn
859
@deffn {} BFD_RELOC_MIPS_COPY
860
@deffnx {} BFD_RELOC_MIPS_JUMP_SLOT
861
MIPS ELF relocations (VxWorks extensions).
862
@end deffn
863
@deffn {} BFD_RELOC_FRV_LABEL16
864
@deffnx {} BFD_RELOC_FRV_LABEL24
865
@deffnx {} BFD_RELOC_FRV_LO16
866
@deffnx {} BFD_RELOC_FRV_HI16
867
@deffnx {} BFD_RELOC_FRV_GPREL12
868
@deffnx {} BFD_RELOC_FRV_GPRELU12
869
@deffnx {} BFD_RELOC_FRV_GPREL32
870
@deffnx {} BFD_RELOC_FRV_GPRELHI
871
@deffnx {} BFD_RELOC_FRV_GPRELLO
872
@deffnx {} BFD_RELOC_FRV_GOT12
873
@deffnx {} BFD_RELOC_FRV_GOTHI
874
@deffnx {} BFD_RELOC_FRV_GOTLO
875
@deffnx {} BFD_RELOC_FRV_FUNCDESC
876
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12
877
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI
878
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO
879
@deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE
880
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12
881
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
882
@deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
883
@deffnx {} BFD_RELOC_FRV_GOTOFF12
884
@deffnx {} BFD_RELOC_FRV_GOTOFFHI
885
@deffnx {} BFD_RELOC_FRV_GOTOFFLO
886
@deffnx {} BFD_RELOC_FRV_GETTLSOFF
887
@deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE
888
@deffnx {} BFD_RELOC_FRV_GOTTLSDESC12
889
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI
890
@deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO
891
@deffnx {} BFD_RELOC_FRV_TLSMOFF12
892
@deffnx {} BFD_RELOC_FRV_TLSMOFFHI
893
@deffnx {} BFD_RELOC_FRV_TLSMOFFLO
894
@deffnx {} BFD_RELOC_FRV_GOTTLSOFF12
895
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI
896
@deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO
897
@deffnx {} BFD_RELOC_FRV_TLSOFF
898
@deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX
899
@deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX
900
@deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX
901
@deffnx {} BFD_RELOC_FRV_TLSMOFF
902
Fujitsu Frv Relocations.
903
@end deffn
904
@deffn {} BFD_RELOC_MN10300_GOTOFF24
905
This is a 24bit GOT-relative reloc for the mn10300.
906
@end deffn
907
@deffn {} BFD_RELOC_MN10300_GOT32
908
This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
909
in the instruction.
910
@end deffn
911
@deffn {} BFD_RELOC_MN10300_GOT24
912
This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
913
in the instruction.
914
@end deffn
915
@deffn {} BFD_RELOC_MN10300_GOT16
916
This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
917
in the instruction.
918
@end deffn
919
@deffn {} BFD_RELOC_MN10300_COPY
920
Copy symbol at runtime.
921
@end deffn
922
@deffn {} BFD_RELOC_MN10300_GLOB_DAT
923
Create GOT entry.
924
@end deffn
925
@deffn {} BFD_RELOC_MN10300_JMP_SLOT
926
Create PLT entry.
927
@end deffn
928
@deffn {} BFD_RELOC_MN10300_RELATIVE
929
Adjust by program base.
930
@end deffn
931
@deffn {} BFD_RELOC_MN10300_SYM_DIFF
932
Together with another reloc targeted at the same location,
933
allows for a value that is the difference of two symbols
934
in the same section.
935
@end deffn
936
@deffn {} BFD_RELOC_MN10300_ALIGN
937
The addend of this reloc is an alignment power that must
938
be honoured at the offset's location, regardless of linker
939
relaxation.
940
@end deffn
941
@deffn {} BFD_RELOC_386_GOT32
942
@deffnx {} BFD_RELOC_386_PLT32
943
@deffnx {} BFD_RELOC_386_COPY
944
@deffnx {} BFD_RELOC_386_GLOB_DAT
945
@deffnx {} BFD_RELOC_386_JUMP_SLOT
946
@deffnx {} BFD_RELOC_386_RELATIVE
947
@deffnx {} BFD_RELOC_386_GOTOFF
948
@deffnx {} BFD_RELOC_386_GOTPC
949
@deffnx {} BFD_RELOC_386_TLS_TPOFF
950
@deffnx {} BFD_RELOC_386_TLS_IE
951
@deffnx {} BFD_RELOC_386_TLS_GOTIE
952
@deffnx {} BFD_RELOC_386_TLS_LE
953
@deffnx {} BFD_RELOC_386_TLS_GD
954
@deffnx {} BFD_RELOC_386_TLS_LDM
955
@deffnx {} BFD_RELOC_386_TLS_LDO_32
956
@deffnx {} BFD_RELOC_386_TLS_IE_32
957
@deffnx {} BFD_RELOC_386_TLS_LE_32
958
@deffnx {} BFD_RELOC_386_TLS_DTPMOD32
959
@deffnx {} BFD_RELOC_386_TLS_DTPOFF32
960
@deffnx {} BFD_RELOC_386_TLS_TPOFF32
961
@deffnx {} BFD_RELOC_386_TLS_GOTDESC
962
@deffnx {} BFD_RELOC_386_TLS_DESC_CALL
963
@deffnx {} BFD_RELOC_386_TLS_DESC
964
i386/elf relocations
965
@end deffn
966
@deffn {} BFD_RELOC_X86_64_GOT32
967
@deffnx {} BFD_RELOC_X86_64_PLT32
968
@deffnx {} BFD_RELOC_X86_64_COPY
969
@deffnx {} BFD_RELOC_X86_64_GLOB_DAT
970
@deffnx {} BFD_RELOC_X86_64_JUMP_SLOT
971
@deffnx {} BFD_RELOC_X86_64_RELATIVE
972
@deffnx {} BFD_RELOC_X86_64_GOTPCREL
973
@deffnx {} BFD_RELOC_X86_64_32S
974
@deffnx {} BFD_RELOC_X86_64_DTPMOD64
975
@deffnx {} BFD_RELOC_X86_64_DTPOFF64
976
@deffnx {} BFD_RELOC_X86_64_TPOFF64
977
@deffnx {} BFD_RELOC_X86_64_TLSGD
978
@deffnx {} BFD_RELOC_X86_64_TLSLD
979
@deffnx {} BFD_RELOC_X86_64_DTPOFF32
980
@deffnx {} BFD_RELOC_X86_64_GOTTPOFF
981
@deffnx {} BFD_RELOC_X86_64_TPOFF32
982
@deffnx {} BFD_RELOC_X86_64_GOTOFF64
983
@deffnx {} BFD_RELOC_X86_64_GOTPC32
984
@deffnx {} BFD_RELOC_X86_64_GOT64
985
@deffnx {} BFD_RELOC_X86_64_GOTPCREL64
986
@deffnx {} BFD_RELOC_X86_64_GOTPC64
987
@deffnx {} BFD_RELOC_X86_64_GOTPLT64
988
@deffnx {} BFD_RELOC_X86_64_PLTOFF64
989
@deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC
990
@deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL
991
@deffnx {} BFD_RELOC_X86_64_TLSDESC
992
x86-64/elf relocations
993
@end deffn
994
@deffn {} BFD_RELOC_NS32K_IMM_8
995
@deffnx {} BFD_RELOC_NS32K_IMM_16
996
@deffnx {} BFD_RELOC_NS32K_IMM_32
997
@deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL
998
@deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL
999
@deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL
1000
@deffnx {} BFD_RELOC_NS32K_DISP_8
1001
@deffnx {} BFD_RELOC_NS32K_DISP_16
1002
@deffnx {} BFD_RELOC_NS32K_DISP_32
1003
@deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL
1004
@deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL
1005
@deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL
1006
ns32k relocations
1007
@end deffn
1008
@deffn {} BFD_RELOC_PDP11_DISP_8_PCREL
1009
@deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL
1010
PDP11 relocations
1011
@end deffn
1012
@deffn {} BFD_RELOC_PJ_CODE_HI16
1013
@deffnx {} BFD_RELOC_PJ_CODE_LO16
1014
@deffnx {} BFD_RELOC_PJ_CODE_DIR16
1015
@deffnx {} BFD_RELOC_PJ_CODE_DIR32
1016
@deffnx {} BFD_RELOC_PJ_CODE_REL16
1017
@deffnx {} BFD_RELOC_PJ_CODE_REL32
1018
Picojava relocs.  Not all of these appear in object files.
1019
@end deffn
1020
@deffn {} BFD_RELOC_PPC_B26
1021
@deffnx {} BFD_RELOC_PPC_BA26
1022
@deffnx {} BFD_RELOC_PPC_TOC16
1023
@deffnx {} BFD_RELOC_PPC_B16
1024
@deffnx {} BFD_RELOC_PPC_B16_BRTAKEN
1025
@deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN
1026
@deffnx {} BFD_RELOC_PPC_BA16
1027
@deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN
1028
@deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN
1029
@deffnx {} BFD_RELOC_PPC_COPY
1030
@deffnx {} BFD_RELOC_PPC_GLOB_DAT
1031
@deffnx {} BFD_RELOC_PPC_JMP_SLOT
1032
@deffnx {} BFD_RELOC_PPC_RELATIVE
1033
@deffnx {} BFD_RELOC_PPC_LOCAL24PC
1034
@deffnx {} BFD_RELOC_PPC_EMB_NADDR32
1035
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16
1036
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO
1037
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI
1038
@deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA
1039
@deffnx {} BFD_RELOC_PPC_EMB_SDAI16
1040
@deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
1041
@deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
1042
@deffnx {} BFD_RELOC_PPC_EMB_SDA21
1043
@deffnx {} BFD_RELOC_PPC_EMB_MRKREF
1044
@deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
1045
@deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
1046
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
1047
@deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
1048
@deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
1049
@deffnx {} BFD_RELOC_PPC_EMB_RELSDA
1050
@deffnx {} BFD_RELOC_PPC64_HIGHER
1051
@deffnx {} BFD_RELOC_PPC64_HIGHER_S
1052
@deffnx {} BFD_RELOC_PPC64_HIGHEST
1053
@deffnx {} BFD_RELOC_PPC64_HIGHEST_S
1054
@deffnx {} BFD_RELOC_PPC64_TOC16_LO
1055
@deffnx {} BFD_RELOC_PPC64_TOC16_HI
1056
@deffnx {} BFD_RELOC_PPC64_TOC16_HA
1057
@deffnx {} BFD_RELOC_PPC64_TOC
1058
@deffnx {} BFD_RELOC_PPC64_PLTGOT16
1059
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
1060
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI
1061
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA
1062
@deffnx {} BFD_RELOC_PPC64_ADDR16_DS
1063
@deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS
1064
@deffnx {} BFD_RELOC_PPC64_GOT16_DS
1065
@deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS
1066
@deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS
1067
@deffnx {} BFD_RELOC_PPC64_SECTOFF_DS
1068
@deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS
1069
@deffnx {} BFD_RELOC_PPC64_TOC16_DS
1070
@deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS
1071
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS
1072
@deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS
1073
Power(rs6000) and PowerPC relocations.
1074
@end deffn
1075
@deffn {} BFD_RELOC_PPC_TLS
1076
@deffnx {} BFD_RELOC_PPC_DTPMOD
1077
@deffnx {} BFD_RELOC_PPC_TPREL16
1078
@deffnx {} BFD_RELOC_PPC_TPREL16_LO
1079
@deffnx {} BFD_RELOC_PPC_TPREL16_HI
1080
@deffnx {} BFD_RELOC_PPC_TPREL16_HA
1081
@deffnx {} BFD_RELOC_PPC_TPREL
1082
@deffnx {} BFD_RELOC_PPC_DTPREL16
1083
@deffnx {} BFD_RELOC_PPC_DTPREL16_LO
1084
@deffnx {} BFD_RELOC_PPC_DTPREL16_HI
1085
@deffnx {} BFD_RELOC_PPC_DTPREL16_HA
1086
@deffnx {} BFD_RELOC_PPC_DTPREL
1087
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16
1088
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO
1089
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI
1090
@deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA
1091
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16
1092
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO
1093
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI
1094
@deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA
1095
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16
1096
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO
1097
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI
1098
@deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA
1099
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16
1100
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO
1101
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI
1102
@deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA
1103
@deffnx {} BFD_RELOC_PPC64_TPREL16_DS
1104
@deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS
1105
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER
1106
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA
1107
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST
1108
@deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA
1109
@deffnx {} BFD_RELOC_PPC64_DTPREL16_DS
1110
@deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS
1111
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER
1112
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA
1113
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST
1114
@deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA
1115
PowerPC and PowerPC64 thread-local storage relocations.
1116
@end deffn
1117
@deffn {} BFD_RELOC_I370_D12
1118
IBM 370/390 relocations
1119
@end deffn
1120
@deffn {} BFD_RELOC_CTOR
1121
The type of reloc used to build a constructor table - at the moment
1122
probably a 32 bit wide absolute relocation, but the target can choose.
1123
It generally does map to one of the other relocation types.
1124
@end deffn
1125
@deffn {} BFD_RELOC_ARM_PCREL_BRANCH
1126
ARM 26 bit pc-relative branch.  The lowest two bits must be zero and are
1127
not stored in the instruction.
1128
@end deffn
1129
@deffn {} BFD_RELOC_ARM_PCREL_BLX
1130
ARM 26 bit pc-relative branch.  The lowest bit must be zero and is
1131
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1132
field in the instruction.
1133
@end deffn
1134
@deffn {} BFD_RELOC_THUMB_PCREL_BLX
1135
Thumb 22 bit pc-relative branch.  The lowest bit must be zero and is
1136
not stored in the instruction.  The 2nd lowest bit comes from a 1 bit
1137
field in the instruction.
1138
@end deffn
1139
@deffn {} BFD_RELOC_ARM_PCREL_CALL
1140
ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
1141
@end deffn
1142
@deffn {} BFD_RELOC_ARM_PCREL_JUMP
1143
ARM 26-bit pc-relative branch for B or conditional BL instruction.
1144
@end deffn
1145
@deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7
1146
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9
1147
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12
1148
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20
1149
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23
1150
@deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25
1151
Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
1152
The lowest bit must be zero and is not stored in the instruction.
1153
Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
1154
"nn" one smaller in all cases.  Note further that BRANCH23
1155
corresponds to R_ARM_THM_CALL.
1156
@end deffn
1157
@deffn {} BFD_RELOC_ARM_OFFSET_IMM
1158
12-bit immediate offset, used in ARM-format ldr and str instructions.
1159
@end deffn
1160
@deffn {} BFD_RELOC_ARM_THUMB_OFFSET
1161
5-bit immediate offset, used in Thumb-format ldr and str instructions.
1162
@end deffn
1163
@deffn {} BFD_RELOC_ARM_TARGET1
1164
Pc-relative or absolute relocation depending on target.  Used for
1165
entries in .init_array sections.
1166
@end deffn
1167
@deffn {} BFD_RELOC_ARM_ROSEGREL32
1168
Read-only segment base relative address.
1169
@end deffn
1170
@deffn {} BFD_RELOC_ARM_SBREL32
1171
Data segment base relative address.
1172
@end deffn
1173
@deffn {} BFD_RELOC_ARM_TARGET2
1174
This reloc is used for references to RTTI data from exception handling
1175
tables.  The actual definition depends on the target.  It may be a
1176
pc-relative or some form of GOT-indirect relocation.
1177
@end deffn
1178
@deffn {} BFD_RELOC_ARM_PREL31
1179
31-bit PC relative address.
1180
@end deffn
1181
@deffn {} BFD_RELOC_ARM_MOVW
1182
@deffnx {} BFD_RELOC_ARM_MOVT
1183
@deffnx {} BFD_RELOC_ARM_MOVW_PCREL
1184
@deffnx {} BFD_RELOC_ARM_MOVT_PCREL
1185
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW
1186
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT
1187
@deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL
1188
@deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL
1189
Low and High halfword relocations for MOVW and MOVT instructions.
1190
@end deffn
1191
@deffn {} BFD_RELOC_ARM_JUMP_SLOT
1192
@deffnx {} BFD_RELOC_ARM_GLOB_DAT
1193
@deffnx {} BFD_RELOC_ARM_GOT32
1194
@deffnx {} BFD_RELOC_ARM_PLT32
1195
@deffnx {} BFD_RELOC_ARM_RELATIVE
1196
@deffnx {} BFD_RELOC_ARM_GOTOFF
1197
@deffnx {} BFD_RELOC_ARM_GOTPC
1198
Relocations for setting up GOTs and PLTs for shared libraries.
1199
@end deffn
1200
@deffn {} BFD_RELOC_ARM_TLS_GD32
1201
@deffnx {} BFD_RELOC_ARM_TLS_LDO32
1202
@deffnx {} BFD_RELOC_ARM_TLS_LDM32
1203
@deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32
1204
@deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32
1205
@deffnx {} BFD_RELOC_ARM_TLS_TPOFF32
1206
@deffnx {} BFD_RELOC_ARM_TLS_IE32
1207
@deffnx {} BFD_RELOC_ARM_TLS_LE32
1208
ARM thread-local storage relocations.
1209
@end deffn
1210
@deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC
1211
@deffnx {} BFD_RELOC_ARM_ALU_PC_G0
1212
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC
1213
@deffnx {} BFD_RELOC_ARM_ALU_PC_G1
1214
@deffnx {} BFD_RELOC_ARM_ALU_PC_G2
1215
@deffnx {} BFD_RELOC_ARM_LDR_PC_G0
1216
@deffnx {} BFD_RELOC_ARM_LDR_PC_G1
1217
@deffnx {} BFD_RELOC_ARM_LDR_PC_G2
1218
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G0
1219
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G1
1220
@deffnx {} BFD_RELOC_ARM_LDRS_PC_G2
1221
@deffnx {} BFD_RELOC_ARM_LDC_PC_G0
1222
@deffnx {} BFD_RELOC_ARM_LDC_PC_G1
1223
@deffnx {} BFD_RELOC_ARM_LDC_PC_G2
1224
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC
1225
@deffnx {} BFD_RELOC_ARM_ALU_SB_G0
1226
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC
1227
@deffnx {} BFD_RELOC_ARM_ALU_SB_G1
1228
@deffnx {} BFD_RELOC_ARM_ALU_SB_G2
1229
@deffnx {} BFD_RELOC_ARM_LDR_SB_G0
1230
@deffnx {} BFD_RELOC_ARM_LDR_SB_G1
1231
@deffnx {} BFD_RELOC_ARM_LDR_SB_G2
1232
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G0
1233
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G1
1234
@deffnx {} BFD_RELOC_ARM_LDRS_SB_G2
1235
@deffnx {} BFD_RELOC_ARM_LDC_SB_G0
1236
@deffnx {} BFD_RELOC_ARM_LDC_SB_G1
1237
@deffnx {} BFD_RELOC_ARM_LDC_SB_G2
1238
ARM group relocations.
1239
@end deffn
1240
@deffn {} BFD_RELOC_ARM_V4BX
1241
Annotation of BX instructions.
1242
@end deffn
1243
@deffn {} BFD_RELOC_ARM_IMMEDIATE
1244
@deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE
1245
@deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE
1246
@deffnx {} BFD_RELOC_ARM_T32_ADD_IMM
1247
@deffnx {} BFD_RELOC_ARM_T32_IMM12
1248
@deffnx {} BFD_RELOC_ARM_T32_ADD_PC12
1249
@deffnx {} BFD_RELOC_ARM_SHIFT_IMM
1250
@deffnx {} BFD_RELOC_ARM_SMC
1251
@deffnx {} BFD_RELOC_ARM_SWI
1252
@deffnx {} BFD_RELOC_ARM_MULTI
1253
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM
1254
@deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2
1255
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM
1256
@deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
1257
@deffnx {} BFD_RELOC_ARM_ADR_IMM
1258
@deffnx {} BFD_RELOC_ARM_LDR_IMM
1259
@deffnx {} BFD_RELOC_ARM_LITERAL
1260
@deffnx {} BFD_RELOC_ARM_IN_POOL
1261
@deffnx {} BFD_RELOC_ARM_OFFSET_IMM8
1262
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8
1263
@deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM
1264
@deffnx {} BFD_RELOC_ARM_HWLITERAL
1265
@deffnx {} BFD_RELOC_ARM_THUMB_ADD
1266
@deffnx {} BFD_RELOC_ARM_THUMB_IMM
1267
@deffnx {} BFD_RELOC_ARM_THUMB_SHIFT
1268
These relocs are only used within the ARM assembler.  They are not
1269
(at present) written to any object files.
1270
@end deffn
1271
@deffn {} BFD_RELOC_SH_PCDISP8BY2
1272
@deffnx {} BFD_RELOC_SH_PCDISP12BY2
1273
@deffnx {} BFD_RELOC_SH_IMM3
1274
@deffnx {} BFD_RELOC_SH_IMM3U
1275
@deffnx {} BFD_RELOC_SH_DISP12
1276
@deffnx {} BFD_RELOC_SH_DISP12BY2
1277
@deffnx {} BFD_RELOC_SH_DISP12BY4
1278
@deffnx {} BFD_RELOC_SH_DISP12BY8
1279
@deffnx {} BFD_RELOC_SH_DISP20
1280
@deffnx {} BFD_RELOC_SH_DISP20BY8
1281
@deffnx {} BFD_RELOC_SH_IMM4
1282
@deffnx {} BFD_RELOC_SH_IMM4BY2
1283
@deffnx {} BFD_RELOC_SH_IMM4BY4
1284
@deffnx {} BFD_RELOC_SH_IMM8
1285
@deffnx {} BFD_RELOC_SH_IMM8BY2
1286
@deffnx {} BFD_RELOC_SH_IMM8BY4
1287
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY2
1288
@deffnx {} BFD_RELOC_SH_PCRELIMM8BY4
1289
@deffnx {} BFD_RELOC_SH_SWITCH16
1290
@deffnx {} BFD_RELOC_SH_SWITCH32
1291
@deffnx {} BFD_RELOC_SH_USES
1292
@deffnx {} BFD_RELOC_SH_COUNT
1293
@deffnx {} BFD_RELOC_SH_ALIGN
1294
@deffnx {} BFD_RELOC_SH_CODE
1295
@deffnx {} BFD_RELOC_SH_DATA
1296
@deffnx {} BFD_RELOC_SH_LABEL
1297
@deffnx {} BFD_RELOC_SH_LOOP_START
1298
@deffnx {} BFD_RELOC_SH_LOOP_END
1299
@deffnx {} BFD_RELOC_SH_COPY
1300
@deffnx {} BFD_RELOC_SH_GLOB_DAT
1301
@deffnx {} BFD_RELOC_SH_JMP_SLOT
1302
@deffnx {} BFD_RELOC_SH_RELATIVE
1303
@deffnx {} BFD_RELOC_SH_GOTPC
1304
@deffnx {} BFD_RELOC_SH_GOT_LOW16
1305
@deffnx {} BFD_RELOC_SH_GOT_MEDLOW16
1306
@deffnx {} BFD_RELOC_SH_GOT_MEDHI16
1307
@deffnx {} BFD_RELOC_SH_GOT_HI16
1308
@deffnx {} BFD_RELOC_SH_GOTPLT_LOW16
1309
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16
1310
@deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16
1311
@deffnx {} BFD_RELOC_SH_GOTPLT_HI16
1312
@deffnx {} BFD_RELOC_SH_PLT_LOW16
1313
@deffnx {} BFD_RELOC_SH_PLT_MEDLOW16
1314
@deffnx {} BFD_RELOC_SH_PLT_MEDHI16
1315
@deffnx {} BFD_RELOC_SH_PLT_HI16
1316
@deffnx {} BFD_RELOC_SH_GOTOFF_LOW16
1317
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16
1318
@deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16
1319
@deffnx {} BFD_RELOC_SH_GOTOFF_HI16
1320
@deffnx {} BFD_RELOC_SH_GOTPC_LOW16
1321
@deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16
1322
@deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16
1323
@deffnx {} BFD_RELOC_SH_GOTPC_HI16
1324
@deffnx {} BFD_RELOC_SH_COPY64
1325
@deffnx {} BFD_RELOC_SH_GLOB_DAT64
1326
@deffnx {} BFD_RELOC_SH_JMP_SLOT64
1327
@deffnx {} BFD_RELOC_SH_RELATIVE64
1328
@deffnx {} BFD_RELOC_SH_GOT10BY4
1329
@deffnx {} BFD_RELOC_SH_GOT10BY8
1330
@deffnx {} BFD_RELOC_SH_GOTPLT10BY4
1331
@deffnx {} BFD_RELOC_SH_GOTPLT10BY8
1332
@deffnx {} BFD_RELOC_SH_GOTPLT32
1333
@deffnx {} BFD_RELOC_SH_SHMEDIA_CODE
1334
@deffnx {} BFD_RELOC_SH_IMMU5
1335
@deffnx {} BFD_RELOC_SH_IMMS6
1336
@deffnx {} BFD_RELOC_SH_IMMS6BY32
1337
@deffnx {} BFD_RELOC_SH_IMMU6
1338
@deffnx {} BFD_RELOC_SH_IMMS10
1339
@deffnx {} BFD_RELOC_SH_IMMS10BY2
1340
@deffnx {} BFD_RELOC_SH_IMMS10BY4
1341
@deffnx {} BFD_RELOC_SH_IMMS10BY8
1342
@deffnx {} BFD_RELOC_SH_IMMS16
1343
@deffnx {} BFD_RELOC_SH_IMMU16
1344
@deffnx {} BFD_RELOC_SH_IMM_LOW16
1345
@deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL
1346
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16
1347
@deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL
1348
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16
1349
@deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL
1350
@deffnx {} BFD_RELOC_SH_IMM_HI16
1351
@deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL
1352
@deffnx {} BFD_RELOC_SH_PT_16
1353
@deffnx {} BFD_RELOC_SH_TLS_GD_32
1354
@deffnx {} BFD_RELOC_SH_TLS_LD_32
1355
@deffnx {} BFD_RELOC_SH_TLS_LDO_32
1356
@deffnx {} BFD_RELOC_SH_TLS_IE_32
1357
@deffnx {} BFD_RELOC_SH_TLS_LE_32
1358
@deffnx {} BFD_RELOC_SH_TLS_DTPMOD32
1359
@deffnx {} BFD_RELOC_SH_TLS_DTPOFF32
1360
@deffnx {} BFD_RELOC_SH_TLS_TPOFF32
1361
Renesas / SuperH SH relocs.  Not all of these appear in object files.
1362
@end deffn
1363
@deffn {} BFD_RELOC_ARC_B22_PCREL
1364
ARC Cores relocs.
1365
ARC 22 bit pc-relative branch.  The lowest two bits must be zero and are
1366
not stored in the instruction.  The high 20 bits are installed in bits 26
1367
through 7 of the instruction.
1368
@end deffn
1369
@deffn {} BFD_RELOC_ARC_B26
1370
ARC 26 bit absolute branch.  The lowest two bits must be zero and are not
1371
stored in the instruction.  The high 24 bits are installed in bits 23
1372
through 0.
1373
@end deffn
1374
@deffn {} BFD_RELOC_BFIN_16_IMM
1375
ADI Blackfin 16 bit immediate absolute reloc.
1376
@end deffn
1377
@deffn {} BFD_RELOC_BFIN_16_HIGH
1378
ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
1379
@end deffn
1380
@deffn {} BFD_RELOC_BFIN_4_PCREL
1381
ADI Blackfin 'a' part of LSETUP.
1382
@end deffn
1383
@deffn {} BFD_RELOC_BFIN_5_PCREL
1384
ADI Blackfin.
1385
@end deffn
1386
@deffn {} BFD_RELOC_BFIN_16_LOW
1387
ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
1388
@end deffn
1389
@deffn {} BFD_RELOC_BFIN_10_PCREL
1390
ADI Blackfin.
1391
@end deffn
1392
@deffn {} BFD_RELOC_BFIN_11_PCREL
1393
ADI Blackfin 'b' part of LSETUP.
1394
@end deffn
1395
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP
1396
ADI Blackfin.
1397
@end deffn
1398
@deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S
1399
ADI Blackfin Short jump, pcrel.
1400
@end deffn
1401
@deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X
1402
ADI Blackfin Call.x not implemented.
1403
@end deffn
1404
@deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L
1405
ADI Blackfin Long Jump pcrel.
1406
@end deffn
1407
@deffn {} BFD_RELOC_BFIN_GOT17M4
1408
@deffnx {} BFD_RELOC_BFIN_GOTHI
1409
@deffnx {} BFD_RELOC_BFIN_GOTLO
1410
@deffnx {} BFD_RELOC_BFIN_FUNCDESC
1411
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4
1412
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI
1413
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO
1414
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE
1415
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
1416
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
1417
@deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
1418
@deffnx {} BFD_RELOC_BFIN_GOTOFF17M4
1419
@deffnx {} BFD_RELOC_BFIN_GOTOFFHI
1420
@deffnx {} BFD_RELOC_BFIN_GOTOFFLO
1421
ADI Blackfin FD-PIC relocations.
1422
@end deffn
1423
@deffn {} BFD_RELOC_BFIN_GOT
1424
ADI Blackfin GOT relocation.
1425
@end deffn
1426
@deffn {} BFD_RELOC_BFIN_PLTPC
1427
ADI Blackfin PLTPC relocation.
1428
@end deffn
1429
@deffn {} BFD_ARELOC_BFIN_PUSH
1430
ADI Blackfin arithmetic relocation.
1431
@end deffn
1432
@deffn {} BFD_ARELOC_BFIN_CONST
1433
ADI Blackfin arithmetic relocation.
1434
@end deffn
1435
@deffn {} BFD_ARELOC_BFIN_ADD
1436
ADI Blackfin arithmetic relocation.
1437
@end deffn
1438
@deffn {} BFD_ARELOC_BFIN_SUB
1439
ADI Blackfin arithmetic relocation.
1440
@end deffn
1441
@deffn {} BFD_ARELOC_BFIN_MULT
1442
ADI Blackfin arithmetic relocation.
1443
@end deffn
1444
@deffn {} BFD_ARELOC_BFIN_DIV
1445
ADI Blackfin arithmetic relocation.
1446
@end deffn
1447
@deffn {} BFD_ARELOC_BFIN_MOD
1448
ADI Blackfin arithmetic relocation.
1449
@end deffn
1450
@deffn {} BFD_ARELOC_BFIN_LSHIFT
1451
ADI Blackfin arithmetic relocation.
1452
@end deffn
1453
@deffn {} BFD_ARELOC_BFIN_RSHIFT
1454
ADI Blackfin arithmetic relocation.
1455
@end deffn
1456
@deffn {} BFD_ARELOC_BFIN_AND
1457
ADI Blackfin arithmetic relocation.
1458
@end deffn
1459
@deffn {} BFD_ARELOC_BFIN_OR
1460
ADI Blackfin arithmetic relocation.
1461
@end deffn
1462
@deffn {} BFD_ARELOC_BFIN_XOR
1463
ADI Blackfin arithmetic relocation.
1464
@end deffn
1465
@deffn {} BFD_ARELOC_BFIN_LAND
1466
ADI Blackfin arithmetic relocation.
1467
@end deffn
1468
@deffn {} BFD_ARELOC_BFIN_LOR
1469
ADI Blackfin arithmetic relocation.
1470
@end deffn
1471
@deffn {} BFD_ARELOC_BFIN_LEN
1472
ADI Blackfin arithmetic relocation.
1473
@end deffn
1474
@deffn {} BFD_ARELOC_BFIN_NEG
1475
ADI Blackfin arithmetic relocation.
1476
@end deffn
1477
@deffn {} BFD_ARELOC_BFIN_COMP
1478
ADI Blackfin arithmetic relocation.
1479
@end deffn
1480
@deffn {} BFD_ARELOC_BFIN_PAGE
1481
ADI Blackfin arithmetic relocation.
1482
@end deffn
1483
@deffn {} BFD_ARELOC_BFIN_HWPAGE
1484
ADI Blackfin arithmetic relocation.
1485
@end deffn
1486
@deffn {} BFD_ARELOC_BFIN_ADDR
1487
ADI Blackfin arithmetic relocation.
1488
@end deffn
1489
@deffn {} BFD_RELOC_D10V_10_PCREL_R
1490
Mitsubishi D10V relocs.
1491
This is a 10-bit reloc with the right 2 bits
1492
assumed to be 0.
1493
@end deffn
1494
@deffn {} BFD_RELOC_D10V_10_PCREL_L
1495
Mitsubishi D10V relocs.
1496
This is a 10-bit reloc with the right 2 bits
1497
assumed to be 0.  This is the same as the previous reloc
1498
except it is in the left container, i.e.,
1499
shifted left 15 bits.
1500
@end deffn
1501
@deffn {} BFD_RELOC_D10V_18
1502
This is an 18-bit reloc with the right 2 bits
1503
assumed to be 0.
1504
@end deffn
1505
@deffn {} BFD_RELOC_D10V_18_PCREL
1506
This is an 18-bit reloc with the right 2 bits
1507
assumed to be 0.
1508
@end deffn
1509
@deffn {} BFD_RELOC_D30V_6
1510
Mitsubishi D30V relocs.
1511
This is a 6-bit absolute reloc.
1512
@end deffn
1513
@deffn {} BFD_RELOC_D30V_9_PCREL
1514
This is a 6-bit pc-relative reloc with
1515
the right 3 bits assumed to be 0.
1516
@end deffn
1517
@deffn {} BFD_RELOC_D30V_9_PCREL_R
1518
This is a 6-bit pc-relative reloc with
1519
the right 3 bits assumed to be 0. Same
1520
as the previous reloc but on the right side
1521
of the container.
1522
@end deffn
1523
@deffn {} BFD_RELOC_D30V_15
1524
This is a 12-bit absolute reloc with the
1525
right 3 bitsassumed to be 0.
1526
@end deffn
1527
@deffn {} BFD_RELOC_D30V_15_PCREL
1528
This is a 12-bit pc-relative reloc with
1529
the right 3 bits assumed to be 0.
1530
@end deffn
1531
@deffn {} BFD_RELOC_D30V_15_PCREL_R
1532
This is a 12-bit pc-relative reloc with
1533
the right 3 bits assumed to be 0. Same
1534
as the previous reloc but on the right side
1535
of the container.
1536
@end deffn
1537
@deffn {} BFD_RELOC_D30V_21
1538
This is an 18-bit absolute reloc with
1539
the right 3 bits assumed to be 0.
1540
@end deffn
1541
@deffn {} BFD_RELOC_D30V_21_PCREL
1542
This is an 18-bit pc-relative reloc with
1543
the right 3 bits assumed to be 0.
1544
@end deffn
1545
@deffn {} BFD_RELOC_D30V_21_PCREL_R
1546
This is an 18-bit pc-relative reloc with
1547
the right 3 bits assumed to be 0. Same
1548
as the previous reloc but on the right side
1549
of the container.
1550
@end deffn
1551
@deffn {} BFD_RELOC_D30V_32
1552
This is a 32-bit absolute reloc.
1553
@end deffn
1554
@deffn {} BFD_RELOC_D30V_32_PCREL
1555
This is a 32-bit pc-relative reloc.
1556
@end deffn
1557
@deffn {} BFD_RELOC_DLX_HI16_S
1558
DLX relocs
1559
@end deffn
1560
@deffn {} BFD_RELOC_DLX_LO16
1561
DLX relocs
1562
@end deffn
1563
@deffn {} BFD_RELOC_DLX_JMP26
1564
DLX relocs
1565
@end deffn
1566
@deffn {} BFD_RELOC_M32C_HI8
1567
@deffnx {} BFD_RELOC_M32C_RL_JUMP
1568
@deffnx {} BFD_RELOC_M32C_RL_1ADDR
1569
@deffnx {} BFD_RELOC_M32C_RL_2ADDR
1570
Renesas M16C/M32C Relocations.
1571
@end deffn
1572
@deffn {} BFD_RELOC_M32R_24
1573
Renesas M32R (formerly Mitsubishi M32R) relocs.
1574
This is a 24 bit absolute address.
1575
@end deffn
1576
@deffn {} BFD_RELOC_M32R_10_PCREL
1577
This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
1578
@end deffn
1579
@deffn {} BFD_RELOC_M32R_18_PCREL
1580
This is an 18-bit reloc with the right 2 bits assumed to be 0.
1581
@end deffn
1582
@deffn {} BFD_RELOC_M32R_26_PCREL
1583
This is a 26-bit reloc with the right 2 bits assumed to be 0.
1584
@end deffn
1585
@deffn {} BFD_RELOC_M32R_HI16_ULO
1586
This is a 16-bit reloc containing the high 16 bits of an address
1587
used when the lower 16 bits are treated as unsigned.
1588
@end deffn
1589
@deffn {} BFD_RELOC_M32R_HI16_SLO
1590
This is a 16-bit reloc containing the high 16 bits of an address
1591
used when the lower 16 bits are treated as signed.
1592
@end deffn
1593
@deffn {} BFD_RELOC_M32R_LO16
1594
This is a 16-bit reloc containing the lower 16 bits of an address.
1595
@end deffn
1596
@deffn {} BFD_RELOC_M32R_SDA16
1597
This is a 16-bit reloc containing the small data area offset for use in
1598
add3, load, and store instructions.
1599
@end deffn
1600
@deffn {} BFD_RELOC_M32R_GOT24
1601
@deffnx {} BFD_RELOC_M32R_26_PLTREL
1602
@deffnx {} BFD_RELOC_M32R_COPY
1603
@deffnx {} BFD_RELOC_M32R_GLOB_DAT
1604
@deffnx {} BFD_RELOC_M32R_JMP_SLOT
1605
@deffnx {} BFD_RELOC_M32R_RELATIVE
1606
@deffnx {} BFD_RELOC_M32R_GOTOFF
1607
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO
1608
@deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO
1609
@deffnx {} BFD_RELOC_M32R_GOTOFF_LO
1610
@deffnx {} BFD_RELOC_M32R_GOTPC24
1611
@deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO
1612
@deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO
1613
@deffnx {} BFD_RELOC_M32R_GOT16_LO
1614
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO
1615
@deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO
1616
@deffnx {} BFD_RELOC_M32R_GOTPC_LO
1617
For PIC.
1618
@end deffn
1619
@deffn {} BFD_RELOC_V850_9_PCREL
1620
This is a 9-bit reloc
1621
@end deffn
1622
@deffn {} BFD_RELOC_V850_22_PCREL
1623
This is a 22-bit reloc
1624
@end deffn
1625
@deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET
1626
This is a 16 bit offset from the short data area pointer.
1627
@end deffn
1628
@deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET
1629
This is a 16 bit offset (of which only 15 bits are used) from the
1630
short data area pointer.
1631
@end deffn
1632
@deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET
1633
This is a 16 bit offset from the zero data area pointer.
1634
@end deffn
1635
@deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET
1636
This is a 16 bit offset (of which only 15 bits are used) from the
1637
zero data area pointer.
1638
@end deffn
1639
@deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET
1640
This is an 8 bit offset (of which only 6 bits are used) from the
1641
tiny data area pointer.
1642
@end deffn
1643
@deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET
1644
This is an 8bit offset (of which only 7 bits are used) from the tiny
1645
data area pointer.
1646
@end deffn
1647
@deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET
1648
This is a 7 bit offset from the tiny data area pointer.
1649
@end deffn
1650
@deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET
1651
This is a 16 bit offset from the tiny data area pointer.
1652
@end deffn
1653
@deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET
1654
This is a 5 bit offset (of which only 4 bits are used) from the tiny
1655
data area pointer.
1656
@end deffn
1657
@deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET
1658
This is a 4 bit offset from the tiny data area pointer.
1659
@end deffn
1660
@deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
1661
This is a 16 bit offset from the short data area pointer, with the
1662
bits placed non-contiguously in the instruction.
1663
@end deffn
1664
@deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
1665
This is a 16 bit offset from the zero data area pointer, with the
1666
bits placed non-contiguously in the instruction.
1667
@end deffn
1668
@deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET
1669
This is a 6 bit offset from the call table base pointer.
1670
@end deffn
1671
@deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET
1672
This is a 16 bit offset from the call table base pointer.
1673
@end deffn
1674
@deffn {} BFD_RELOC_V850_LONGCALL
1675
Used for relaxing indirect function calls.
1676
@end deffn
1677
@deffn {} BFD_RELOC_V850_LONGJUMP
1678
Used for relaxing indirect jumps.
1679
@end deffn
1680
@deffn {} BFD_RELOC_V850_ALIGN
1681
Used to maintain alignment whilst relaxing.
1682
@end deffn
1683
@deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET
1684
This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
1685
instructions.
1686
@end deffn
1687
@deffn {} BFD_RELOC_MN10300_32_PCREL
1688
This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
1689
instruction.
1690
@end deffn
1691
@deffn {} BFD_RELOC_MN10300_16_PCREL
1692
This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
1693
instruction.
1694
@end deffn
1695
@deffn {} BFD_RELOC_TIC30_LDP
1696
This is a 8bit DP reloc for the tms320c30, where the most
1697
significant 8 bits of a 24 bit word are placed into the least
1698
significant 8 bits of the opcode.
1699
@end deffn
1700
@deffn {} BFD_RELOC_TIC54X_PARTLS7
1701
This is a 7bit reloc for the tms320c54x, where the least
1702
significant 7 bits of a 16 bit word are placed into the least
1703
significant 7 bits of the opcode.
1704
@end deffn
1705
@deffn {} BFD_RELOC_TIC54X_PARTMS9
1706
This is a 9bit DP reloc for the tms320c54x, where the most
1707
significant 9 bits of a 16 bit word are placed into the least
1708
significant 9 bits of the opcode.
1709
@end deffn
1710
@deffn {} BFD_RELOC_TIC54X_23
1711
This is an extended address 23-bit reloc for the tms320c54x.
1712
@end deffn
1713
@deffn {} BFD_RELOC_TIC54X_16_OF_23
1714
This is a 16-bit reloc for the tms320c54x, where the least
1715
significant 16 bits of a 23-bit extended address are placed into
1716
the opcode.
1717
@end deffn
1718
@deffn {} BFD_RELOC_TIC54X_MS7_OF_23
1719
This is a reloc for the tms320c54x, where the most
1720
significant 7 bits of a 23-bit extended address are placed into
1721
the opcode.
1722
@end deffn
1723
@deffn {} BFD_RELOC_FR30_48
1724
This is a 48 bit reloc for the FR30 that stores 32 bits.
1725
@end deffn
1726
@deffn {} BFD_RELOC_FR30_20
1727
This is a 32 bit reloc for the FR30 that stores 20 bits split up into
1728
two sections.
1729
@end deffn
1730
@deffn {} BFD_RELOC_FR30_6_IN_4
1731
This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
1732
4 bits.
1733
@end deffn
1734
@deffn {} BFD_RELOC_FR30_8_IN_8
1735
This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
1736
into 8 bits.
1737
@end deffn
1738
@deffn {} BFD_RELOC_FR30_9_IN_8
1739
This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
1740
into 8 bits.
1741
@end deffn
1742
@deffn {} BFD_RELOC_FR30_10_IN_8
1743
This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
1744
into 8 bits.
1745
@end deffn
1746
@deffn {} BFD_RELOC_FR30_9_PCREL
1747
This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
1748
short offset into 8 bits.
1749
@end deffn
1750
@deffn {} BFD_RELOC_FR30_12_PCREL
1751
This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
1752
short offset into 11 bits.
1753
@end deffn
1754
@deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4
1755
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2
1756
@deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2
1757
@deffnx {} BFD_RELOC_MCORE_PCREL_32
1758
@deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
1759
@deffnx {} BFD_RELOC_MCORE_RVA
1760
Motorola Mcore relocations.
1761
@end deffn
1762
@deffn {} BFD_RELOC_MEP_8
1763
@deffnx {} BFD_RELOC_MEP_16
1764
@deffnx {} BFD_RELOC_MEP_32
1765
@deffnx {} BFD_RELOC_MEP_PCREL8A2
1766
@deffnx {} BFD_RELOC_MEP_PCREL12A2
1767
@deffnx {} BFD_RELOC_MEP_PCREL17A2
1768
@deffnx {} BFD_RELOC_MEP_PCREL24A2
1769
@deffnx {} BFD_RELOC_MEP_PCABS24A2
1770
@deffnx {} BFD_RELOC_MEP_LOW16
1771
@deffnx {} BFD_RELOC_MEP_HI16U
1772
@deffnx {} BFD_RELOC_MEP_HI16S
1773
@deffnx {} BFD_RELOC_MEP_GPREL
1774
@deffnx {} BFD_RELOC_MEP_TPREL
1775
@deffnx {} BFD_RELOC_MEP_TPREL7
1776
@deffnx {} BFD_RELOC_MEP_TPREL7A2
1777
@deffnx {} BFD_RELOC_MEP_TPREL7A4
1778
@deffnx {} BFD_RELOC_MEP_UIMM24
1779
@deffnx {} BFD_RELOC_MEP_ADDR24A4
1780
@deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT
1781
@deffnx {} BFD_RELOC_MEP_GNU_VTENTRY
1782
Toshiba Media Processor Relocations.
1783
@end deffn
1784
@deffn {} BFD_RELOC_MMIX_GETA
1785
@deffnx {} BFD_RELOC_MMIX_GETA_1
1786
@deffnx {} BFD_RELOC_MMIX_GETA_2
1787
@deffnx {} BFD_RELOC_MMIX_GETA_3
1788
These are relocations for the GETA instruction.
1789
@end deffn
1790
@deffn {} BFD_RELOC_MMIX_CBRANCH
1791
@deffnx {} BFD_RELOC_MMIX_CBRANCH_J
1792
@deffnx {} BFD_RELOC_MMIX_CBRANCH_1
1793
@deffnx {} BFD_RELOC_MMIX_CBRANCH_2
1794
@deffnx {} BFD_RELOC_MMIX_CBRANCH_3
1795
These are relocations for a conditional branch instruction.
1796
@end deffn
1797
@deffn {} BFD_RELOC_MMIX_PUSHJ
1798
@deffnx {} BFD_RELOC_MMIX_PUSHJ_1
1799
@deffnx {} BFD_RELOC_MMIX_PUSHJ_2
1800
@deffnx {} BFD_RELOC_MMIX_PUSHJ_3
1801
@deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE
1802
These are relocations for the PUSHJ instruction.
1803
@end deffn
1804
@deffn {} BFD_RELOC_MMIX_JMP
1805
@deffnx {} BFD_RELOC_MMIX_JMP_1
1806
@deffnx {} BFD_RELOC_MMIX_JMP_2
1807
@deffnx {} BFD_RELOC_MMIX_JMP_3
1808
These are relocations for the JMP instruction.
1809
@end deffn
1810
@deffn {} BFD_RELOC_MMIX_ADDR19
1811
This is a relocation for a relative address as in a GETA instruction or
1812
a branch.
1813
@end deffn
1814
@deffn {} BFD_RELOC_MMIX_ADDR27
1815
This is a relocation for a relative address as in a JMP instruction.
1816
@end deffn
1817
@deffn {} BFD_RELOC_MMIX_REG_OR_BYTE
1818
This is a relocation for an instruction field that may be a general
1819
register or a value 0..255.
1820
@end deffn
1821
@deffn {} BFD_RELOC_MMIX_REG
1822
This is a relocation for an instruction field that may be a general
1823
register.
1824
@end deffn
1825
@deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET
1826
This is a relocation for two instruction fields holding a register and
1827
an offset, the equivalent of the relocation.
1828
@end deffn
1829
@deffn {} BFD_RELOC_MMIX_LOCAL
1830
This relocation is an assertion that the expression is not allocated as
1831
a global register.  It does not modify contents.
1832
@end deffn
1833
@deffn {} BFD_RELOC_AVR_7_PCREL
1834
This is a 16 bit reloc for the AVR that stores 8 bit pc relative
1835
short offset into 7 bits.
1836
@end deffn
1837
@deffn {} BFD_RELOC_AVR_13_PCREL
1838
This is a 16 bit reloc for the AVR that stores 13 bit pc relative
1839
short offset into 12 bits.
1840
@end deffn
1841
@deffn {} BFD_RELOC_AVR_16_PM
1842
This is a 16 bit reloc for the AVR that stores 17 bit value (usually
1843
program memory address) into 16 bits.
1844
@end deffn
1845
@deffn {} BFD_RELOC_AVR_LO8_LDI
1846
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1847
data memory address) into 8 bit immediate value of LDI insn.
1848
@end deffn
1849
@deffn {} BFD_RELOC_AVR_HI8_LDI
1850
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1851
of data memory address) into 8 bit immediate value of LDI insn.
1852
@end deffn
1853
@deffn {} BFD_RELOC_AVR_HH8_LDI
1854
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1855
of program memory address) into 8 bit immediate value of LDI insn.
1856
@end deffn
1857
@deffn {} BFD_RELOC_AVR_MS8_LDI
1858
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1859
of 32 bit value) into 8 bit immediate value of LDI insn.
1860
@end deffn
1861
@deffn {} BFD_RELOC_AVR_LO8_LDI_NEG
1862
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1863
(usually data memory address) into 8 bit immediate value of SUBI insn.
1864
@end deffn
1865
@deffn {} BFD_RELOC_AVR_HI8_LDI_NEG
1866
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1867
(high 8 bit of data memory address) into 8 bit immediate value of
1868
SUBI insn.
1869
@end deffn
1870
@deffn {} BFD_RELOC_AVR_HH8_LDI_NEG
1871
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1872
(most high 8 bit of program memory address) into 8 bit immediate value
1873
of LDI or SUBI insn.
1874
@end deffn
1875
@deffn {} BFD_RELOC_AVR_MS8_LDI_NEG
1876
This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
1877
of 32 bit value) into 8 bit immediate value of LDI insn.
1878
@end deffn
1879
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM
1880
This is a 16 bit reloc for the AVR that stores 8 bit value (usually
1881
command address) into 8 bit immediate value of LDI insn.
1882
@end deffn
1883
@deffn {} BFD_RELOC_AVR_LO8_LDI_GS
1884
This is a 16 bit reloc for the AVR that stores 8 bit value
1885
(command address) into 8 bit immediate value of LDI insn. If the address
1886
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1887
in the lower 128k.
1888
@end deffn
1889
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM
1890
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1891
of command address) into 8 bit immediate value of LDI insn.
1892
@end deffn
1893
@deffn {} BFD_RELOC_AVR_HI8_LDI_GS
1894
This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
1895
of command address) into 8 bit immediate value of LDI insn.  If the address
1896
is beyond the 128k boundary, the linker inserts a jump stub for this reloc
1897
below 128k.
1898
@end deffn
1899
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM
1900
This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
1901
of command address) into 8 bit immediate value of LDI insn.
1902
@end deffn
1903
@deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG
1904
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1905
(usually command address) into 8 bit immediate value of SUBI insn.
1906
@end deffn
1907
@deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG
1908
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1909
(high 8 bit of 16 bit command address) into 8 bit immediate value
1910
of SUBI insn.
1911
@end deffn
1912
@deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG
1913
This is a 16 bit reloc for the AVR that stores negated 8 bit value
1914
(high 6 bit of 22 bit command address) into 8 bit immediate
1915
value of SUBI insn.
1916
@end deffn
1917
@deffn {} BFD_RELOC_AVR_CALL
1918
This is a 32 bit reloc for the AVR that stores 23 bit value
1919
into 22 bits.
1920
@end deffn
1921
@deffn {} BFD_RELOC_AVR_LDI
1922
This is a 16 bit reloc for the AVR that stores all needed bits
1923
for absolute addressing with ldi with overflow check to linktime
1924
@end deffn
1925
@deffn {} BFD_RELOC_AVR_6
1926
This is a 6 bit reloc for the AVR that stores offset for ldd/std
1927
instructions
1928
@end deffn
1929
@deffn {} BFD_RELOC_AVR_6_ADIW
1930
This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
1931
instructions
1932
@end deffn
1933
@deffn {} BFD_RELOC_390_12
1934
Direct 12 bit.
1935
@end deffn
1936
@deffn {} BFD_RELOC_390_GOT12
1937
12 bit GOT offset.
1938
@end deffn
1939
@deffn {} BFD_RELOC_390_PLT32
1940
32 bit PC relative PLT address.
1941
@end deffn
1942
@deffn {} BFD_RELOC_390_COPY
1943
Copy symbol at runtime.
1944
@end deffn
1945
@deffn {} BFD_RELOC_390_GLOB_DAT
1946
Create GOT entry.
1947
@end deffn
1948
@deffn {} BFD_RELOC_390_JMP_SLOT
1949
Create PLT entry.
1950
@end deffn
1951
@deffn {} BFD_RELOC_390_RELATIVE
1952
Adjust by program base.
1953
@end deffn
1954
@deffn {} BFD_RELOC_390_GOTPC
1955
32 bit PC relative offset to GOT.
1956
@end deffn
1957
@deffn {} BFD_RELOC_390_GOT16
1958
16 bit GOT offset.
1959
@end deffn
1960
@deffn {} BFD_RELOC_390_PC16DBL
1961
PC relative 16 bit shifted by 1.
1962
@end deffn
1963
@deffn {} BFD_RELOC_390_PLT16DBL
1964
16 bit PC rel. PLT shifted by 1.
1965
@end deffn
1966
@deffn {} BFD_RELOC_390_PC32DBL
1967
PC relative 32 bit shifted by 1.
1968
@end deffn
1969
@deffn {} BFD_RELOC_390_PLT32DBL
1970
32 bit PC rel. PLT shifted by 1.
1971
@end deffn
1972
@deffn {} BFD_RELOC_390_GOTPCDBL
1973
32 bit PC rel. GOT shifted by 1.
1974
@end deffn
1975
@deffn {} BFD_RELOC_390_GOT64
1976
64 bit GOT offset.
1977
@end deffn
1978
@deffn {} BFD_RELOC_390_PLT64
1979
64 bit PC relative PLT address.
1980
@end deffn
1981
@deffn {} BFD_RELOC_390_GOTENT
1982
32 bit rel. offset to GOT entry.
1983
@end deffn
1984
@deffn {} BFD_RELOC_390_GOTOFF64
1985
64 bit offset to GOT.
1986
@end deffn
1987
@deffn {} BFD_RELOC_390_GOTPLT12
1988
12-bit offset to symbol-entry within GOT, with PLT handling.
1989
@end deffn
1990
@deffn {} BFD_RELOC_390_GOTPLT16
1991
16-bit offset to symbol-entry within GOT, with PLT handling.
1992
@end deffn
1993
@deffn {} BFD_RELOC_390_GOTPLT32
1994
32-bit offset to symbol-entry within GOT, with PLT handling.
1995
@end deffn
1996
@deffn {} BFD_RELOC_390_GOTPLT64
1997
64-bit offset to symbol-entry within GOT, with PLT handling.
1998
@end deffn
1999
@deffn {} BFD_RELOC_390_GOTPLTENT
2000
32-bit rel. offset to symbol-entry within GOT, with PLT handling.
2001
@end deffn
2002
@deffn {} BFD_RELOC_390_PLTOFF16
2003
16-bit rel. offset from the GOT to a PLT entry.
2004
@end deffn
2005
@deffn {} BFD_RELOC_390_PLTOFF32
2006
32-bit rel. offset from the GOT to a PLT entry.
2007
@end deffn
2008
@deffn {} BFD_RELOC_390_PLTOFF64
2009
64-bit rel. offset from the GOT to a PLT entry.
2010
@end deffn
2011
@deffn {} BFD_RELOC_390_TLS_LOAD
2012
@deffnx {} BFD_RELOC_390_TLS_GDCALL
2013
@deffnx {} BFD_RELOC_390_TLS_LDCALL
2014
@deffnx {} BFD_RELOC_390_TLS_GD32
2015
@deffnx {} BFD_RELOC_390_TLS_GD64
2016
@deffnx {} BFD_RELOC_390_TLS_GOTIE12
2017
@deffnx {} BFD_RELOC_390_TLS_GOTIE32
2018
@deffnx {} BFD_RELOC_390_TLS_GOTIE64
2019
@deffnx {} BFD_RELOC_390_TLS_LDM32
2020
@deffnx {} BFD_RELOC_390_TLS_LDM64
2021
@deffnx {} BFD_RELOC_390_TLS_IE32
2022
@deffnx {} BFD_RELOC_390_TLS_IE64
2023
@deffnx {} BFD_RELOC_390_TLS_IEENT
2024
@deffnx {} BFD_RELOC_390_TLS_LE32
2025
@deffnx {} BFD_RELOC_390_TLS_LE64
2026
@deffnx {} BFD_RELOC_390_TLS_LDO32
2027
@deffnx {} BFD_RELOC_390_TLS_LDO64
2028
@deffnx {} BFD_RELOC_390_TLS_DTPMOD
2029
@deffnx {} BFD_RELOC_390_TLS_DTPOFF
2030
@deffnx {} BFD_RELOC_390_TLS_TPOFF
2031
s390 tls relocations.
2032
@end deffn
2033
@deffn {} BFD_RELOC_390_20
2034
@deffnx {} BFD_RELOC_390_GOT20
2035
@deffnx {} BFD_RELOC_390_GOTPLT20
2036
@deffnx {} BFD_RELOC_390_TLS_GOTIE20
2037
Long displacement extension.
2038
@end deffn
2039
@deffn {} BFD_RELOC_SCORE_DUMMY1
2040
Score relocations
2041
@end deffn
2042
@deffn {} BFD_RELOC_SCORE_GPREL15
2043
Low 16 bit for load/store
2044
@end deffn
2045
@deffn {} BFD_RELOC_SCORE_DUMMY2
2046
@deffnx {} BFD_RELOC_SCORE_JMP
2047
This is a 24-bit reloc with the right 1 bit assumed to be 0
2048
@end deffn
2049
@deffn {} BFD_RELOC_SCORE_BRANCH
2050
This is a 19-bit reloc with the right 1 bit assumed to be 0
2051
@end deffn
2052
@deffn {} BFD_RELOC_SCORE16_JMP
2053
This is a 11-bit reloc with the right 1 bit assumed to be 0
2054
@end deffn
2055
@deffn {} BFD_RELOC_SCORE16_BRANCH
2056
This is a 8-bit reloc with the right 1 bit assumed to be 0
2057
@end deffn
2058
@deffn {} BFD_RELOC_SCORE_GOT15
2059
@deffnx {} BFD_RELOC_SCORE_GOT_LO16
2060
@deffnx {} BFD_RELOC_SCORE_CALL15
2061
@deffnx {} BFD_RELOC_SCORE_DUMMY_HI16
2062
Undocumented Score relocs
2063
@end deffn
2064
@deffn {} BFD_RELOC_IP2K_FR9
2065
Scenix IP2K - 9-bit register number / data address
2066
@end deffn
2067
@deffn {} BFD_RELOC_IP2K_BANK
2068
Scenix IP2K - 4-bit register/data bank number
2069
@end deffn
2070
@deffn {} BFD_RELOC_IP2K_ADDR16CJP
2071
Scenix IP2K - low 13 bits of instruction word address
2072
@end deffn
2073
@deffn {} BFD_RELOC_IP2K_PAGE3
2074
Scenix IP2K - high 3 bits of instruction word address
2075
@end deffn
2076
@deffn {} BFD_RELOC_IP2K_LO8DATA
2077
@deffnx {} BFD_RELOC_IP2K_HI8DATA
2078
@deffnx {} BFD_RELOC_IP2K_EX8DATA
2079
Scenix IP2K - ext/low/high 8 bits of data address
2080
@end deffn
2081
@deffn {} BFD_RELOC_IP2K_LO8INSN
2082
@deffnx {} BFD_RELOC_IP2K_HI8INSN
2083
Scenix IP2K - low/high 8 bits of instruction word address
2084
@end deffn
2085
@deffn {} BFD_RELOC_IP2K_PC_SKIP
2086
Scenix IP2K - even/odd PC modifier to modify snb pcl.0
2087
@end deffn
2088
@deffn {} BFD_RELOC_IP2K_TEXT
2089
Scenix IP2K - 16 bit word address in text section.
2090
@end deffn
2091
@deffn {} BFD_RELOC_IP2K_FR_OFFSET
2092
Scenix IP2K - 7-bit sp or dp offset
2093
@end deffn
2094
@deffn {} BFD_RELOC_VPE4KMATH_DATA
2095
@deffnx {} BFD_RELOC_VPE4KMATH_INSN
2096
Scenix VPE4K coprocessor - data/insn-space addressing
2097
@end deffn
2098
@deffn {} BFD_RELOC_VTABLE_INHERIT
2099
@deffnx {} BFD_RELOC_VTABLE_ENTRY
2100
These two relocations are used by the linker to determine which of
2101
the entries in a C++ virtual function table are actually used.  When
2102
the --gc-sections option is given, the linker will zero out the entries
2103
that are not used, so that the code for those functions need not be
2104
included in the output.
2105
 
2106
VTABLE_INHERIT is a zero-space relocation used to describe to the
2107
linker the inheritance tree of a C++ virtual function table.  The
2108
relocation's symbol should be the parent class' vtable, and the
2109
relocation should be located at the child vtable.
2110
 
2111
VTABLE_ENTRY is a zero-space relocation that describes the use of a
2112
virtual function table entry.  The reloc's symbol should refer to the
2113
table of the class mentioned in the code.  Off of that base, an offset
2114
describes the entry that is being used.  For Rela hosts, this offset
2115
is stored in the reloc's addend.  For Rel hosts, we are forced to put
2116
this offset in the reloc's section offset.
2117
@end deffn
2118
@deffn {} BFD_RELOC_IA64_IMM14
2119
@deffnx {} BFD_RELOC_IA64_IMM22
2120
@deffnx {} BFD_RELOC_IA64_IMM64
2121
@deffnx {} BFD_RELOC_IA64_DIR32MSB
2122
@deffnx {} BFD_RELOC_IA64_DIR32LSB
2123
@deffnx {} BFD_RELOC_IA64_DIR64MSB
2124
@deffnx {} BFD_RELOC_IA64_DIR64LSB
2125
@deffnx {} BFD_RELOC_IA64_GPREL22
2126
@deffnx {} BFD_RELOC_IA64_GPREL64I
2127
@deffnx {} BFD_RELOC_IA64_GPREL32MSB
2128
@deffnx {} BFD_RELOC_IA64_GPREL32LSB
2129
@deffnx {} BFD_RELOC_IA64_GPREL64MSB
2130
@deffnx {} BFD_RELOC_IA64_GPREL64LSB
2131
@deffnx {} BFD_RELOC_IA64_LTOFF22
2132
@deffnx {} BFD_RELOC_IA64_LTOFF64I
2133
@deffnx {} BFD_RELOC_IA64_PLTOFF22
2134
@deffnx {} BFD_RELOC_IA64_PLTOFF64I
2135
@deffnx {} BFD_RELOC_IA64_PLTOFF64MSB
2136
@deffnx {} BFD_RELOC_IA64_PLTOFF64LSB
2137
@deffnx {} BFD_RELOC_IA64_FPTR64I
2138
@deffnx {} BFD_RELOC_IA64_FPTR32MSB
2139
@deffnx {} BFD_RELOC_IA64_FPTR32LSB
2140
@deffnx {} BFD_RELOC_IA64_FPTR64MSB
2141
@deffnx {} BFD_RELOC_IA64_FPTR64LSB
2142
@deffnx {} BFD_RELOC_IA64_PCREL21B
2143
@deffnx {} BFD_RELOC_IA64_PCREL21BI
2144
@deffnx {} BFD_RELOC_IA64_PCREL21M
2145
@deffnx {} BFD_RELOC_IA64_PCREL21F
2146
@deffnx {} BFD_RELOC_IA64_PCREL22
2147
@deffnx {} BFD_RELOC_IA64_PCREL60B
2148
@deffnx {} BFD_RELOC_IA64_PCREL64I
2149
@deffnx {} BFD_RELOC_IA64_PCREL32MSB
2150
@deffnx {} BFD_RELOC_IA64_PCREL32LSB
2151
@deffnx {} BFD_RELOC_IA64_PCREL64MSB
2152
@deffnx {} BFD_RELOC_IA64_PCREL64LSB
2153
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22
2154
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I
2155
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB
2156
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB
2157
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB
2158
@deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB
2159
@deffnx {} BFD_RELOC_IA64_SEGREL32MSB
2160
@deffnx {} BFD_RELOC_IA64_SEGREL32LSB
2161
@deffnx {} BFD_RELOC_IA64_SEGREL64MSB
2162
@deffnx {} BFD_RELOC_IA64_SEGREL64LSB
2163
@deffnx {} BFD_RELOC_IA64_SECREL32MSB
2164
@deffnx {} BFD_RELOC_IA64_SECREL32LSB
2165
@deffnx {} BFD_RELOC_IA64_SECREL64MSB
2166
@deffnx {} BFD_RELOC_IA64_SECREL64LSB
2167
@deffnx {} BFD_RELOC_IA64_REL32MSB
2168
@deffnx {} BFD_RELOC_IA64_REL32LSB
2169
@deffnx {} BFD_RELOC_IA64_REL64MSB
2170
@deffnx {} BFD_RELOC_IA64_REL64LSB
2171
@deffnx {} BFD_RELOC_IA64_LTV32MSB
2172
@deffnx {} BFD_RELOC_IA64_LTV32LSB
2173
@deffnx {} BFD_RELOC_IA64_LTV64MSB
2174
@deffnx {} BFD_RELOC_IA64_LTV64LSB
2175
@deffnx {} BFD_RELOC_IA64_IPLTMSB
2176
@deffnx {} BFD_RELOC_IA64_IPLTLSB
2177
@deffnx {} BFD_RELOC_IA64_COPY
2178
@deffnx {} BFD_RELOC_IA64_LTOFF22X
2179
@deffnx {} BFD_RELOC_IA64_LDXMOV
2180
@deffnx {} BFD_RELOC_IA64_TPREL14
2181
@deffnx {} BFD_RELOC_IA64_TPREL22
2182
@deffnx {} BFD_RELOC_IA64_TPREL64I
2183
@deffnx {} BFD_RELOC_IA64_TPREL64MSB
2184
@deffnx {} BFD_RELOC_IA64_TPREL64LSB
2185
@deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22
2186
@deffnx {} BFD_RELOC_IA64_DTPMOD64MSB
2187
@deffnx {} BFD_RELOC_IA64_DTPMOD64LSB
2188
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22
2189
@deffnx {} BFD_RELOC_IA64_DTPREL14
2190
@deffnx {} BFD_RELOC_IA64_DTPREL22
2191
@deffnx {} BFD_RELOC_IA64_DTPREL64I
2192
@deffnx {} BFD_RELOC_IA64_DTPREL32MSB
2193
@deffnx {} BFD_RELOC_IA64_DTPREL32LSB
2194
@deffnx {} BFD_RELOC_IA64_DTPREL64MSB
2195
@deffnx {} BFD_RELOC_IA64_DTPREL64LSB
2196
@deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22
2197
Intel IA64 Relocations.
2198
@end deffn
2199
@deffn {} BFD_RELOC_M68HC11_HI8
2200
Motorola 68HC11 reloc.
2201
This is the 8 bit high part of an absolute address.
2202
@end deffn
2203
@deffn {} BFD_RELOC_M68HC11_LO8
2204
Motorola 68HC11 reloc.
2205
This is the 8 bit low part of an absolute address.
2206
@end deffn
2207
@deffn {} BFD_RELOC_M68HC11_3B
2208
Motorola 68HC11 reloc.
2209
This is the 3 bit of a value.
2210
@end deffn
2211
@deffn {} BFD_RELOC_M68HC11_RL_JUMP
2212
Motorola 68HC11 reloc.
2213
This reloc marks the beginning of a jump/call instruction.
2214
It is used for linker relaxation to correctly identify beginning
2215
of instruction and change some branches to use PC-relative
2216
addressing mode.
2217
@end deffn
2218
@deffn {} BFD_RELOC_M68HC11_RL_GROUP
2219
Motorola 68HC11 reloc.
2220
This reloc marks a group of several instructions that gcc generates
2221
and for which the linker relaxation pass can modify and/or remove
2222
some of them.
2223
@end deffn
2224
@deffn {} BFD_RELOC_M68HC11_LO16
2225
Motorola 68HC11 reloc.
2226
This is the 16-bit lower part of an address.  It is used for 'call'
2227
instruction to specify the symbol address without any special
2228
transformation (due to memory bank window).
2229
@end deffn
2230
@deffn {} BFD_RELOC_M68HC11_PAGE
2231
Motorola 68HC11 reloc.
2232
This is a 8-bit reloc that specifies the page number of an address.
2233
It is used by 'call' instruction to specify the page number of
2234
the symbol.
2235
@end deffn
2236
@deffn {} BFD_RELOC_M68HC11_24
2237
Motorola 68HC11 reloc.
2238
This is a 24-bit reloc that represents the address with a 16-bit
2239
value and a 8-bit page number.  The symbol address is transformed
2240
to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
2241
@end deffn
2242
@deffn {} BFD_RELOC_M68HC12_5B
2243
Motorola 68HC12 reloc.
2244
This is the 5 bits of a value.
2245
@end deffn
2246
@deffn {} BFD_RELOC_16C_NUM08
2247
@deffnx {} BFD_RELOC_16C_NUM08_C
2248
@deffnx {} BFD_RELOC_16C_NUM16
2249
@deffnx {} BFD_RELOC_16C_NUM16_C
2250
@deffnx {} BFD_RELOC_16C_NUM32
2251
@deffnx {} BFD_RELOC_16C_NUM32_C
2252
@deffnx {} BFD_RELOC_16C_DISP04
2253
@deffnx {} BFD_RELOC_16C_DISP04_C
2254
@deffnx {} BFD_RELOC_16C_DISP08
2255
@deffnx {} BFD_RELOC_16C_DISP08_C
2256
@deffnx {} BFD_RELOC_16C_DISP16
2257
@deffnx {} BFD_RELOC_16C_DISP16_C
2258
@deffnx {} BFD_RELOC_16C_DISP24
2259
@deffnx {} BFD_RELOC_16C_DISP24_C
2260
@deffnx {} BFD_RELOC_16C_DISP24a
2261
@deffnx {} BFD_RELOC_16C_DISP24a_C
2262
@deffnx {} BFD_RELOC_16C_REG04
2263
@deffnx {} BFD_RELOC_16C_REG04_C
2264
@deffnx {} BFD_RELOC_16C_REG04a
2265
@deffnx {} BFD_RELOC_16C_REG04a_C
2266
@deffnx {} BFD_RELOC_16C_REG14
2267
@deffnx {} BFD_RELOC_16C_REG14_C
2268
@deffnx {} BFD_RELOC_16C_REG16
2269
@deffnx {} BFD_RELOC_16C_REG16_C
2270
@deffnx {} BFD_RELOC_16C_REG20
2271
@deffnx {} BFD_RELOC_16C_REG20_C
2272
@deffnx {} BFD_RELOC_16C_ABS20
2273
@deffnx {} BFD_RELOC_16C_ABS20_C
2274
@deffnx {} BFD_RELOC_16C_ABS24
2275
@deffnx {} BFD_RELOC_16C_ABS24_C
2276
@deffnx {} BFD_RELOC_16C_IMM04
2277
@deffnx {} BFD_RELOC_16C_IMM04_C
2278
@deffnx {} BFD_RELOC_16C_IMM16
2279
@deffnx {} BFD_RELOC_16C_IMM16_C
2280
@deffnx {} BFD_RELOC_16C_IMM20
2281
@deffnx {} BFD_RELOC_16C_IMM20_C
2282
@deffnx {} BFD_RELOC_16C_IMM24
2283
@deffnx {} BFD_RELOC_16C_IMM24_C
2284
@deffnx {} BFD_RELOC_16C_IMM32
2285
@deffnx {} BFD_RELOC_16C_IMM32_C
2286
NS CR16C Relocations.
2287
@end deffn
2288
@deffn {} BFD_RELOC_CR16_NUM8
2289
@deffnx {} BFD_RELOC_CR16_NUM16
2290
@deffnx {} BFD_RELOC_CR16_NUM32
2291
@deffnx {} BFD_RELOC_CR16_NUM32a
2292
@deffnx {} BFD_RELOC_CR16_REGREL0
2293
@deffnx {} BFD_RELOC_CR16_REGREL4
2294
@deffnx {} BFD_RELOC_CR16_REGREL4a
2295
@deffnx {} BFD_RELOC_CR16_REGREL14
2296
@deffnx {} BFD_RELOC_CR16_REGREL14a
2297
@deffnx {} BFD_RELOC_CR16_REGREL16
2298
@deffnx {} BFD_RELOC_CR16_REGREL20
2299
@deffnx {} BFD_RELOC_CR16_REGREL20a
2300
@deffnx {} BFD_RELOC_CR16_ABS20
2301
@deffnx {} BFD_RELOC_CR16_ABS24
2302
@deffnx {} BFD_RELOC_CR16_IMM4
2303
@deffnx {} BFD_RELOC_CR16_IMM8
2304
@deffnx {} BFD_RELOC_CR16_IMM16
2305
@deffnx {} BFD_RELOC_CR16_IMM20
2306
@deffnx {} BFD_RELOC_CR16_IMM24
2307
@deffnx {} BFD_RELOC_CR16_IMM32
2308
@deffnx {} BFD_RELOC_CR16_IMM32a
2309
@deffnx {} BFD_RELOC_CR16_DISP4
2310
@deffnx {} BFD_RELOC_CR16_DISP8
2311
@deffnx {} BFD_RELOC_CR16_DISP16
2312
@deffnx {} BFD_RELOC_CR16_DISP20
2313
@deffnx {} BFD_RELOC_CR16_DISP24
2314
@deffnx {} BFD_RELOC_CR16_DISP24a
2315
@deffnx {} BFD_RELOC_CR16_SWITCH8
2316
@deffnx {} BFD_RELOC_CR16_SWITCH16
2317
@deffnx {} BFD_RELOC_CR16_SWITCH32
2318
NS CR16 Relocations.
2319
@end deffn
2320
@deffn {} BFD_RELOC_CRX_REL4
2321
@deffnx {} BFD_RELOC_CRX_REL8
2322
@deffnx {} BFD_RELOC_CRX_REL8_CMP
2323
@deffnx {} BFD_RELOC_CRX_REL16
2324
@deffnx {} BFD_RELOC_CRX_REL24
2325
@deffnx {} BFD_RELOC_CRX_REL32
2326
@deffnx {} BFD_RELOC_CRX_REGREL12
2327
@deffnx {} BFD_RELOC_CRX_REGREL22
2328
@deffnx {} BFD_RELOC_CRX_REGREL28
2329
@deffnx {} BFD_RELOC_CRX_REGREL32
2330
@deffnx {} BFD_RELOC_CRX_ABS16
2331
@deffnx {} BFD_RELOC_CRX_ABS32
2332
@deffnx {} BFD_RELOC_CRX_NUM8
2333
@deffnx {} BFD_RELOC_CRX_NUM16
2334
@deffnx {} BFD_RELOC_CRX_NUM32
2335
@deffnx {} BFD_RELOC_CRX_IMM16
2336
@deffnx {} BFD_RELOC_CRX_IMM32
2337
@deffnx {} BFD_RELOC_CRX_SWITCH8
2338
@deffnx {} BFD_RELOC_CRX_SWITCH16
2339
@deffnx {} BFD_RELOC_CRX_SWITCH32
2340
NS CRX Relocations.
2341
@end deffn
2342
@deffn {} BFD_RELOC_CRIS_BDISP8
2343
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_5
2344
@deffnx {} BFD_RELOC_CRIS_SIGNED_6
2345
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_6
2346
@deffnx {} BFD_RELOC_CRIS_SIGNED_8
2347
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_8
2348
@deffnx {} BFD_RELOC_CRIS_SIGNED_16
2349
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_16
2350
@deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET
2351
@deffnx {} BFD_RELOC_CRIS_UNSIGNED_4
2352
These relocs are only used within the CRIS assembler.  They are not
2353
(at present) written to any object files.
2354
@end deffn
2355
@deffn {} BFD_RELOC_CRIS_COPY
2356
@deffnx {} BFD_RELOC_CRIS_GLOB_DAT
2357
@deffnx {} BFD_RELOC_CRIS_JUMP_SLOT
2358
@deffnx {} BFD_RELOC_CRIS_RELATIVE
2359
Relocs used in ELF shared libraries for CRIS.
2360
@end deffn
2361
@deffn {} BFD_RELOC_CRIS_32_GOT
2362
32-bit offset to symbol-entry within GOT.
2363
@end deffn
2364
@deffn {} BFD_RELOC_CRIS_16_GOT
2365
16-bit offset to symbol-entry within GOT.
2366
@end deffn
2367
@deffn {} BFD_RELOC_CRIS_32_GOTPLT
2368
32-bit offset to symbol-entry within GOT, with PLT handling.
2369
@end deffn
2370
@deffn {} BFD_RELOC_CRIS_16_GOTPLT
2371
16-bit offset to symbol-entry within GOT, with PLT handling.
2372
@end deffn
2373
@deffn {} BFD_RELOC_CRIS_32_GOTREL
2374
32-bit offset to symbol, relative to GOT.
2375
@end deffn
2376
@deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL
2377
32-bit offset to symbol with PLT entry, relative to GOT.
2378
@end deffn
2379
@deffn {} BFD_RELOC_CRIS_32_PLT_PCREL
2380
32-bit offset to symbol with PLT entry, relative to this relocation.
2381
@end deffn
2382
@deffn {} BFD_RELOC_860_COPY
2383
@deffnx {} BFD_RELOC_860_GLOB_DAT
2384
@deffnx {} BFD_RELOC_860_JUMP_SLOT
2385
@deffnx {} BFD_RELOC_860_RELATIVE
2386
@deffnx {} BFD_RELOC_860_PC26
2387
@deffnx {} BFD_RELOC_860_PLT26
2388
@deffnx {} BFD_RELOC_860_PC16
2389
@deffnx {} BFD_RELOC_860_LOW0
2390
@deffnx {} BFD_RELOC_860_SPLIT0
2391
@deffnx {} BFD_RELOC_860_LOW1
2392
@deffnx {} BFD_RELOC_860_SPLIT1
2393
@deffnx {} BFD_RELOC_860_LOW2
2394
@deffnx {} BFD_RELOC_860_SPLIT2
2395
@deffnx {} BFD_RELOC_860_LOW3
2396
@deffnx {} BFD_RELOC_860_LOGOT0
2397
@deffnx {} BFD_RELOC_860_SPGOT0
2398
@deffnx {} BFD_RELOC_860_LOGOT1
2399
@deffnx {} BFD_RELOC_860_SPGOT1
2400
@deffnx {} BFD_RELOC_860_LOGOTOFF0
2401
@deffnx {} BFD_RELOC_860_SPGOTOFF0
2402
@deffnx {} BFD_RELOC_860_LOGOTOFF1
2403
@deffnx {} BFD_RELOC_860_SPGOTOFF1
2404
@deffnx {} BFD_RELOC_860_LOGOTOFF2
2405
@deffnx {} BFD_RELOC_860_LOGOTOFF3
2406
@deffnx {} BFD_RELOC_860_LOPC
2407
@deffnx {} BFD_RELOC_860_HIGHADJ
2408
@deffnx {} BFD_RELOC_860_HAGOT
2409
@deffnx {} BFD_RELOC_860_HAGOTOFF
2410
@deffnx {} BFD_RELOC_860_HAPC
2411
@deffnx {} BFD_RELOC_860_HIGH
2412
@deffnx {} BFD_RELOC_860_HIGOT
2413
@deffnx {} BFD_RELOC_860_HIGOTOFF
2414
Intel i860 Relocations.
2415
@end deffn
2416
@deffn {} BFD_RELOC_OPENRISC_ABS_26
2417
@deffnx {} BFD_RELOC_OPENRISC_REL_26
2418
OpenRISC Relocations.
2419
@end deffn
2420
@deffn {} BFD_RELOC_H8_DIR16A8
2421
@deffnx {} BFD_RELOC_H8_DIR16R8
2422
@deffnx {} BFD_RELOC_H8_DIR24A8
2423
@deffnx {} BFD_RELOC_H8_DIR24R8
2424
@deffnx {} BFD_RELOC_H8_DIR32A16
2425
H8 elf Relocations.
2426
@end deffn
2427
@deffn {} BFD_RELOC_XSTORMY16_REL_12
2428
@deffnx {} BFD_RELOC_XSTORMY16_12
2429
@deffnx {} BFD_RELOC_XSTORMY16_24
2430
@deffnx {} BFD_RELOC_XSTORMY16_FPTR16
2431
Sony Xstormy16 Relocations.
2432
@end deffn
2433
@deffn {} BFD_RELOC_RELC
2434
Self-describing complex relocations.
2435
@end deffn
2436
@deffn {} BFD_RELOC_XC16X_PAG
2437
@deffnx {} BFD_RELOC_XC16X_POF
2438
@deffnx {} BFD_RELOC_XC16X_SEG
2439
@deffnx {} BFD_RELOC_XC16X_SOF
2440
Infineon Relocations.
2441
@end deffn
2442
@deffn {} BFD_RELOC_VAX_GLOB_DAT
2443
@deffnx {} BFD_RELOC_VAX_JMP_SLOT
2444
@deffnx {} BFD_RELOC_VAX_RELATIVE
2445
Relocations used by VAX ELF.
2446
@end deffn
2447
@deffn {} BFD_RELOC_MT_PC16
2448
Morpho MT - 16 bit immediate relocation.
2449
@end deffn
2450
@deffn {} BFD_RELOC_MT_HI16
2451
Morpho MT - Hi 16 bits of an address.
2452
@end deffn
2453
@deffn {} BFD_RELOC_MT_LO16
2454
Morpho MT - Low 16 bits of an address.
2455
@end deffn
2456
@deffn {} BFD_RELOC_MT_GNU_VTINHERIT
2457
Morpho MT - Used to tell the linker which vtable entries are used.
2458
@end deffn
2459
@deffn {} BFD_RELOC_MT_GNU_VTENTRY
2460
Morpho MT - Used to tell the linker which vtable entries are used.
2461
@end deffn
2462
@deffn {} BFD_RELOC_MT_PCINSN8
2463
Morpho MT - 8 bit immediate relocation.
2464
@end deffn
2465
@deffn {} BFD_RELOC_MSP430_10_PCREL
2466
@deffnx {} BFD_RELOC_MSP430_16_PCREL
2467
@deffnx {} BFD_RELOC_MSP430_16
2468
@deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE
2469
@deffnx {} BFD_RELOC_MSP430_16_BYTE
2470
@deffnx {} BFD_RELOC_MSP430_2X_PCREL
2471
@deffnx {} BFD_RELOC_MSP430_RL_PCREL
2472
msp430 specific relocation codes
2473
@end deffn
2474
@deffn {} BFD_RELOC_IQ2000_OFFSET_16
2475
@deffnx {} BFD_RELOC_IQ2000_OFFSET_21
2476
@deffnx {} BFD_RELOC_IQ2000_UHI16
2477
IQ2000 Relocations.
2478
@end deffn
2479
@deffn {} BFD_RELOC_XTENSA_RTLD
2480
Special Xtensa relocation used only by PLT entries in ELF shared
2481
objects to indicate that the runtime linker should set the value
2482
to one of its own internal functions or data structures.
2483
@end deffn
2484
@deffn {} BFD_RELOC_XTENSA_GLOB_DAT
2485
@deffnx {} BFD_RELOC_XTENSA_JMP_SLOT
2486
@deffnx {} BFD_RELOC_XTENSA_RELATIVE
2487
Xtensa relocations for ELF shared objects.
2488
@end deffn
2489
@deffn {} BFD_RELOC_XTENSA_PLT
2490
Xtensa relocation used in ELF object files for symbols that may require
2491
PLT entries.  Otherwise, this is just a generic 32-bit relocation.
2492
@end deffn
2493
@deffn {} BFD_RELOC_XTENSA_DIFF8
2494
@deffnx {} BFD_RELOC_XTENSA_DIFF16
2495
@deffnx {} BFD_RELOC_XTENSA_DIFF32
2496
Xtensa relocations to mark the difference of two local symbols.
2497
These are only needed to support linker relaxation and can be ignored
2498
when not relaxing.  The field is set to the value of the difference
2499
assuming no relaxation.  The relocation encodes the position of the
2500
first symbol so the linker can determine whether to adjust the field
2501
value.
2502
@end deffn
2503
@deffn {} BFD_RELOC_XTENSA_SLOT0_OP
2504
@deffnx {} BFD_RELOC_XTENSA_SLOT1_OP
2505
@deffnx {} BFD_RELOC_XTENSA_SLOT2_OP
2506
@deffnx {} BFD_RELOC_XTENSA_SLOT3_OP
2507
@deffnx {} BFD_RELOC_XTENSA_SLOT4_OP
2508
@deffnx {} BFD_RELOC_XTENSA_SLOT5_OP
2509
@deffnx {} BFD_RELOC_XTENSA_SLOT6_OP
2510
@deffnx {} BFD_RELOC_XTENSA_SLOT7_OP
2511
@deffnx {} BFD_RELOC_XTENSA_SLOT8_OP
2512
@deffnx {} BFD_RELOC_XTENSA_SLOT9_OP
2513
@deffnx {} BFD_RELOC_XTENSA_SLOT10_OP
2514
@deffnx {} BFD_RELOC_XTENSA_SLOT11_OP
2515
@deffnx {} BFD_RELOC_XTENSA_SLOT12_OP
2516
@deffnx {} BFD_RELOC_XTENSA_SLOT13_OP
2517
@deffnx {} BFD_RELOC_XTENSA_SLOT14_OP
2518
Generic Xtensa relocations for instruction operands.  Only the slot
2519
number is encoded in the relocation.  The relocation applies to the
2520
last PC-relative immediate operand, or if there are no PC-relative
2521
immediates, to the last immediate operand.
2522
@end deffn
2523
@deffn {} BFD_RELOC_XTENSA_SLOT0_ALT
2524
@deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT
2525
@deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT
2526
@deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT
2527
@deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT
2528
@deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT
2529
@deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT
2530
@deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT
2531
@deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT
2532
@deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT
2533
@deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT
2534
@deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT
2535
@deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT
2536
@deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT
2537
@deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT
2538
Alternate Xtensa relocations.  Only the slot is encoded in the
2539
relocation.  The meaning of these relocations is opcode-specific.
2540
@end deffn
2541
@deffn {} BFD_RELOC_XTENSA_OP0
2542
@deffnx {} BFD_RELOC_XTENSA_OP1
2543
@deffnx {} BFD_RELOC_XTENSA_OP2
2544
Xtensa relocations for backward compatibility.  These have all been
2545
replaced by BFD_RELOC_XTENSA_SLOT0_OP.
2546
@end deffn
2547
@deffn {} BFD_RELOC_XTENSA_ASM_EXPAND
2548
Xtensa relocation to mark that the assembler expanded the
2549
instructions from an original target.  The expansion size is
2550
encoded in the reloc size.
2551
@end deffn
2552
@deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY
2553
Xtensa relocation to mark that the linker should simplify
2554
assembler-expanded instructions.  This is commonly used
2555
internally by the linker after analysis of a
2556
BFD_RELOC_XTENSA_ASM_EXPAND.
2557
@end deffn
2558
@deffn {} BFD_RELOC_Z80_DISP8
2559
8 bit signed offset in (ix+d) or (iy+d).
2560
@end deffn
2561
@deffn {} BFD_RELOC_Z8K_DISP7
2562
DJNZ offset.
2563
@end deffn
2564
@deffn {} BFD_RELOC_Z8K_CALLR
2565
CALR offset.
2566
@end deffn
2567
@deffn {} BFD_RELOC_Z8K_IMM4L
2568
4 bit value.
2569
@end deffn
2570
 
2571
@example
2572
 
2573
typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
2574
@end example
2575
@findex bfd_reloc_type_lookup
2576
@subsubsection @code{bfd_reloc_type_lookup}
2577
@strong{Synopsis}
2578
@example
2579
reloc_howto_type *bfd_reloc_type_lookup
2580
   (bfd *abfd, bfd_reloc_code_real_type code);
2581
reloc_howto_type *bfd_reloc_name_lookup
2582
   (bfd *abfd, const char *reloc_name);
2583
@end example
2584
@strong{Description}@*
2585
Return a pointer to a howto structure which, when
2586
invoked, will perform the relocation @var{code} on data from the
2587
architecture noted.
2588
 
2589
@findex bfd_default_reloc_type_lookup
2590
@subsubsection @code{bfd_default_reloc_type_lookup}
2591
@strong{Synopsis}
2592
@example
2593
reloc_howto_type *bfd_default_reloc_type_lookup
2594
   (bfd *abfd, bfd_reloc_code_real_type  code);
2595
@end example
2596
@strong{Description}@*
2597
Provides a default relocation lookup routine for any architecture.
2598
 
2599
@findex bfd_get_reloc_code_name
2600
@subsubsection @code{bfd_get_reloc_code_name}
2601
@strong{Synopsis}
2602
@example
2603
const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
2604
@end example
2605
@strong{Description}@*
2606
Provides a printable name for the supplied relocation code.
2607
Useful mainly for printing error messages.
2608
 
2609
@findex bfd_generic_relax_section
2610
@subsubsection @code{bfd_generic_relax_section}
2611
@strong{Synopsis}
2612
@example
2613
bfd_boolean bfd_generic_relax_section
2614
   (bfd *abfd,
2615
    asection *section,
2616
    struct bfd_link_info *,
2617
    bfd_boolean *);
2618
@end example
2619
@strong{Description}@*
2620
Provides default handling for relaxing for back ends which
2621
don't do relaxing.
2622
 
2623
@findex bfd_generic_gc_sections
2624
@subsubsection @code{bfd_generic_gc_sections}
2625
@strong{Synopsis}
2626
@example
2627
bfd_boolean bfd_generic_gc_sections
2628
   (bfd *, struct bfd_link_info *);
2629
@end example
2630
@strong{Description}@*
2631
Provides default handling for relaxing for back ends which
2632
don't do section gc -- i.e., does nothing.
2633
 
2634
@findex bfd_generic_merge_sections
2635
@subsubsection @code{bfd_generic_merge_sections}
2636
@strong{Synopsis}
2637
@example
2638
bfd_boolean bfd_generic_merge_sections
2639
   (bfd *, struct bfd_link_info *);
2640
@end example
2641
@strong{Description}@*
2642
Provides default handling for SEC_MERGE section merging for back ends
2643
which don't have SEC_MERGE support -- i.e., does nothing.
2644
 
2645
@findex bfd_generic_get_relocated_section_contents
2646
@subsubsection @code{bfd_generic_get_relocated_section_contents}
2647
@strong{Synopsis}
2648
@example
2649
bfd_byte *bfd_generic_get_relocated_section_contents
2650
   (bfd *abfd,
2651
    struct bfd_link_info *link_info,
2652
    struct bfd_link_order *link_order,
2653
    bfd_byte *data,
2654
    bfd_boolean relocatable,
2655
    asymbol **symbols);
2656
@end example
2657
@strong{Description}@*
2658
Provides default handling of relocation effort for back ends
2659
which can't be bothered to do it efficiently.
2660
 

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