OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [frv/] [stqc.pcgs] - Blame information for rev 223

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
# frv parallel testcase for stqc $CPRk,@($GRi,$GRj)
2 
# mach: frv
3 
# as(frv): -mcpu=frv
4 
 
5 
        .include "testutils.inc"
6 
 
7 
        start
8 
 
9 
        .global stqc
10 
stqc:
11 
        set_mem_limmed  0xbeef,0xdead,sp
12 
        inc_gr_immed    -4,sp
13 
        set_mem_limmed  0xdead,0xbeef,sp
14 
        inc_gr_immed    -4,sp
15 
        set_mem_limmed  0xdead,0xdead,sp
16 
        inc_gr_immed    -4,sp
17 
        set_mem_limmed  0xbeef,0xbeef,sp
18 
        set_gr_immed    0,gr7
19 
        set_cpr_limmed  0xbeef,0xdead,cpr8
20 
        set_cpr_limmed  0xdead,0xbeef,cpr9
21 
        set_cpr_limmed  0xdead,0xdead,cpr10
22 
        set_cpr_limmed  0xbeef,0xbeef,cpr11
23 
        stqc            cpr8,@(sp,gr7)          ; non parallel
24 
        test_mem_limmed 0xbeef,0xdead,sp
25 
        inc_gr_immed    4,sp
26 
        test_mem_limmed 0xdead,0xbeef,sp
27 
        inc_gr_immed    4,sp
28 
        test_mem_limmed 0xdead,0xdead,sp
29 
        inc_gr_immed    4,sp
30 
        test_mem_limmed 0xbeef,0xbeef,sp
31 
 
32 
        set_mem_limmed  0xbeef,0xdead,sp
33 
        inc_gr_immed    -4,sp
34 
        set_mem_limmed  0xdead,0xbeef,sp
35 
        inc_gr_immed    -4,sp
36 
        set_mem_limmed  0xdead,0xdead,sp
37 
        inc_gr_immed    -4,sp
38 
        set_mem_limmed  0xbeef,0xbeef,sp
39 
        set_gr_immed    0,gr7
40 
        set_cpr_limmed  0xbeef,0xdead,cpr8
41 
        set_cpr_limmed  0xdead,0xbeef,cpr9
42 
        set_cpr_limmed  0xdead,0xdead,cpr10
43 
        set_cpr_limmed  0xbeef,0xbeef,cpr11
44 
        stqc.p          cpr8,@(sp,gr7)          ; parallel
45 
        addi            sp,4,sp
46 
        subi            sp,4,sp
47 
        ldqc            @(sp,gr7),cpr12
48 
        test_mem_limmed 0xbeef,0xdead,sp        ; memory is set
49 
        inc_gr_immed    4,sp
50 
        test_mem_limmed 0xdead,0xbeef,sp
51 
        inc_gr_immed    4,sp
52 
        test_mem_limmed 0xdead,0xdead,sp
53 
        inc_gr_immed    4,sp
54 
        test_mem_limmed 0xbeef,0xbeef,sp
55 
        test_cpr_limmed 0xbeef,0xdead,cpr12
56 
        test_cpr_limmed 0xdead,0xbeef,cpr13
57 
        test_cpr_limmed 0xdead,0xdead,cpr14
58 
        test_cpr_limmed 0xbeef,0xbeef,cpr15
59 
 
60 
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.