OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [m32r/] [mvtaclo.cgs] - Blame information for rev 157

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# m32r testcase for mvtaclo $src1
2
# mach(): m32r m32rx
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global mvtaclo
9
mvtaclo:
10
        mvi_h_accum0 0, 0
11
        mvi_h_gr r4, 0x11223344
12
 
13
        mvtaclo r4
14
 
15
        test_h_accum0 0, 0x11223344
16
 
17
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.