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[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [sh/] [dmxy.s] - Blame information for rev 223

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# sh testcase for setdmx, setdmy, clrdmxy
# mach: shdsp
# as(shdsp):    -defsym sim_cpu=1 -dsp
 
        .include "testutils.inc"
 
        start
        set_grs_a5a5
        setdmx
        test_sr_bit_set   0x400
        test_sr_bit_clear 0x800
        setdmy
        test_sr_bit_clear 0x400
        test_sr_bit_set   0x800
        clrdmxy
        test_sr_bit_clear 0x400
        test_sr_bit_clear 0x800
 
        test_grs_a5a5
        pass
        exit 0

Line No.	Rev	Author	Line
1	24	jeremybenn	`# sh testcase for setdmx, setdmy, clrdmxy`
2			`# mach: shdsp`
3			`# as(shdsp): -defsym sim_cpu=1 -dsp`
4
5			`.include "testutils.inc"`
6
7			`start`
8			`set_grs_a5a5`
9			`setdmx`
10			`test_sr_bit_set 0x400`
11			`test_sr_bit_clear 0x800`
12			`setdmy`
13			`test_sr_bit_clear 0x400`
14			`test_sr_bit_set 0x800`
15			`clrdmxy`
16			`test_sr_bit_clear 0x400`
17			`test_sr_bit_clear 0x800`
18
19			`test_grs_a5a5`
20			`pass`
21			`exit 0`

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[/] [openrisc/] [tags/] [gnu-src/] [gdb-6.8/] [pre-binutils-2.20.1-sync/] [sim/] [testsuite/] [sim/] [sh/] [dmxy.s] - Blame information for rev 223