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[/] [openrisc/] [tags/] [gnu-src/] [gdb-7.2/] [gdb-7.2-or32-1.0rc3/] [gdb/] [testsuite/] [gdb.arch/] [vsx-regs.exp] - Blame information for rev 513

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Line No. Rev Author Line
1 330 jeremybenn 
# Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program.  If not, see .
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#
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if $tracelevel then {
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    strace $tracelevel
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}
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#
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# Test the use of VSX registers, for Powerpc.
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#
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if {![istarget "powerpc*"] || [skip_vsx_tests]} then {
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    verbose "Skipping vsx register tests."
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    return
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}
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set testfile "vsx-regs"
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set binfile ${objdir}/${subdir}/${testfile}
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set srcfile ${testfile}.c
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set compile_flags {debug nowarnings quiet}
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if [get_compiler_info $binfile] {
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    warning "get_compiler failed"
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    return -1
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}
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if [test_compiler_info gcc*] {
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    set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec"
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} elseif [test_compiler_info xlc*] {
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    set compile_flags "$compile_flags additional_flags=-qaltivec"
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} else {
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    warning "unknown compiler"
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    return -1
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}
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if  { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } {
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     untested vsx-regs.exp
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     return -1
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}
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gdb_start
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gdb_reinitialize_dir $srcdir/$subdir
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gdb_load ${binfile}
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# Run to `main' where we begin our tests.
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if ![runto_main] then {
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    gdb_suppress_tests
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}
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# Data sets used throughout the test
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set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
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set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
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set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
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set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
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set float_register ".raw 0xdeadbeefdeadbeef."
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# First run the F0~F31/VS0~VS31 tests
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# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
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for {set i 0} {$i < 32} {incr i 1} {
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    gdb_test_no_output "set \$f$i = 1\.3"
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}
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for {set i 0} {$i < 32} {incr i 1} {
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    gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)"
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}
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# 2: Set VS0~VS31 registers and check if it reflects on F0~F31.
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for {set i 0} {$i < 32} {incr i 1} {
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        for {set j 0} {$j < 4} {incr j 1} {
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           gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef"
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        }
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}
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for {set i 0} {$i < 32} {incr i 1} {
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    gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
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}
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for {set i 0} {$i < 32} {incr i 1} {
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    gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)"
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}
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# Now run the VR0~VR31/VS32~VS63 tests
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# 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63.
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for {set i 0} {$i < 32} {incr i 1} {
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        for {set j 0} {$j < 4} {incr j 1} {
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           gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1"
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        }
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}
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for {set i 32} {$i < 64} {incr i 1} {
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    gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i"
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}
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# 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31.
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for {set i 32} {$i < 64} {incr i 1} {
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        for {set j 0} {$j < 4} {incr j 1} {
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           gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1"
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        }
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}
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for {set i 0} {$i < 32} {incr i 1} {
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    gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
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}
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set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]
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set core_supported 0
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gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \
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        "Save a VSX-enabled corefile" \
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{
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  -re "Saved corefile ${escapedfilename}\[\r\n\]+$gdb_prompt $" {
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    pass "Save a VSX-enabled corefile"
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    global core_supported
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    set core_supported 1
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  }
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  -re "Can't create a corefile\[\r\n\]+$gdb_prompt $" {
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    unsupported "Save a VSX-enabled corefile"
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    global core_supported
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    set core_supported 0
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  }
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}
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if {!$core_supported} {
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  return -1
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}
148 
 
149 
gdb_exit
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gdb_start
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gdb_reinitialize_dir $srcdir/$subdir
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gdb_load ${binfile}
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154 
gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \
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        "re-load generated corefile" \
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{
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    -re ".* is not a core dump:.*$gdb_prompt $" {
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        fail "re-load generated corefile (bad file format)"
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        # No use proceeding from here.
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        return;
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    }
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    -re ".*: No such file or directory.*$gdb_prompt $" {
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        fail "re-load generated corefile (file not found)"
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        # No use proceeding from here.
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        return;
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    }
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    -re ".*Couldn't find .* registers in core file.*$gdb_prompt $" {
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        fail "re-load generated corefile (incomplete note section)"
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    }
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    -re "Core was generated by .*$gdb_prompt $" {
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        pass "re-load generated corefile"
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    }
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    -re ".*$gdb_prompt $" {
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        fail "re-load generated corefile"
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    }
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    timeout {
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        fail "re-load generated corefile (timeout)"
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    }
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}
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for {set i 0} {$i < 32} {incr i 1} {
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    gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file"
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}
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for {set i 32} {$i < 64} {incr i 1} {
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    gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file"
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}

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