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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [newlib-1.18.0/] [newlib-1.18.0-or32-1.0rc1/] [libgloss/] [bfin/] [include/] [defBF54x_base.h] - Blame information for rev 345

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Line No. Rev Author Line
1 207 jeremybenn 
/*
2 
 * The authors hereby grant permission to use, copy, modify, distribute,
3 
 * and license this software and its documentation for any purpose, provided
4 
 * that existing copyright notices are retained in all copies and that this
5 
 * notice is included verbatim in any distributions. No written agreement,
6 
 * license, or royalty fee is required for any of the authorized uses.
7 
 * Modifications to this software may be copyrighted by their authors
8 
 * and need not follow the licensing terms described here, provided that
9 
 * the new terms are clearly indicated on the first page of each file where
10 
 * they apply.
11 
 */
12 
 
13 
/*
14 
** defBF54x_base.h
15 
**
16 
** Copyright (C) 2008, 2009 Analog Devices, Inc.
17 
**
18 
************************************************************************************
19 
**
20 
** This include file contains a list of macro "defines" to enable the programmer
21 
** to use symbolic names for the registers common to the ADSP-BF54x peripherals.
22 
**
23 
************************************************************************************
24 
** System MMR Register Map
25 
************************************************************************************/
26 
 
27 
#ifndef _DEF_BF54X_H
28 
#define _DEF_BF54X_H
29 
 
30 
#ifdef _MISRA_RULES
31 
#pragma diag(push)
32 
#pragma diag(suppress:misra_rule_19_4)
33 
#pragma diag(suppress:misra_rule_19_7)
34 
#endif /* _MISRA_RULES */
35 
 
36 
 
37 
/* ************************************************************** */
38 
/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
39 
/* ************************************************************** */
40 
 
41 
/* PLL Registers */
42 
 
43 
#define                          PLL_CTL  0xffc00000   /* PLL Control Register */
44 
#define                          PLL_DIV  0xffc00004   /* PLL Divisor Register */
45 
#define                           VR_CTL  0xffc00008   /* Voltage Regulator Control Register */
46 
#define                         PLL_STAT  0xffc0000c   /* PLL Status Register */
47 
#define                      PLL_LOCKCNT  0xffc00010   /* PLL Lock Count Register */
48 
 
49 
/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
50 
 
51 
#define                           CHIPID  0xffc00014
52 
 
53 
/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
54 
 
55 
#define                            SWRST  0xffc00100   /* Software Reset Register */
56 
#define                            SYSCR  0xffc00104   /* System Configuration register */
57 
 
58 
/* SIC Registers */
59 
 
60 
#define                       SIC_IMASK0  0xffc0010c   /* System Interrupt Mask Register 0 */
61 
#define                       SIC_IMASK1  0xffc00110   /* System Interrupt Mask Register 1 */
62 
#define                       SIC_IMASK2  0xffc00114   /* System Interrupt Mask Register 2 */
63 
#define                         SIC_ISR0  0xffc00118   /* System Interrupt Status Register 0 */
64 
#define                         SIC_ISR1  0xffc0011c   /* System Interrupt Status Register 1 */
65 
#define                         SIC_ISR2  0xffc00120   /* System Interrupt Status Register 2 */
66 
#define                         SIC_IWR0  0xffc00124   /* System Interrupt Wakeup Register 0 */
67 
#define                         SIC_IWR1  0xffc00128   /* System Interrupt Wakeup Register 1 */
68 
#define                         SIC_IWR2  0xffc0012c   /* System Interrupt Wakeup Register 2 */
69 
#define                         SIC_IAR0  0xffc00130   /* System Interrupt Assignment Register 0 */
70 
#define                         SIC_IAR1  0xffc00134   /* System Interrupt Assignment Register 1 */
71 
#define                         SIC_IAR2  0xffc00138   /* System Interrupt Assignment Register 2 */
72 
#define                         SIC_IAR3  0xffc0013c   /* System Interrupt Assignment Register 3 */
73 
#define                         SIC_IAR4  0xffc00140   /* System Interrupt Assignment Register 4 */
74 
#define                         SIC_IAR5  0xffc00144   /* System Interrupt Assignment Register 5 */
75 
#define                         SIC_IAR6  0xffc00148   /* System Interrupt Assignment Register 6 */
76 
#define                         SIC_IAR7  0xffc0014c   /* System Interrupt Assignment Register 7 */
77 
#define                         SIC_IAR8  0xffc00150   /* System Interrupt Assignment Register 8 */
78 
#define                         SIC_IAR9  0xffc00154   /* System Interrupt Assignment Register 9 */
79 
#define                        SIC_IAR10  0xffc00158   /* System Interrupt Assignment Register 10 */
80 
#define                        SIC_IAR11  0xffc0015c   /* System Interrupt Assignment Register 11 */
81 
 
82 
/* Watchdog Timer Registers */
83 
 
84 
#define                         WDOG_CTL  0xffc00200   /* Watchdog Control Register */
85 
#define                         WDOG_CNT  0xffc00204   /* Watchdog Count Register */
86 
#define                        WDOG_STAT  0xffc00208   /* Watchdog Status Register */
87 
 
88 
/* RTC Registers */
89 
 
90 
#define                         RTC_STAT  0xffc00300   /* RTC Status Register */
91 
#define                         RTC_ICTL  0xffc00304   /* RTC Interrupt Control Register */
92 
#define                        RTC_ISTAT  0xffc00308   /* RTC Interrupt Status Register */
93 
#define                        RTC_SWCNT  0xffc0030c   /* RTC Stopwatch Count Register */
94 
#define                        RTC_ALARM  0xffc00310   /* RTC Alarm Register */
95 
#define                         RTC_PREN  0xffc00314   /* RTC Prescaler Enable Register */
96 
 
97 
/* UART0 Registers */
98 
 
99 
#define                        UART0_DLL  0xffc00400   /* Divisor Latch Low Byte */
100 
#define                        UART0_DLH  0xffc00404   /* Divisor Latch High Byte */
101 
#define                       UART0_GCTL  0xffc00408   /* Global Control Register */
102 
#define                        UART0_LCR  0xffc0040c   /* Line Control Register */
103 
#define                        UART0_MCR  0xffc00410   /* Modem Control Register */
104 
#define                        UART0_LSR  0xffc00414   /* Line Status Register */
105 
#define                        UART0_MSR  0xffc00418   /* Modem Status Register */
106 
#define                        UART0_SCR  0xffc0041c   /* Scratch Register */
107 
#define                    UART0_IER_SET  0xffc00420   /* Interrupt Enable Register Set */
108 
#define                  UART0_IER_CLEAR  0xffc00424   /* Interrupt Enable Register Clear */
109 
#define                        UART0_THR  0xffc00428   /* Transmit Hold Register */
110 
#define                        UART0_RBR  0xffc0042c   /* Receive Buffer Register */
111 
 
112 
/* SPI0 Registers */
113 
 
114 
#define                         SPI0_CTL  0xffc00500   /* SPI0 Control Register */
115 
#define                         SPI0_FLG  0xffc00504   /* SPI0 Flag Register */
116 
#define                        SPI0_STAT  0xffc00508   /* SPI0 Status Register */
117 
#define                        SPI0_TDBR  0xffc0050c   /* SPI0 Transmit Data Buffer Register */
118 
#define                        SPI0_RDBR  0xffc00510   /* SPI0 Receive Data Buffer Register */
119 
#define                        SPI0_BAUD  0xffc00514   /* SPI0 Baud Rate Register */
120 
#define                      SPI0_SHADOW  0xffc00518   /* SPI0 Receive Data Buffer Shadow Register */
121 
 
122 
/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
123 
 
124 
/* Two Wire Interface Registers (TWI0) */
125 
 
126 
#define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
127 
#define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
128 
#define                   TWI0_SLAVE_CTL  0xffc00708   /* TWI Slave Mode Control Register */
129 
#define                  TWI0_SLAVE_STAT  0xffc0070c   /* TWI Slave Mode Status Register */
130 
#define                  TWI0_SLAVE_ADDR  0xffc00710   /* TWI Slave Mode Address Register */
131 
#define                  TWI0_MASTER_CTL  0xffc00714   /* TWI Master Mode Control Register */
132 
#define                 TWI0_MASTER_STAT  0xffc00718   /* TWI Master Mode Status Register */
133 
#define                 TWI0_MASTER_ADDR  0xffc0071c   /* TWI Master Mode Address Register */
134 
#define                    TWI0_INT_STAT  0xffc00720   /* TWI Interrupt Status Register */
135 
#define                    TWI0_INT_MASK  0xffc00724   /* TWI Interrupt Mask Register */
136 
#define                    TWI0_FIFO_CTL  0xffc00728   /* TWI FIFO Control Register */
137 
#define                   TWI0_FIFO_STAT  0xffc0072c   /* TWI FIFO Status Register */
138 
#define                   TWI0_XMT_DATA8  0xffc00780   /* TWI FIFO Transmit Data Single Byte Register */
139 
#define                  TWI0_XMT_DATA16  0xffc00784   /* TWI FIFO Transmit Data Double Byte Register */
140 
#define                   TWI0_RCV_DATA8  0xffc00788   /* TWI FIFO Receive Data Single Byte Register */
141 
#define                  TWI0_RCV_DATA16  0xffc0078c   /* TWI FIFO Receive Data Double Byte Register */
142 
 
143 
/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
144 
 
145 
/* SPORT1 Registers */
146 
 
147 
#define                      SPORT1_TCR1  0xffc00900   /* SPORT1 Transmit Configuration 1 Register */
148 
#define                      SPORT1_TCR2  0xffc00904   /* SPORT1 Transmit Configuration 2 Register */
149 
#define                   SPORT1_TCLKDIV  0xffc00908   /* SPORT1 Transmit Serial Clock Divider Register */
150 
#define                    SPORT1_TFSDIV  0xffc0090c   /* SPORT1 Transmit Frame Sync Divider Register */
151 
#define                        SPORT1_TX  0xffc00910   /* SPORT1 Transmit Data Register */
152 
#define                        SPORT1_RX  0xffc00918   /* SPORT1 Receive Data Register */
153 
#define                      SPORT1_RCR1  0xffc00920   /* SPORT1 Receive Configuration 1 Register */
154 
#define                      SPORT1_RCR2  0xffc00924   /* SPORT1 Receive Configuration 2 Register */
155 
#define                   SPORT1_RCLKDIV  0xffc00928   /* SPORT1 Receive Serial Clock Divider Register */
156 
#define                    SPORT1_RFSDIV  0xffc0092c   /* SPORT1 Receive Frame Sync Divider Register */
157 
#define                      SPORT1_STAT  0xffc00930   /* SPORT1 Status Register */
158 
#define                      SPORT1_CHNL  0xffc00934   /* SPORT1 Current Channel Register */
159 
#define                     SPORT1_MCMC1  0xffc00938   /* SPORT1 Multi channel Configuration Register 1 */
160 
#define                     SPORT1_MCMC2  0xffc0093c   /* SPORT1 Multi channel Configuration Register 2 */
161 
#define                     SPORT1_MTCS0  0xffc00940   /* SPORT1 Multi channel Transmit Select Register 0 */
162 
#define                     SPORT1_MTCS1  0xffc00944   /* SPORT1 Multi channel Transmit Select Register 1 */
163 
#define                     SPORT1_MTCS2  0xffc00948   /* SPORT1 Multi channel Transmit Select Register 2 */
164 
#define                     SPORT1_MTCS3  0xffc0094c   /* SPORT1 Multi channel Transmit Select Register 3 */
165 
#define                     SPORT1_MRCS0  0xffc00950   /* SPORT1 Multi channel Receive Select Register 0 */
166 
#define                     SPORT1_MRCS1  0xffc00954   /* SPORT1 Multi channel Receive Select Register 1 */
167 
#define                     SPORT1_MRCS2  0xffc00958   /* SPORT1 Multi channel Receive Select Register 2 */
168 
#define                     SPORT1_MRCS3  0xffc0095c   /* SPORT1 Multi channel Receive Select Register 3 */
169 
 
170 
/* Asynchronous Memory Control Registers */
171 
 
172 
#define                      EBIU_AMGCTL  0xffc00a00   /* Asynchronous Memory Global Control Register */
173 
#define                     EBIU_AMBCTL0  0xffc00a04   /* Asynchronous Memory Bank Control Register */
174 
#define                     EBIU_AMBCTL1  0xffc00a08   /* Asynchronous Memory Bank Control Register */
175 
#define                      EBIU_MBSCTL  0xffc00a0c   /* Asynchronous Memory Bank Select Control Register */
176 
#define                     EBIU_ARBSTAT  0xffc00a10   /* Asynchronous Memory Arbiter Status Register */
177 
#define                        EBIU_MODE  0xffc00a14   /* Asynchronous Mode Control Register */
178 
#define                        EBIU_FCTL  0xffc00a18   /* Asynchronous Memory Flash Control Register */
179 
 
180 
/* DDR Memory Control Registers */
181 
 
182 
#define                     EBIU_DDRCTL0  0xffc00a20   /* DDR Memory Control 0 Register */
183 
#define                     EBIU_DDRCTL1  0xffc00a24   /* DDR Memory Control 1 Register */
184 
#define                     EBIU_DDRCTL2  0xffc00a28   /* DDR Memory Control 2 Register */
185 
#define                     EBIU_DDRCTL3  0xffc00a2c   /* DDR Memory Control 3 Register */
186 
#define                      EBIU_DDRQUE  0xffc00a30   /* DDR Queue Configuration Register */
187 
#define                      EBIU_ERRADD  0xffc00a34   /* DDR Error Address Register */
188 
#define                      EBIU_ERRMST  0xffc00a38   /* DDR Error Master Register */
189 
#define                      EBIU_RSTCTL  0xffc00a3c   /* DDR Reset Control Register */
190 
 
191 
/* DDR BankRead and Write Count Registers */
192 
 
193 
#define                     EBIU_DDRBRC0  0xffc00a60   /* DDR Bank0 Read Count Register */
194 
#define                     EBIU_DDRBRC1  0xffc00a64   /* DDR Bank1 Read Count Register */
195 
#define                     EBIU_DDRBRC2  0xffc00a68   /* DDR Bank2 Read Count Register */
196 
#define                     EBIU_DDRBRC3  0xffc00a6c   /* DDR Bank3 Read Count Register */
197 
#define                     EBIU_DDRBRC4  0xffc00a70   /* DDR Bank4 Read Count Register */
198 
#define                     EBIU_DDRBRC5  0xffc00a74   /* DDR Bank5 Read Count Register */
199 
#define                     EBIU_DDRBRC6  0xffc00a78   /* DDR Bank6 Read Count Register */
200 
#define                     EBIU_DDRBRC7  0xffc00a7c   /* DDR Bank7 Read Count Register */
201 
#define                     EBIU_DDRBWC0  0xffc00a80   /* DDR Bank0 Write Count Register */
202 
#define                     EBIU_DDRBWC1  0xffc00a84   /* DDR Bank1 Write Count Register */
203 
#define                     EBIU_DDRBWC2  0xffc00a88   /* DDR Bank2 Write Count Register */
204 
#define                     EBIU_DDRBWC3  0xffc00a8c   /* DDR Bank3 Write Count Register */
205 
#define                     EBIU_DDRBWC4  0xffc00a90   /* DDR Bank4 Write Count Register */
206 
#define                     EBIU_DDRBWC5  0xffc00a94   /* DDR Bank5 Write Count Register */
207 
#define                     EBIU_DDRBWC6  0xffc00a98   /* DDR Bank6 Write Count Register */
208 
#define                     EBIU_DDRBWC7  0xffc00a9c   /* DDR Bank7 Write Count Register */
209 
#define                     EBIU_DDRACCT  0xffc00aa0   /* DDR Activation Count Register */
210 
#define                     EBIU_DDRTACT  0xffc00aa8   /* DDR Turn Around Count Register */
211 
#define                     EBIU_DDRARCT  0xffc00aac   /* DDR Auto-refresh Count Register */
212 
#define                      EBIU_DDRGC0  0xffc00ab0   /* DDR Grant Count 0 Register */
213 
#define                      EBIU_DDRGC1  0xffc00ab4   /* DDR Grant Count 1 Register */
214 
#define                      EBIU_DDRGC2  0xffc00ab8   /* DDR Grant Count 2 Register */
215 
#define                      EBIU_DDRGC3  0xffc00abc   /* DDR Grant Count 3 Register */
216 
#define                     EBIU_DDRMCEN  0xffc00ac0   /* DDR Metrics Counter Enable Register */
217 
#define                     EBIU_DDRMCCL  0xffc00ac4   /* DDR Metrics Counter Clear Register */
218 
 
219 
/* DMAC0 Registers */
220 
 
221 
#define                      DMAC0_TCPER  0xffc00b0c   /* DMA Controller 0 Traffic Control Periods Register */
222 
#define                      DMAC0_TCCNT  0xffc00b10   /* DMA Controller 0 Current Counts Register */
223 
 
224 
/* DMA Channel 0 Registers */
225 
 
226 
#define               DMA0_NEXT_DESC_PTR  0xffc00c00   /* DMA Channel 0 Next Descriptor Pointer Register */
227 
#define                  DMA0_START_ADDR  0xffc00c04   /* DMA Channel 0 Start Address Register */
228 
#define                      DMA0_CONFIG  0xffc00c08   /* DMA Channel 0 Configuration Register */
229 
#define                     DMA0_X_COUNT  0xffc00c10   /* DMA Channel 0 X Count Register */
230 
#define                    DMA0_X_MODIFY  0xffc00c14   /* DMA Channel 0 X Modify Register */
231 
#define                     DMA0_Y_COUNT  0xffc00c18   /* DMA Channel 0 Y Count Register */
232 
#define                    DMA0_Y_MODIFY  0xffc00c1c   /* DMA Channel 0 Y Modify Register */
233 
#define               DMA0_CURR_DESC_PTR  0xffc00c20   /* DMA Channel 0 Current Descriptor Pointer Register */
234 
#define                   DMA0_CURR_ADDR  0xffc00c24   /* DMA Channel 0 Current Address Register */
235 
#define                  DMA0_IRQ_STATUS  0xffc00c28   /* DMA Channel 0 Interrupt/Status Register */
236 
#define              DMA0_PERIPHERAL_MAP  0xffc00c2c   /* DMA Channel 0 Peripheral Map Register */
237 
#define                DMA0_CURR_X_COUNT  0xffc00c30   /* DMA Channel 0 Current X Count Register */
238 
#define                DMA0_CURR_Y_COUNT  0xffc00c38   /* DMA Channel 0 Current Y Count Register */
239 
 
240 
/* DMA Channel 1 Registers */
241 
 
242 
#define               DMA1_NEXT_DESC_PTR  0xffc00c40   /* DMA Channel 1 Next Descriptor Pointer Register */
243 
#define                  DMA1_START_ADDR  0xffc00c44   /* DMA Channel 1 Start Address Register */
244 
#define                      DMA1_CONFIG  0xffc00c48   /* DMA Channel 1 Configuration Register */
245 
#define                     DMA1_X_COUNT  0xffc00c50   /* DMA Channel 1 X Count Register */
246 
#define                    DMA1_X_MODIFY  0xffc00c54   /* DMA Channel 1 X Modify Register */
247 
#define                     DMA1_Y_COUNT  0xffc00c58   /* DMA Channel 1 Y Count Register */
248 
#define                    DMA1_Y_MODIFY  0xffc00c5c   /* DMA Channel 1 Y Modify Register */
249 
#define               DMA1_CURR_DESC_PTR  0xffc00c60   /* DMA Channel 1 Current Descriptor Pointer Register */
250 
#define                   DMA1_CURR_ADDR  0xffc00c64   /* DMA Channel 1 Current Address Register */
251 
#define                  DMA1_IRQ_STATUS  0xffc00c68   /* DMA Channel 1 Interrupt/Status Register */
252 
#define              DMA1_PERIPHERAL_MAP  0xffc00c6c   /* DMA Channel 1 Peripheral Map Register */
253 
#define                DMA1_CURR_X_COUNT  0xffc00c70   /* DMA Channel 1 Current X Count Register */
254 
#define                DMA1_CURR_Y_COUNT  0xffc00c78   /* DMA Channel 1 Current Y Count Register */
255 
 
256 
/* DMA Channel 2 Registers */
257 
 
258 
#define               DMA2_NEXT_DESC_PTR  0xffc00c80   /* DMA Channel 2 Next Descriptor Pointer Register */
259 
#define                  DMA2_START_ADDR  0xffc00c84   /* DMA Channel 2 Start Address Register */
260 
#define                      DMA2_CONFIG  0xffc00c88   /* DMA Channel 2 Configuration Register */
261 
#define                     DMA2_X_COUNT  0xffc00c90   /* DMA Channel 2 X Count Register */
262 
#define                    DMA2_X_MODIFY  0xffc00c94   /* DMA Channel 2 X Modify Register */
263 
#define                     DMA2_Y_COUNT  0xffc00c98   /* DMA Channel 2 Y Count Register */
264 
#define                    DMA2_Y_MODIFY  0xffc00c9c   /* DMA Channel 2 Y Modify Register */
265 
#define               DMA2_CURR_DESC_PTR  0xffc00ca0   /* DMA Channel 2 Current Descriptor Pointer Register */
266 
#define                   DMA2_CURR_ADDR  0xffc00ca4   /* DMA Channel 2 Current Address Register */
267 
#define                  DMA2_IRQ_STATUS  0xffc00ca8   /* DMA Channel 2 Interrupt/Status Register */
268 
#define              DMA2_PERIPHERAL_MAP  0xffc00cac   /* DMA Channel 2 Peripheral Map Register */
269 
#define                DMA2_CURR_X_COUNT  0xffc00cb0   /* DMA Channel 2 Current X Count Register */
270 
#define                DMA2_CURR_Y_COUNT  0xffc00cb8   /* DMA Channel 2 Current Y Count Register */
271 
 
272 
/* DMA Channel 3 Registers */
273 
 
274 
#define               DMA3_NEXT_DESC_PTR  0xffc00cc0   /* DMA Channel 3 Next Descriptor Pointer Register */
275 
#define                  DMA3_START_ADDR  0xffc00cc4   /* DMA Channel 3 Start Address Register */
276 
#define                      DMA3_CONFIG  0xffc00cc8   /* DMA Channel 3 Configuration Register */
277 
#define                     DMA3_X_COUNT  0xffc00cd0   /* DMA Channel 3 X Count Register */
278 
#define                    DMA3_X_MODIFY  0xffc00cd4   /* DMA Channel 3 X Modify Register */
279 
#define                     DMA3_Y_COUNT  0xffc00cd8   /* DMA Channel 3 Y Count Register */
280 
#define                    DMA3_Y_MODIFY  0xffc00cdc   /* DMA Channel 3 Y Modify Register */
281 
#define               DMA3_CURR_DESC_PTR  0xffc00ce0   /* DMA Channel 3 Current Descriptor Pointer Register */
282 
#define                   DMA3_CURR_ADDR  0xffc00ce4   /* DMA Channel 3 Current Address Register */
283 
#define                  DMA3_IRQ_STATUS  0xffc00ce8   /* DMA Channel 3 Interrupt/Status Register */
284 
#define              DMA3_PERIPHERAL_MAP  0xffc00cec   /* DMA Channel 3 Peripheral Map Register */
285 
#define                DMA3_CURR_X_COUNT  0xffc00cf0   /* DMA Channel 3 Current X Count Register */
286 
#define                DMA3_CURR_Y_COUNT  0xffc00cf8   /* DMA Channel 3 Current Y Count Register */
287 
 
288 
/* DMA Channel 4 Registers */
289 
 
290 
#define               DMA4_NEXT_DESC_PTR  0xffc00d00   /* DMA Channel 4 Next Descriptor Pointer Register */
291 
#define                  DMA4_START_ADDR  0xffc00d04   /* DMA Channel 4 Start Address Register */
292 
#define                      DMA4_CONFIG  0xffc00d08   /* DMA Channel 4 Configuration Register */
293 
#define                     DMA4_X_COUNT  0xffc00d10   /* DMA Channel 4 X Count Register */
294 
#define                    DMA4_X_MODIFY  0xffc00d14   /* DMA Channel 4 X Modify Register */
295 
#define                     DMA4_Y_COUNT  0xffc00d18   /* DMA Channel 4 Y Count Register */
296 
#define                    DMA4_Y_MODIFY  0xffc00d1c   /* DMA Channel 4 Y Modify Register */
297 
#define               DMA4_CURR_DESC_PTR  0xffc00d20   /* DMA Channel 4 Current Descriptor Pointer Register */
298 
#define                   DMA4_CURR_ADDR  0xffc00d24   /* DMA Channel 4 Current Address Register */
299 
#define                  DMA4_IRQ_STATUS  0xffc00d28   /* DMA Channel 4 Interrupt/Status Register */
300 
#define              DMA4_PERIPHERAL_MAP  0xffc00d2c   /* DMA Channel 4 Peripheral Map Register */
301 
#define                DMA4_CURR_X_COUNT  0xffc00d30   /* DMA Channel 4 Current X Count Register */
302 
#define                DMA4_CURR_Y_COUNT  0xffc00d38   /* DMA Channel 4 Current Y Count Register */
303 
 
304 
/* DMA Channel 5 Registers */
305 
 
306 
#define               DMA5_NEXT_DESC_PTR  0xffc00d40   /* DMA Channel 5 Next Descriptor Pointer Register */
307 
#define                  DMA5_START_ADDR  0xffc00d44   /* DMA Channel 5 Start Address Register */
308 
#define                      DMA5_CONFIG  0xffc00d48   /* DMA Channel 5 Configuration Register */
309 
#define                     DMA5_X_COUNT  0xffc00d50   /* DMA Channel 5 X Count Register */
310 
#define                    DMA5_X_MODIFY  0xffc00d54   /* DMA Channel 5 X Modify Register */
311 
#define                     DMA5_Y_COUNT  0xffc00d58   /* DMA Channel 5 Y Count Register */
312 
#define                    DMA5_Y_MODIFY  0xffc00d5c   /* DMA Channel 5 Y Modify Register */
313 
#define               DMA5_CURR_DESC_PTR  0xffc00d60   /* DMA Channel 5 Current Descriptor Pointer Register */
314 
#define                   DMA5_CURR_ADDR  0xffc00d64   /* DMA Channel 5 Current Address Register */
315 
#define                  DMA5_IRQ_STATUS  0xffc00d68   /* DMA Channel 5 Interrupt/Status Register */
316 
#define              DMA5_PERIPHERAL_MAP  0xffc00d6c   /* DMA Channel 5 Peripheral Map Register */
317 
#define                DMA5_CURR_X_COUNT  0xffc00d70   /* DMA Channel 5 Current X Count Register */
318 
#define                DMA5_CURR_Y_COUNT  0xffc00d78   /* DMA Channel 5 Current Y Count Register */
319 
 
320 
/* DMA Channel 6 Registers */
321 
 
322 
#define               DMA6_NEXT_DESC_PTR  0xffc00d80   /* DMA Channel 6 Next Descriptor Pointer Register */
323 
#define                  DMA6_START_ADDR  0xffc00d84   /* DMA Channel 6 Start Address Register */
324 
#define                      DMA6_CONFIG  0xffc00d88   /* DMA Channel 6 Configuration Register */
325 
#define                     DMA6_X_COUNT  0xffc00d90   /* DMA Channel 6 X Count Register */
326 
#define                    DMA6_X_MODIFY  0xffc00d94   /* DMA Channel 6 X Modify Register */
327 
#define                     DMA6_Y_COUNT  0xffc00d98   /* DMA Channel 6 Y Count Register */
328 
#define                    DMA6_Y_MODIFY  0xffc00d9c   /* DMA Channel 6 Y Modify Register */
329 
#define               DMA6_CURR_DESC_PTR  0xffc00da0   /* DMA Channel 6 Current Descriptor Pointer Register */
330 
#define                   DMA6_CURR_ADDR  0xffc00da4   /* DMA Channel 6 Current Address Register */
331 
#define                  DMA6_IRQ_STATUS  0xffc00da8   /* DMA Channel 6 Interrupt/Status Register */
332 
#define              DMA6_PERIPHERAL_MAP  0xffc00dac   /* DMA Channel 6 Peripheral Map Register */
333 
#define                DMA6_CURR_X_COUNT  0xffc00db0   /* DMA Channel 6 Current X Count Register */
334 
#define                DMA6_CURR_Y_COUNT  0xffc00db8   /* DMA Channel 6 Current Y Count Register */
335 
 
336 
/* DMA Channel 7 Registers */
337 
 
338 
#define               DMA7_NEXT_DESC_PTR  0xffc00dc0   /* DMA Channel 7 Next Descriptor Pointer Register */
339 
#define                  DMA7_START_ADDR  0xffc00dc4   /* DMA Channel 7 Start Address Register */
340 
#define                      DMA7_CONFIG  0xffc00dc8   /* DMA Channel 7 Configuration Register */
341 
#define                     DMA7_X_COUNT  0xffc00dd0   /* DMA Channel 7 X Count Register */
342 
#define                    DMA7_X_MODIFY  0xffc00dd4   /* DMA Channel 7 X Modify Register */
343 
#define                     DMA7_Y_COUNT  0xffc00dd8   /* DMA Channel 7 Y Count Register */
344 
#define                    DMA7_Y_MODIFY  0xffc00ddc   /* DMA Channel 7 Y Modify Register */
345 
#define               DMA7_CURR_DESC_PTR  0xffc00de0   /* DMA Channel 7 Current Descriptor Pointer Register */
346 
#define                   DMA7_CURR_ADDR  0xffc00de4   /* DMA Channel 7 Current Address Register */
347 
#define                  DMA7_IRQ_STATUS  0xffc00de8   /* DMA Channel 7 Interrupt/Status Register */
348 
#define              DMA7_PERIPHERAL_MAP  0xffc00dec   /* DMA Channel 7 Peripheral Map Register */
349 
#define                DMA7_CURR_X_COUNT  0xffc00df0   /* DMA Channel 7 Current X Count Register */
350 
#define                DMA7_CURR_Y_COUNT  0xffc00df8   /* DMA Channel 7 Current Y Count Register */
351 
 
352 
/* DMA Channel 8 Registers */
353 
 
354 
#define               DMA8_NEXT_DESC_PTR  0xffc00e00   /* DMA Channel 8 Next Descriptor Pointer Register */
355 
#define                  DMA8_START_ADDR  0xffc00e04   /* DMA Channel 8 Start Address Register */
356 
#define                      DMA8_CONFIG  0xffc00e08   /* DMA Channel 8 Configuration Register */
357 
#define                     DMA8_X_COUNT  0xffc00e10   /* DMA Channel 8 X Count Register */
358 
#define                    DMA8_X_MODIFY  0xffc00e14   /* DMA Channel 8 X Modify Register */
359 
#define                     DMA8_Y_COUNT  0xffc00e18   /* DMA Channel 8 Y Count Register */
360 
#define                    DMA8_Y_MODIFY  0xffc00e1c   /* DMA Channel 8 Y Modify Register */
361 
#define               DMA8_CURR_DESC_PTR  0xffc00e20   /* DMA Channel 8 Current Descriptor Pointer Register */
362 
#define                   DMA8_CURR_ADDR  0xffc00e24   /* DMA Channel 8 Current Address Register */
363 
#define                  DMA8_IRQ_STATUS  0xffc00e28   /* DMA Channel 8 Interrupt/Status Register */
364 
#define              DMA8_PERIPHERAL_MAP  0xffc00e2c   /* DMA Channel 8 Peripheral Map Register */
365 
#define                DMA8_CURR_X_COUNT  0xffc00e30   /* DMA Channel 8 Current X Count Register */
366 
#define                DMA8_CURR_Y_COUNT  0xffc00e38   /* DMA Channel 8 Current Y Count Register */
367 
 
368 
/* DMA Channel 9 Registers */
369 
 
370 
#define               DMA9_NEXT_DESC_PTR  0xffc00e40   /* DMA Channel 9 Next Descriptor Pointer Register */
371 
#define                  DMA9_START_ADDR  0xffc00e44   /* DMA Channel 9 Start Address Register */
372 
#define                      DMA9_CONFIG  0xffc00e48   /* DMA Channel 9 Configuration Register */
373 
#define                     DMA9_X_COUNT  0xffc00e50   /* DMA Channel 9 X Count Register */
374 
#define                    DMA9_X_MODIFY  0xffc00e54   /* DMA Channel 9 X Modify Register */
375 
#define                     DMA9_Y_COUNT  0xffc00e58   /* DMA Channel 9 Y Count Register */
376 
#define                    DMA9_Y_MODIFY  0xffc00e5c   /* DMA Channel 9 Y Modify Register */
377 
#define               DMA9_CURR_DESC_PTR  0xffc00e60   /* DMA Channel 9 Current Descriptor Pointer Register */
378 
#define                   DMA9_CURR_ADDR  0xffc00e64   /* DMA Channel 9 Current Address Register */
379 
#define                  DMA9_IRQ_STATUS  0xffc00e68   /* DMA Channel 9 Interrupt/Status Register */
380 
#define              DMA9_PERIPHERAL_MAP  0xffc00e6c   /* DMA Channel 9 Peripheral Map Register */
381 
#define                DMA9_CURR_X_COUNT  0xffc00e70   /* DMA Channel 9 Current X Count Register */
382 
#define                DMA9_CURR_Y_COUNT  0xffc00e78   /* DMA Channel 9 Current Y Count Register */
383 
 
384 
/* DMA Channel 10 Registers */
385 
 
386 
#define              DMA10_NEXT_DESC_PTR  0xffc00e80   /* DMA Channel 10 Next Descriptor Pointer Register */
387 
#define                 DMA10_START_ADDR  0xffc00e84   /* DMA Channel 10 Start Address Register */
388 
#define                     DMA10_CONFIG  0xffc00e88   /* DMA Channel 10 Configuration Register */
389 
#define                    DMA10_X_COUNT  0xffc00e90   /* DMA Channel 10 X Count Register */
390 
#define                   DMA10_X_MODIFY  0xffc00e94   /* DMA Channel 10 X Modify Register */
391 
#define                    DMA10_Y_COUNT  0xffc00e98   /* DMA Channel 10 Y Count Register */
392 
#define                   DMA10_Y_MODIFY  0xffc00e9c   /* DMA Channel 10 Y Modify Register */
393 
#define              DMA10_CURR_DESC_PTR  0xffc00ea0   /* DMA Channel 10 Current Descriptor Pointer Register */
394 
#define                  DMA10_CURR_ADDR  0xffc00ea4   /* DMA Channel 10 Current Address Register */
395 
#define                 DMA10_IRQ_STATUS  0xffc00ea8   /* DMA Channel 10 Interrupt/Status Register */
396 
#define             DMA10_PERIPHERAL_MAP  0xffc00eac   /* DMA Channel 10 Peripheral Map Register */
397 
#define               DMA10_CURR_X_COUNT  0xffc00eb0   /* DMA Channel 10 Current X Count Register */
398 
#define               DMA10_CURR_Y_COUNT  0xffc00eb8   /* DMA Channel 10 Current Y Count Register */
399 
 
400 
/* DMA Channel 11 Registers */
401 
 
402 
#define              DMA11_NEXT_DESC_PTR  0xffc00ec0   /* DMA Channel 11 Next Descriptor Pointer Register */
403 
#define                 DMA11_START_ADDR  0xffc00ec4   /* DMA Channel 11 Start Address Register */
404 
#define                     DMA11_CONFIG  0xffc00ec8   /* DMA Channel 11 Configuration Register */
405 
#define                    DMA11_X_COUNT  0xffc00ed0   /* DMA Channel 11 X Count Register */
406 
#define                   DMA11_X_MODIFY  0xffc00ed4   /* DMA Channel 11 X Modify Register */
407 
#define                    DMA11_Y_COUNT  0xffc00ed8   /* DMA Channel 11 Y Count Register */
408 
#define                   DMA11_Y_MODIFY  0xffc00edc   /* DMA Channel 11 Y Modify Register */
409 
#define              DMA11_CURR_DESC_PTR  0xffc00ee0   /* DMA Channel 11 Current Descriptor Pointer Register */
410 
#define                  DMA11_CURR_ADDR  0xffc00ee4   /* DMA Channel 11 Current Address Register */
411 
#define                 DMA11_IRQ_STATUS  0xffc00ee8   /* DMA Channel 11 Interrupt/Status Register */
412 
#define             DMA11_PERIPHERAL_MAP  0xffc00eec   /* DMA Channel 11 Peripheral Map Register */
413 
#define               DMA11_CURR_X_COUNT  0xffc00ef0   /* DMA Channel 11 Current X Count Register */
414 
#define               DMA11_CURR_Y_COUNT  0xffc00ef8   /* DMA Channel 11 Current Y Count Register */
415 
 
416 
/* MDMA Stream 0 Registers */
417 
 
418 
#define            MDMA_D0_NEXT_DESC_PTR  0xffc00f00   /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
419 
#define               MDMA_D0_START_ADDR  0xffc00f04   /* Memory DMA Stream 0 Destination Start Address Register */
420 
#define                   MDMA_D0_CONFIG  0xffc00f08   /* Memory DMA Stream 0 Destination Configuration Register */
421 
#define                  MDMA_D0_X_COUNT  0xffc00f10   /* Memory DMA Stream 0 Destination X Count Register */
422 
#define                 MDMA_D0_X_MODIFY  0xffc00f14   /* Memory DMA Stream 0 Destination X Modify Register */
423 
#define                  MDMA_D0_Y_COUNT  0xffc00f18   /* Memory DMA Stream 0 Destination Y Count Register */
424 
#define                 MDMA_D0_Y_MODIFY  0xffc00f1c   /* Memory DMA Stream 0 Destination Y Modify Register */
425 
#define            MDMA_D0_CURR_DESC_PTR  0xffc00f20   /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
426 
#define                MDMA_D0_CURR_ADDR  0xffc00f24   /* Memory DMA Stream 0 Destination Current Address Register */
427 
#define               MDMA_D0_IRQ_STATUS  0xffc00f28   /* Memory DMA Stream 0 Destination Interrupt/Status Register */
428 
#define           MDMA_D0_PERIPHERAL_MAP  0xffc00f2c   /* Memory DMA Stream 0 Destination Peripheral Map Register */
429 
#define             MDMA_D0_CURR_X_COUNT  0xffc00f30   /* Memory DMA Stream 0 Destination Current X Count Register */
430 
#define             MDMA_D0_CURR_Y_COUNT  0xffc00f38   /* Memory DMA Stream 0 Destination Current Y Count Register */
431 
#define            MDMA_S0_NEXT_DESC_PTR  0xffc00f40   /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
432 
#define               MDMA_S0_START_ADDR  0xffc00f44   /* Memory DMA Stream 0 Source Start Address Register */
433 
#define                   MDMA_S0_CONFIG  0xffc00f48   /* Memory DMA Stream 0 Source Configuration Register */
434 
#define                  MDMA_S0_X_COUNT  0xffc00f50   /* Memory DMA Stream 0 Source X Count Register */
435 
#define                 MDMA_S0_X_MODIFY  0xffc00f54   /* Memory DMA Stream 0 Source X Modify Register */
436 
#define                  MDMA_S0_Y_COUNT  0xffc00f58   /* Memory DMA Stream 0 Source Y Count Register */
437 
#define                 MDMA_S0_Y_MODIFY  0xffc00f5c   /* Memory DMA Stream 0 Source Y Modify Register */
438 
#define            MDMA_S0_CURR_DESC_PTR  0xffc00f60   /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
439 
#define                MDMA_S0_CURR_ADDR  0xffc00f64   /* Memory DMA Stream 0 Source Current Address Register */
440 
#define               MDMA_S0_IRQ_STATUS  0xffc00f68   /* Memory DMA Stream 0 Source Interrupt/Status Register */
441 
#define           MDMA_S0_PERIPHERAL_MAP  0xffc00f6c   /* Memory DMA Stream 0 Source Peripheral Map Register */
442 
#define             MDMA_S0_CURR_X_COUNT  0xffc00f70   /* Memory DMA Stream 0 Source Current X Count Register */
443 
#define             MDMA_S0_CURR_Y_COUNT  0xffc00f78   /* Memory DMA Stream 0 Source Current Y Count Register */
444 
 
445 
/* MDMA Stream 1 Registers */
446 
 
447 
#define            MDMA_D1_NEXT_DESC_PTR  0xffc00f80   /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
448 
#define               MDMA_D1_START_ADDR  0xffc00f84   /* Memory DMA Stream 1 Destination Start Address Register */
449 
#define                   MDMA_D1_CONFIG  0xffc00f88   /* Memory DMA Stream 1 Destination Configuration Register */
450 
#define                  MDMA_D1_X_COUNT  0xffc00f90   /* Memory DMA Stream 1 Destination X Count Register */
451 
#define                 MDMA_D1_X_MODIFY  0xffc00f94   /* Memory DMA Stream 1 Destination X Modify Register */
452 
#define                  MDMA_D1_Y_COUNT  0xffc00f98   /* Memory DMA Stream 1 Destination Y Count Register */
453 
#define                 MDMA_D1_Y_MODIFY  0xffc00f9c   /* Memory DMA Stream 1 Destination Y Modify Register */
454 
#define            MDMA_D1_CURR_DESC_PTR  0xffc00fa0   /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
455 
#define                MDMA_D1_CURR_ADDR  0xffc00fa4   /* Memory DMA Stream 1 Destination Current Address Register */
456 
#define               MDMA_D1_IRQ_STATUS  0xffc00fa8   /* Memory DMA Stream 1 Destination Interrupt/Status Register */
457 
#define           MDMA_D1_PERIPHERAL_MAP  0xffc00fac   /* Memory DMA Stream 1 Destination Peripheral Map Register */
458 
#define             MDMA_D1_CURR_X_COUNT  0xffc00fb0   /* Memory DMA Stream 1 Destination Current X Count Register */
459 
#define             MDMA_D1_CURR_Y_COUNT  0xffc00fb8   /* Memory DMA Stream 1 Destination Current Y Count Register */
460 
#define            MDMA_S1_NEXT_DESC_PTR  0xffc00fc0   /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
461 
#define               MDMA_S1_START_ADDR  0xffc00fc4   /* Memory DMA Stream 1 Source Start Address Register */
462 
#define                   MDMA_S1_CONFIG  0xffc00fc8   /* Memory DMA Stream 1 Source Configuration Register */
463 
#define                  MDMA_S1_X_COUNT  0xffc00fd0   /* Memory DMA Stream 1 Source X Count Register */
464 
#define                 MDMA_S1_X_MODIFY  0xffc00fd4   /* Memory DMA Stream 1 Source X Modify Register */
465 
#define                  MDMA_S1_Y_COUNT  0xffc00fd8   /* Memory DMA Stream 1 Source Y Count Register */
466 
#define                 MDMA_S1_Y_MODIFY  0xffc00fdc   /* Memory DMA Stream 1 Source Y Modify Register */
467 
#define            MDMA_S1_CURR_DESC_PTR  0xffc00fe0   /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
468 
#define                MDMA_S1_CURR_ADDR  0xffc00fe4   /* Memory DMA Stream 1 Source Current Address Register */
469 
#define               MDMA_S1_IRQ_STATUS  0xffc00fe8   /* Memory DMA Stream 1 Source Interrupt/Status Register */
470 
#define           MDMA_S1_PERIPHERAL_MAP  0xffc00fec   /* Memory DMA Stream 1 Source Peripheral Map Register */
471 
#define             MDMA_S1_CURR_X_COUNT  0xffc00ff0   /* Memory DMA Stream 1 Source Current X Count Register */
472 
#define             MDMA_S1_CURR_Y_COUNT  0xffc00ff8   /* Memory DMA Stream 1 Source Current Y Count Register */
473 
 
474 
/* UART3 Registers */
475 
 
476 
#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
477 
#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
478 
#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
479 
#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
480 
#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
481 
#define                        UART3_LSR  0xffc03114   /* Line Status Register */
482 
#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
483 
#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
484 
#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
485 
#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
486 
#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
487 
#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
488 
 
489 
/* EPPI1 Registers */
490 
 
491 
#define                     EPPI1_STATUS  0xffc01300   /* EPPI1 Status Register */
492 
#define                     EPPI1_HCOUNT  0xffc01304   /* EPPI1 Horizontal Transfer Count Register */
493 
#define                     EPPI1_HDELAY  0xffc01308   /* EPPI1 Horizontal Delay Count Register */
494 
#define                     EPPI1_VCOUNT  0xffc0130c   /* EPPI1 Vertical Transfer Count Register */
495 
#define                     EPPI1_VDELAY  0xffc01310   /* EPPI1 Vertical Delay Count Register */
496 
#define                      EPPI1_FRAME  0xffc01314   /* EPPI1 Lines per Frame Register */
497 
#define                       EPPI1_LINE  0xffc01318   /* EPPI1 Samples per Line Register */
498 
#define                     EPPI1_CLKDIV  0xffc0131c   /* EPPI1 Clock Divide Register */
499 
#define                    EPPI1_CONTROL  0xffc01320   /* EPPI1 Control Register */
500 
#define                   EPPI1_FS1W_HBL  0xffc01324   /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
501 
#define                  EPPI1_FS1P_AVPL  0xffc01328   /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
502 
#define                   EPPI1_FS2W_LVB  0xffc0132c   /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
503 
#define                  EPPI1_FS2P_LAVF  0xffc01330   /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
504 
#define                       EPPI1_CLIP  0xffc01334   /* EPPI1 Clipping Register */
505 
 
506 
/* Port Interrupt 0 Registers (32-bit) */
507 
 
508 
#define                   PINT0_MASK_SET  0xffc01400   /* Pin Interrupt 0 Mask Set Register */
509 
#define                 PINT0_MASK_CLEAR  0xffc01404   /* Pin Interrupt 0 Mask Clear Register */
510 
#define                    PINT0_REQUEST  0xffc01408   /* Pin Interrupt 0 Interrupt Request Register */
511 
#define                     PINT0_ASSIGN  0xffc0140c   /* Pin Interrupt 0 Port Assign Register */
512 
#define                   PINT0_EDGE_SET  0xffc01410   /* Pin Interrupt 0 Edge-sensitivity Set Register */
513 
#define                 PINT0_EDGE_CLEAR  0xffc01414   /* Pin Interrupt 0 Edge-sensitivity Clear Register */
514 
#define                 PINT0_INVERT_SET  0xffc01418   /* Pin Interrupt 0 Inversion Set Register */
515 
#define               PINT0_INVERT_CLEAR  0xffc0141c   /* Pin Interrupt 0 Inversion Clear Register */
516 
#define                   PINT0_PINSTATE  0xffc01420   /* Pin Interrupt 0 Pin Status Register */
517 
#define                      PINT0_LATCH  0xffc01424   /* Pin Interrupt 0 Latch Register */
518 
 
519 
/* Port Interrupt 1 Registers (32-bit) */
520 
 
521 
#define                   PINT1_MASK_SET  0xffc01430   /* Pin Interrupt 1 Mask Set Register */
522 
#define                 PINT1_MASK_CLEAR  0xffc01434   /* Pin Interrupt 1 Mask Clear Register */
523 
#define                    PINT1_REQUEST  0xffc01438   /* Pin Interrupt 1 Interrupt Request Register */
524 
#define                     PINT1_ASSIGN  0xffc0143c   /* Pin Interrupt 1 Port Assign Register */
525 
#define                   PINT1_EDGE_SET  0xffc01440   /* Pin Interrupt 1 Edge-sensitivity Set Register */
526 
#define                 PINT1_EDGE_CLEAR  0xffc01444   /* Pin Interrupt 1 Edge-sensitivity Clear Register */
527 
#define                 PINT1_INVERT_SET  0xffc01448   /* Pin Interrupt 1 Inversion Set Register */
528 
#define               PINT1_INVERT_CLEAR  0xffc0144c   /* Pin Interrupt 1 Inversion Clear Register */
529 
#define                   PINT1_PINSTATE  0xffc01450   /* Pin Interrupt 1 Pin Status Register */
530 
#define                      PINT1_LATCH  0xffc01454   /* Pin Interrupt 1 Latch Register */
531 
 
532 
/* Port Interrupt 2 Registers (32-bit) */
533 
 
534 
#define                   PINT2_MASK_SET  0xffc01460   /* Pin Interrupt 2 Mask Set Register */
535 
#define                 PINT2_MASK_CLEAR  0xffc01464   /* Pin Interrupt 2 Mask Clear Register */
536 
#define                    PINT2_REQUEST  0xffc01468   /* Pin Interrupt 2 Interrupt Request Register */
537 
#define                     PINT2_ASSIGN  0xffc0146c   /* Pin Interrupt 2 Port Assign Register */
538 
#define                   PINT2_EDGE_SET  0xffc01470   /* Pin Interrupt 2 Edge-sensitivity Set Register */
539 
#define                 PINT2_EDGE_CLEAR  0xffc01474   /* Pin Interrupt 2 Edge-sensitivity Clear Register */
540 
#define                 PINT2_INVERT_SET  0xffc01478   /* Pin Interrupt 2 Inversion Set Register */
541 
#define               PINT2_INVERT_CLEAR  0xffc0147c   /* Pin Interrupt 2 Inversion Clear Register */
542 
#define                   PINT2_PINSTATE  0xffc01480   /* Pin Interrupt 2 Pin Status Register */
543 
#define                      PINT2_LATCH  0xffc01484   /* Pin Interrupt 2 Latch Register */
544 
 
545 
/* Port Interrupt 3 Registers (32-bit) */
546 
 
547 
#define                   PINT3_MASK_SET  0xffc01490   /* Pin Interrupt 3 Mask Set Register */
548 
#define                 PINT3_MASK_CLEAR  0xffc01494   /* Pin Interrupt 3 Mask Clear Register */
549 
#define                    PINT3_REQUEST  0xffc01498   /* Pin Interrupt 3 Interrupt Request Register */
550 
#define                     PINT3_ASSIGN  0xffc0149c   /* Pin Interrupt 3 Port Assign Register */
551 
#define                   PINT3_EDGE_SET  0xffc014a0   /* Pin Interrupt 3 Edge-sensitivity Set Register */
552 
#define                 PINT3_EDGE_CLEAR  0xffc014a4   /* Pin Interrupt 3 Edge-sensitivity Clear Register */
553 
#define                 PINT3_INVERT_SET  0xffc014a8   /* Pin Interrupt 3 Inversion Set Register */
554 
#define               PINT3_INVERT_CLEAR  0xffc014ac   /* Pin Interrupt 3 Inversion Clear Register */
555 
#define                   PINT3_PINSTATE  0xffc014b0   /* Pin Interrupt 3 Pin Status Register */
556 
#define                      PINT3_LATCH  0xffc014b4   /* Pin Interrupt 3 Latch Register */
557 
 
558 
/* Port A Registers */
559 
 
560 
#define                        PORTA_FER  0xffc014c0   /* Function Enable Register */
561 
#define                            PORTA  0xffc014c4   /* GPIO Data Register */
562 
#define                        PORTA_SET  0xffc014c8   /* GPIO Data Set Register */
563 
#define                      PORTA_CLEAR  0xffc014cc   /* GPIO Data Clear Register */
564 
#define                    PORTA_DIR_SET  0xffc014d0   /* GPIO Direction Set Register */
565 
#define                  PORTA_DIR_CLEAR  0xffc014d4   /* GPIO Direction Clear Register */
566 
#define                       PORTA_INEN  0xffc014d8   /* GPIO Input Enable Register */
567 
#define                        PORTA_MUX  0xffc014dc   /* Multiplexer Control Register */
568 
 
569 
/* Port B Registers */
570 
 
571 
#define                        PORTB_FER  0xffc014e0   /* Function Enable Register */
572 
#define                            PORTB  0xffc014e4   /* GPIO Data Register */
573 
#define                        PORTB_SET  0xffc014e8   /* GPIO Data Set Register */
574 
#define                      PORTB_CLEAR  0xffc014ec   /* GPIO Data Clear Register */
575 
#define                    PORTB_DIR_SET  0xffc014f0   /* GPIO Direction Set Register */
576 
#define                  PORTB_DIR_CLEAR  0xffc014f4   /* GPIO Direction Clear Register */
577 
#define                       PORTB_INEN  0xffc014f8   /* GPIO Input Enable Register */
578 
#define                        PORTB_MUX  0xffc014fc   /* Multiplexer Control Register */
579 
 
580 
/* Port C Registers */
581 
 
582 
#define                        PORTC_FER  0xffc01500   /* Function Enable Register */
583 
#define                            PORTC  0xffc01504   /* GPIO Data Register */
584 
#define                        PORTC_SET  0xffc01508   /* GPIO Data Set Register */
585 
#define                      PORTC_CLEAR  0xffc0150c   /* GPIO Data Clear Register */
586 
#define                    PORTC_DIR_SET  0xffc01510   /* GPIO Direction Set Register */
587 
#define                  PORTC_DIR_CLEAR  0xffc01514   /* GPIO Direction Clear Register */
588 
#define                       PORTC_INEN  0xffc01518   /* GPIO Input Enable Register */
589 
#define                        PORTC_MUX  0xffc0151c   /* Multiplexer Control Register */
590 
 
591 
/* Port D Registers */
592 
 
593 
#define                        PORTD_FER  0xffc01520   /* Function Enable Register */
594 
#define                            PORTD  0xffc01524   /* GPIO Data Register */
595 
#define                        PORTD_SET  0xffc01528   /* GPIO Data Set Register */
596 
#define                      PORTD_CLEAR  0xffc0152c   /* GPIO Data Clear Register */
597 
#define                    PORTD_DIR_SET  0xffc01530   /* GPIO Direction Set Register */
598 
#define                  PORTD_DIR_CLEAR  0xffc01534   /* GPIO Direction Clear Register */
599 
#define                       PORTD_INEN  0xffc01538   /* GPIO Input Enable Register */
600 
#define                        PORTD_MUX  0xffc0153c   /* Multiplexer Control Register */
601 
 
602 
/* Port E Registers */
603 
 
604 
#define                        PORTE_FER  0xffc01540   /* Function Enable Register */
605 
#define                            PORTE  0xffc01544   /* GPIO Data Register */
606 
#define                        PORTE_SET  0xffc01548   /* GPIO Data Set Register */
607 
#define                      PORTE_CLEAR  0xffc0154c   /* GPIO Data Clear Register */
608 
#define                    PORTE_DIR_SET  0xffc01550   /* GPIO Direction Set Register */
609 
#define                  PORTE_DIR_CLEAR  0xffc01554   /* GPIO Direction Clear Register */
610 
#define                       PORTE_INEN  0xffc01558   /* GPIO Input Enable Register */
611 
#define                        PORTE_MUX  0xffc0155c   /* Multiplexer Control Register */
612 
 
613 
/* Port F Registers */
614 
 
615 
#define                        PORTF_FER  0xffc01560   /* Function Enable Register */
616 
#define                            PORTF  0xffc01564   /* GPIO Data Register */
617 
#define                        PORTF_SET  0xffc01568   /* GPIO Data Set Register */
618 
#define                      PORTF_CLEAR  0xffc0156c   /* GPIO Data Clear Register */
619 
#define                    PORTF_DIR_SET  0xffc01570   /* GPIO Direction Set Register */
620 
#define                  PORTF_DIR_CLEAR  0xffc01574   /* GPIO Direction Clear Register */
621 
#define                       PORTF_INEN  0xffc01578   /* GPIO Input Enable Register */
622 
#define                        PORTF_MUX  0xffc0157c   /* Multiplexer Control Register */
623 
 
624 
/* Port G Registers */
625 
 
626 
#define                        PORTG_FER  0xffc01580   /* Function Enable Register */
627 
#define                            PORTG  0xffc01584   /* GPIO Data Register */
628 
#define                        PORTG_SET  0xffc01588   /* GPIO Data Set Register */
629 
#define                      PORTG_CLEAR  0xffc0158c   /* GPIO Data Clear Register */
630 
#define                    PORTG_DIR_SET  0xffc01590   /* GPIO Direction Set Register */
631 
#define                  PORTG_DIR_CLEAR  0xffc01594   /* GPIO Direction Clear Register */
632 
#define                       PORTG_INEN  0xffc01598   /* GPIO Input Enable Register */
633 
#define                        PORTG_MUX  0xffc0159c   /* Multiplexer Control Register */
634 
 
635 
/* Port H Registers */
636 
 
637 
#define                        PORTH_FER  0xffc015a0   /* Function Enable Register */
638 
#define                            PORTH  0xffc015a4   /* GPIO Data Register */
639 
#define                        PORTH_SET  0xffc015a8   /* GPIO Data Set Register */
640 
#define                      PORTH_CLEAR  0xffc015ac   /* GPIO Data Clear Register */
641 
#define                    PORTH_DIR_SET  0xffc015b0   /* GPIO Direction Set Register */
642 
#define                  PORTH_DIR_CLEAR  0xffc015b4   /* GPIO Direction Clear Register */
643 
#define                       PORTH_INEN  0xffc015b8   /* GPIO Input Enable Register */
644 
#define                        PORTH_MUX  0xffc015bc   /* Multiplexer Control Register */
645 
 
646 
/* Port I Registers */
647 
 
648 
#define                        PORTI_FER  0xffc015c0   /* Function Enable Register */
649 
#define                            PORTI  0xffc015c4   /* GPIO Data Register */
650 
#define                        PORTI_SET  0xffc015c8   /* GPIO Data Set Register */
651 
#define                      PORTI_CLEAR  0xffc015cc   /* GPIO Data Clear Register */
652 
#define                    PORTI_DIR_SET  0xffc015d0   /* GPIO Direction Set Register */
653 
#define                  PORTI_DIR_CLEAR  0xffc015d4   /* GPIO Direction Clear Register */
654 
#define                       PORTI_INEN  0xffc015d8   /* GPIO Input Enable Register */
655 
#define                        PORTI_MUX  0xffc015dc   /* Multiplexer Control Register */
656 
 
657 
/* Port J Registers */
658 
 
659 
#define                        PORTJ_FER  0xffc015e0   /* Function Enable Register */
660 
#define                            PORTJ  0xffc015e4   /* GPIO Data Register */
661 
#define                        PORTJ_SET  0xffc015e8   /* GPIO Data Set Register */
662 
#define                      PORTJ_CLEAR  0xffc015ec   /* GPIO Data Clear Register */
663 
#define                    PORTJ_DIR_SET  0xffc015f0   /* GPIO Direction Set Register */
664 
#define                  PORTJ_DIR_CLEAR  0xffc015f4   /* GPIO Direction Clear Register */
665 
#define                       PORTJ_INEN  0xffc015f8   /* GPIO Input Enable Register */
666 
#define                        PORTJ_MUX  0xffc015fc   /* Multiplexer Control Register */
667 
 
668 
/* PWM Timer Registers */
669 
 
670 
#define                    TIMER0_CONFIG  0xffc01600   /* Timer 0 Configuration Register */
671 
#define                   TIMER0_COUNTER  0xffc01604   /* Timer 0 Counter Register */
672 
#define                    TIMER0_PERIOD  0xffc01608   /* Timer 0 Period Register */
673 
#define                     TIMER0_WIDTH  0xffc0160c   /* Timer 0 Width Register */
674 
#define                    TIMER1_CONFIG  0xffc01610   /* Timer 1 Configuration Register */
675 
#define                   TIMER1_COUNTER  0xffc01614   /* Timer 1 Counter Register */
676 
#define                    TIMER1_PERIOD  0xffc01618   /* Timer 1 Period Register */
677 
#define                     TIMER1_WIDTH  0xffc0161c   /* Timer 1 Width Register */
678 
#define                    TIMER2_CONFIG  0xffc01620   /* Timer 2 Configuration Register */
679 
#define                   TIMER2_COUNTER  0xffc01624   /* Timer 2 Counter Register */
680 
#define                    TIMER2_PERIOD  0xffc01628   /* Timer 2 Period Register */
681 
#define                     TIMER2_WIDTH  0xffc0162c   /* Timer 2 Width Register */
682 
#define                    TIMER3_CONFIG  0xffc01630   /* Timer 3 Configuration Register */
683 
#define                   TIMER3_COUNTER  0xffc01634   /* Timer 3 Counter Register */
684 
#define                    TIMER3_PERIOD  0xffc01638   /* Timer 3 Period Register */
685 
#define                     TIMER3_WIDTH  0xffc0163c   /* Timer 3 Width Register */
686 
#define                    TIMER4_CONFIG  0xffc01640   /* Timer 4 Configuration Register */
687 
#define                   TIMER4_COUNTER  0xffc01644   /* Timer 4 Counter Register */
688 
#define                    TIMER4_PERIOD  0xffc01648   /* Timer 4 Period Register */
689 
#define                     TIMER4_WIDTH  0xffc0164c   /* Timer 4 Width Register */
690 
#define                    TIMER5_CONFIG  0xffc01650   /* Timer 5 Configuration Register */
691 
#define                   TIMER5_COUNTER  0xffc01654   /* Timer 5 Counter Register */
692 
#define                    TIMER5_PERIOD  0xffc01658   /* Timer 5 Period Register */
693 
#define                     TIMER5_WIDTH  0xffc0165c   /* Timer 5 Width Register */
694 
#define                    TIMER6_CONFIG  0xffc01660   /* Timer 6 Configuration Register */
695 
#define                   TIMER6_COUNTER  0xffc01664   /* Timer 6 Counter Register */
696 
#define                    TIMER6_PERIOD  0xffc01668   /* Timer 6 Period Register */
697 
#define                     TIMER6_WIDTH  0xffc0166c   /* Timer 6 Width Register */
698 
#define                    TIMER7_CONFIG  0xffc01670   /* Timer 7 Configuration Register */
699 
#define                   TIMER7_COUNTER  0xffc01674   /* Timer 7 Counter Register */
700 
#define                    TIMER7_PERIOD  0xffc01678   /* Timer 7 Period Register */
701 
#define                     TIMER7_WIDTH  0xffc0167c   /* Timer 7 Width Register */
702 
 
703 
/* Timer Group of 8 */
704 
 
705 
#define                    TIMER_ENABLE0  0xffc01680   /* Timer Group of 8 Enable Register */
706 
#define                   TIMER_DISABLE0  0xffc01684   /* Timer Group of 8 Disable Register */
707 
#define                    TIMER_STATUS0  0xffc01688   /* Timer Group of 8 Status Register */
708 
 
709 
/* DMAC1 Registers */
710 
 
711 
#define                      DMAC1_TCPER  0xffc01b0c   /* DMA Controller 1 Traffic Control Periods Register */
712 
#define                      DMAC1_TCCNT  0xffc01b10   /* DMA Controller 1 Current Counts Register */
713 
 
714 
/* DMA Channel 12 Registers */
715 
 
716 
#define              DMA12_NEXT_DESC_PTR  0xffc01c00   /* DMA Channel 12 Next Descriptor Pointer Register */
717 
#define                 DMA12_START_ADDR  0xffc01c04   /* DMA Channel 12 Start Address Register */
718 
#define                     DMA12_CONFIG  0xffc01c08   /* DMA Channel 12 Configuration Register */
719 
#define                    DMA12_X_COUNT  0xffc01c10   /* DMA Channel 12 X Count Register */
720 
#define                   DMA12_X_MODIFY  0xffc01c14   /* DMA Channel 12 X Modify Register */
721 
#define                    DMA12_Y_COUNT  0xffc01c18   /* DMA Channel 12 Y Count Register */
722 
#define                   DMA12_Y_MODIFY  0xffc01c1c   /* DMA Channel 12 Y Modify Register */
723 
#define              DMA12_CURR_DESC_PTR  0xffc01c20   /* DMA Channel 12 Current Descriptor Pointer Register */
724 
#define                  DMA12_CURR_ADDR  0xffc01c24   /* DMA Channel 12 Current Address Register */
725 
#define                 DMA12_IRQ_STATUS  0xffc01c28   /* DMA Channel 12 Interrupt/Status Register */
726 
#define             DMA12_PERIPHERAL_MAP  0xffc01c2c   /* DMA Channel 12 Peripheral Map Register */
727 
#define               DMA12_CURR_X_COUNT  0xffc01c30   /* DMA Channel 12 Current X Count Register */
728 
#define               DMA12_CURR_Y_COUNT  0xffc01c38   /* DMA Channel 12 Current Y Count Register */
729 
 
730 
/* DMA Channel 13 Registers */
731 
 
732 
#define              DMA13_NEXT_DESC_PTR  0xffc01c40   /* DMA Channel 13 Next Descriptor Pointer Register */
733 
#define                 DMA13_START_ADDR  0xffc01c44   /* DMA Channel 13 Start Address Register */
734 
#define                     DMA13_CONFIG  0xffc01c48   /* DMA Channel 13 Configuration Register */
735 
#define                    DMA13_X_COUNT  0xffc01c50   /* DMA Channel 13 X Count Register */
736 
#define                   DMA13_X_MODIFY  0xffc01c54   /* DMA Channel 13 X Modify Register */
737 
#define                    DMA13_Y_COUNT  0xffc01c58   /* DMA Channel 13 Y Count Register */
738 
#define                   DMA13_Y_MODIFY  0xffc01c5c   /* DMA Channel 13 Y Modify Register */
739 
#define              DMA13_CURR_DESC_PTR  0xffc01c60   /* DMA Channel 13 Current Descriptor Pointer Register */
740 
#define                  DMA13_CURR_ADDR  0xffc01c64   /* DMA Channel 13 Current Address Register */
741 
#define                 DMA13_IRQ_STATUS  0xffc01c68   /* DMA Channel 13 Interrupt/Status Register */
742 
#define             DMA13_PERIPHERAL_MAP  0xffc01c6c   /* DMA Channel 13 Peripheral Map Register */
743 
#define               DMA13_CURR_X_COUNT  0xffc01c70   /* DMA Channel 13 Current X Count Register */
744 
#define               DMA13_CURR_Y_COUNT  0xffc01c78   /* DMA Channel 13 Current Y Count Register */
745 
 
746 
/* DMA Channel 14 Registers */
747 
 
748 
#define              DMA14_NEXT_DESC_PTR  0xffc01c80   /* DMA Channel 14 Next Descriptor Pointer Register */
749 
#define                 DMA14_START_ADDR  0xffc01c84   /* DMA Channel 14 Start Address Register */
750 
#define                     DMA14_CONFIG  0xffc01c88   /* DMA Channel 14 Configuration Register */
751 
#define                    DMA14_X_COUNT  0xffc01c90   /* DMA Channel 14 X Count Register */
752 
#define                   DMA14_X_MODIFY  0xffc01c94   /* DMA Channel 14 X Modify Register */
753 
#define                    DMA14_Y_COUNT  0xffc01c98   /* DMA Channel 14 Y Count Register */
754 
#define                   DMA14_Y_MODIFY  0xffc01c9c   /* DMA Channel 14 Y Modify Register */
755 
#define              DMA14_CURR_DESC_PTR  0xffc01ca0   /* DMA Channel 14 Current Descriptor Pointer Register */
756 
#define                  DMA14_CURR_ADDR  0xffc01ca4   /* DMA Channel 14 Current Address Register */
757 
#define                 DMA14_IRQ_STATUS  0xffc01ca8   /* DMA Channel 14 Interrupt/Status Register */
758 
#define             DMA14_PERIPHERAL_MAP  0xffc01cac   /* DMA Channel 14 Peripheral Map Register */
759 
#define               DMA14_CURR_X_COUNT  0xffc01cb0   /* DMA Channel 14 Current X Count Register */
760 
#define               DMA14_CURR_Y_COUNT  0xffc01cb8   /* DMA Channel 14 Current Y Count Register */
761 
 
762 
/* DMA Channel 15 Registers */
763 
 
764 
#define              DMA15_NEXT_DESC_PTR  0xffc01cc0   /* DMA Channel 15 Next Descriptor Pointer Register */
765 
#define                 DMA15_START_ADDR  0xffc01cc4   /* DMA Channel 15 Start Address Register */
766 
#define                     DMA15_CONFIG  0xffc01cc8   /* DMA Channel 15 Configuration Register */
767 
#define                    DMA15_X_COUNT  0xffc01cd0   /* DMA Channel 15 X Count Register */
768 
#define                   DMA15_X_MODIFY  0xffc01cd4   /* DMA Channel 15 X Modify Register */
769 
#define                    DMA15_Y_COUNT  0xffc01cd8   /* DMA Channel 15 Y Count Register */
770 
#define                   DMA15_Y_MODIFY  0xffc01cdc   /* DMA Channel 15 Y Modify Register */
771 
#define              DMA15_CURR_DESC_PTR  0xffc01ce0   /* DMA Channel 15 Current Descriptor Pointer Register */
772 
#define                  DMA15_CURR_ADDR  0xffc01ce4   /* DMA Channel 15 Current Address Register */
773 
#define                 DMA15_IRQ_STATUS  0xffc01ce8   /* DMA Channel 15 Interrupt/Status Register */
774 
#define             DMA15_PERIPHERAL_MAP  0xffc01cec   /* DMA Channel 15 Peripheral Map Register */
775 
#define               DMA15_CURR_X_COUNT  0xffc01cf0   /* DMA Channel 15 Current X Count Register */
776 
#define               DMA15_CURR_Y_COUNT  0xffc01cf8   /* DMA Channel 15 Current Y Count Register */
777 
 
778 
/* DMA Channel 16 Registers */
779 
 
780 
#define              DMA16_NEXT_DESC_PTR  0xffc01d00   /* DMA Channel 16 Next Descriptor Pointer Register */
781 
#define                 DMA16_START_ADDR  0xffc01d04   /* DMA Channel 16 Start Address Register */
782 
#define                     DMA16_CONFIG  0xffc01d08   /* DMA Channel 16 Configuration Register */
783 
#define                    DMA16_X_COUNT  0xffc01d10   /* DMA Channel 16 X Count Register */
784 
#define                   DMA16_X_MODIFY  0xffc01d14   /* DMA Channel 16 X Modify Register */
785 
#define                    DMA16_Y_COUNT  0xffc01d18   /* DMA Channel 16 Y Count Register */
786 
#define                   DMA16_Y_MODIFY  0xffc01d1c   /* DMA Channel 16 Y Modify Register */
787 
#define              DMA16_CURR_DESC_PTR  0xffc01d20   /* DMA Channel 16 Current Descriptor Pointer Register */
788 
#define                  DMA16_CURR_ADDR  0xffc01d24   /* DMA Channel 16 Current Address Register */
789 
#define                 DMA16_IRQ_STATUS  0xffc01d28   /* DMA Channel 16 Interrupt/Status Register */
790 
#define             DMA16_PERIPHERAL_MAP  0xffc01d2c   /* DMA Channel 16 Peripheral Map Register */
791 
#define               DMA16_CURR_X_COUNT  0xffc01d30   /* DMA Channel 16 Current X Count Register */
792 
#define               DMA16_CURR_Y_COUNT  0xffc01d38   /* DMA Channel 16 Current Y Count Register */
793 
 
794 
/* DMA Channel 17 Registers */
795 
 
796 
#define              DMA17_NEXT_DESC_PTR  0xffc01d40   /* DMA Channel 17 Next Descriptor Pointer Register */
797 
#define                 DMA17_START_ADDR  0xffc01d44   /* DMA Channel 17 Start Address Register */
798 
#define                     DMA17_CONFIG  0xffc01d48   /* DMA Channel 17 Configuration Register */
799 
#define                    DMA17_X_COUNT  0xffc01d50   /* DMA Channel 17 X Count Register */
800 
#define                   DMA17_X_MODIFY  0xffc01d54   /* DMA Channel 17 X Modify Register */
801 
#define                    DMA17_Y_COUNT  0xffc01d58   /* DMA Channel 17 Y Count Register */
802 
#define                   DMA17_Y_MODIFY  0xffc01d5c   /* DMA Channel 17 Y Modify Register */
803 
#define              DMA17_CURR_DESC_PTR  0xffc01d60   /* DMA Channel 17 Current Descriptor Pointer Register */
804 
#define                  DMA17_CURR_ADDR  0xffc01d64   /* DMA Channel 17 Current Address Register */
805 
#define                 DMA17_IRQ_STATUS  0xffc01d68   /* DMA Channel 17 Interrupt/Status Register */
806 
#define             DMA17_PERIPHERAL_MAP  0xffc01d6c   /* DMA Channel 17 Peripheral Map Register */
807 
#define               DMA17_CURR_X_COUNT  0xffc01d70   /* DMA Channel 17 Current X Count Register */
808 
#define               DMA17_CURR_Y_COUNT  0xffc01d78   /* DMA Channel 17 Current Y Count Register */
809 
 
810 
/* DMA Channel 18 Registers */
811 
 
812 
#define              DMA18_NEXT_DESC_PTR  0xffc01d80   /* DMA Channel 18 Next Descriptor Pointer Register */
813 
#define                 DMA18_START_ADDR  0xffc01d84   /* DMA Channel 18 Start Address Register */
814 
#define                     DMA18_CONFIG  0xffc01d88   /* DMA Channel 18 Configuration Register */
815 
#define                    DMA18_X_COUNT  0xffc01d90   /* DMA Channel 18 X Count Register */
816 
#define                   DMA18_X_MODIFY  0xffc01d94   /* DMA Channel 18 X Modify Register */
817 
#define                    DMA18_Y_COUNT  0xffc01d98   /* DMA Channel 18 Y Count Register */
818 
#define                   DMA18_Y_MODIFY  0xffc01d9c   /* DMA Channel 18 Y Modify Register */
819 
#define              DMA18_CURR_DESC_PTR  0xffc01da0   /* DMA Channel 18 Current Descriptor Pointer Register */
820 
#define                  DMA18_CURR_ADDR  0xffc01da4   /* DMA Channel 18 Current Address Register */
821 
#define                 DMA18_IRQ_STATUS  0xffc01da8   /* DMA Channel 18 Interrupt/Status Register */
822 
#define             DMA18_PERIPHERAL_MAP  0xffc01dac   /* DMA Channel 18 Peripheral Map Register */
823 
#define               DMA18_CURR_X_COUNT  0xffc01db0   /* DMA Channel 18 Current X Count Register */
824 
#define               DMA18_CURR_Y_COUNT  0xffc01db8   /* DMA Channel 18 Current Y Count Register */
825 
 
826 
/* DMA Channel 19 Registers */
827 
 
828 
#define              DMA19_NEXT_DESC_PTR  0xffc01dc0   /* DMA Channel 19 Next Descriptor Pointer Register */
829 
#define                 DMA19_START_ADDR  0xffc01dc4   /* DMA Channel 19 Start Address Register */
830 
#define                     DMA19_CONFIG  0xffc01dc8   /* DMA Channel 19 Configuration Register */
831 
#define                    DMA19_X_COUNT  0xffc01dd0   /* DMA Channel 19 X Count Register */
832 
#define                   DMA19_X_MODIFY  0xffc01dd4   /* DMA Channel 19 X Modify Register */
833 
#define                    DMA19_Y_COUNT  0xffc01dd8   /* DMA Channel 19 Y Count Register */
834 
#define                   DMA19_Y_MODIFY  0xffc01ddc   /* DMA Channel 19 Y Modify Register */
835 
#define              DMA19_CURR_DESC_PTR  0xffc01de0   /* DMA Channel 19 Current Descriptor Pointer Register */
836 
#define                  DMA19_CURR_ADDR  0xffc01de4   /* DMA Channel 19 Current Address Register */
837 
#define                 DMA19_IRQ_STATUS  0xffc01de8   /* DMA Channel 19 Interrupt/Status Register */
838 
#define             DMA19_PERIPHERAL_MAP  0xffc01dec   /* DMA Channel 19 Peripheral Map Register */
839 
#define               DMA19_CURR_X_COUNT  0xffc01df0   /* DMA Channel 19 Current X Count Register */
840 
#define               DMA19_CURR_Y_COUNT  0xffc01df8   /* DMA Channel 19 Current Y Count Register */
841 
 
842 
/* DMA Channel 20 Registers */
843 
 
844 
#define              DMA20_NEXT_DESC_PTR  0xffc01e00   /* DMA Channel 20 Next Descriptor Pointer Register */
845 
#define                 DMA20_START_ADDR  0xffc01e04   /* DMA Channel 20 Start Address Register */
846 
#define                     DMA20_CONFIG  0xffc01e08   /* DMA Channel 20 Configuration Register */
847 
#define                    DMA20_X_COUNT  0xffc01e10   /* DMA Channel 20 X Count Register */
848 
#define                   DMA20_X_MODIFY  0xffc01e14   /* DMA Channel 20 X Modify Register */
849 
#define                    DMA20_Y_COUNT  0xffc01e18   /* DMA Channel 20 Y Count Register */
850 
#define                   DMA20_Y_MODIFY  0xffc01e1c   /* DMA Channel 20 Y Modify Register */
851 
#define              DMA20_CURR_DESC_PTR  0xffc01e20   /* DMA Channel 20 Current Descriptor Pointer Register */
852 
#define                  DMA20_CURR_ADDR  0xffc01e24   /* DMA Channel 20 Current Address Register */
853 
#define                 DMA20_IRQ_STATUS  0xffc01e28   /* DMA Channel 20 Interrupt/Status Register */
854 
#define             DMA20_PERIPHERAL_MAP  0xffc01e2c   /* DMA Channel 20 Peripheral Map Register */
855 
#define               DMA20_CURR_X_COUNT  0xffc01e30   /* DMA Channel 20 Current X Count Register */
856 
#define               DMA20_CURR_Y_COUNT  0xffc01e38   /* DMA Channel 20 Current Y Count Register */
857 
 
858 
/* DMA Channel 21 Registers */
859 
 
860 
#define              DMA21_NEXT_DESC_PTR  0xffc01e40   /* DMA Channel 21 Next Descriptor Pointer Register */
861 
#define                 DMA21_START_ADDR  0xffc01e44   /* DMA Channel 21 Start Address Register */
862 
#define                     DMA21_CONFIG  0xffc01e48   /* DMA Channel 21 Configuration Register */
863 
#define                    DMA21_X_COUNT  0xffc01e50   /* DMA Channel 21 X Count Register */
864 
#define                   DMA21_X_MODIFY  0xffc01e54   /* DMA Channel 21 X Modify Register */
865 
#define                    DMA21_Y_COUNT  0xffc01e58   /* DMA Channel 21 Y Count Register */
866 
#define                   DMA21_Y_MODIFY  0xffc01e5c   /* DMA Channel 21 Y Modify Register */
867 
#define              DMA21_CURR_DESC_PTR  0xffc01e60   /* DMA Channel 21 Current Descriptor Pointer Register */
868 
#define                  DMA21_CURR_ADDR  0xffc01e64   /* DMA Channel 21 Current Address Register */
869 
#define                 DMA21_IRQ_STATUS  0xffc01e68   /* DMA Channel 21 Interrupt/Status Register */
870 
#define             DMA21_PERIPHERAL_MAP  0xffc01e6c   /* DMA Channel 21 Peripheral Map Register */
871 
#define               DMA21_CURR_X_COUNT  0xffc01e70   /* DMA Channel 21 Current X Count Register */
872 
#define               DMA21_CURR_Y_COUNT  0xffc01e78   /* DMA Channel 21 Current Y Count Register */
873 
 
874 
/* DMA Channel 22 Registers */
875 
 
876 
#define              DMA22_NEXT_DESC_PTR  0xffc01e80   /* DMA Channel 22 Next Descriptor Pointer Register */
877 
#define                 DMA22_START_ADDR  0xffc01e84   /* DMA Channel 22 Start Address Register */
878 
#define                     DMA22_CONFIG  0xffc01e88   /* DMA Channel 22 Configuration Register */
879 
#define                    DMA22_X_COUNT  0xffc01e90   /* DMA Channel 22 X Count Register */
880 
#define                   DMA22_X_MODIFY  0xffc01e94   /* DMA Channel 22 X Modify Register */
881 
#define                    DMA22_Y_COUNT  0xffc01e98   /* DMA Channel 22 Y Count Register */
882 
#define                   DMA22_Y_MODIFY  0xffc01e9c   /* DMA Channel 22 Y Modify Register */
883 
#define              DMA22_CURR_DESC_PTR  0xffc01ea0   /* DMA Channel 22 Current Descriptor Pointer Register */
884 
#define                  DMA22_CURR_ADDR  0xffc01ea4   /* DMA Channel 22 Current Address Register */
885 
#define                 DMA22_IRQ_STATUS  0xffc01ea8   /* DMA Channel 22 Interrupt/Status Register */
886 
#define             DMA22_PERIPHERAL_MAP  0xffc01eac   /* DMA Channel 22 Peripheral Map Register */
887 
#define               DMA22_CURR_X_COUNT  0xffc01eb0   /* DMA Channel 22 Current X Count Register */
888 
#define               DMA22_CURR_Y_COUNT  0xffc01eb8   /* DMA Channel 22 Current Y Count Register */
889 
 
890 
/* DMA Channel 23 Registers */
891 
 
892 
#define              DMA23_NEXT_DESC_PTR  0xffc01ec0   /* DMA Channel 23 Next Descriptor Pointer Register */
893 
#define                 DMA23_START_ADDR  0xffc01ec4   /* DMA Channel 23 Start Address Register */
894 
#define                     DMA23_CONFIG  0xffc01ec8   /* DMA Channel 23 Configuration Register */
895 
#define                    DMA23_X_COUNT  0xffc01ed0   /* DMA Channel 23 X Count Register */
896 
#define                   DMA23_X_MODIFY  0xffc01ed4   /* DMA Channel 23 X Modify Register */
897 
#define                    DMA23_Y_COUNT  0xffc01ed8   /* DMA Channel 23 Y Count Register */
898 
#define                   DMA23_Y_MODIFY  0xffc01edc   /* DMA Channel 23 Y Modify Register */
899 
#define              DMA23_CURR_DESC_PTR  0xffc01ee0   /* DMA Channel 23 Current Descriptor Pointer Register */
900 
#define                  DMA23_CURR_ADDR  0xffc01ee4   /* DMA Channel 23 Current Address Register */
901 
#define                 DMA23_IRQ_STATUS  0xffc01ee8   /* DMA Channel 23 Interrupt/Status Register */
902 
#define             DMA23_PERIPHERAL_MAP  0xffc01eec   /* DMA Channel 23 Peripheral Map Register */
903 
#define               DMA23_CURR_X_COUNT  0xffc01ef0   /* DMA Channel 23 Current X Count Register */
904 
#define               DMA23_CURR_Y_COUNT  0xffc01ef8   /* DMA Channel 23 Current Y Count Register */
905 
 
906 
/* MDMA Stream 2 Registers */
907 
 
908 
#define            MDMA_D2_NEXT_DESC_PTR  0xffc01f00   /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
909 
#define               MDMA_D2_START_ADDR  0xffc01f04   /* Memory DMA Stream 2 Destination Start Address Register */
910 
#define                   MDMA_D2_CONFIG  0xffc01f08   /* Memory DMA Stream 2 Destination Configuration Register */
911 
#define                  MDMA_D2_X_COUNT  0xffc01f10   /* Memory DMA Stream 2 Destination X Count Register */
912 
#define                 MDMA_D2_X_MODIFY  0xffc01f14   /* Memory DMA Stream 2 Destination X Modify Register */
913 
#define                  MDMA_D2_Y_COUNT  0xffc01f18   /* Memory DMA Stream 2 Destination Y Count Register */
914 
#define                 MDMA_D2_Y_MODIFY  0xffc01f1c   /* Memory DMA Stream 2 Destination Y Modify Register */
915 
#define            MDMA_D2_CURR_DESC_PTR  0xffc01f20   /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
916 
#define                MDMA_D2_CURR_ADDR  0xffc01f24   /* Memory DMA Stream 2 Destination Current Address Register */
917 
#define               MDMA_D2_IRQ_STATUS  0xffc01f28   /* Memory DMA Stream 2 Destination Interrupt/Status Register */
918 
#define           MDMA_D2_PERIPHERAL_MAP  0xffc01f2c   /* Memory DMA Stream 2 Destination Peripheral Map Register */
919 
#define             MDMA_D2_CURR_X_COUNT  0xffc01f30   /* Memory DMA Stream 2 Destination Current X Count Register */
920 
#define             MDMA_D2_CURR_Y_COUNT  0xffc01f38   /* Memory DMA Stream 2 Destination Current Y Count Register */
921 
#define            MDMA_S2_NEXT_DESC_PTR  0xffc01f40   /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
922 
#define               MDMA_S2_START_ADDR  0xffc01f44   /* Memory DMA Stream 2 Source Start Address Register */
923 
#define                   MDMA_S2_CONFIG  0xffc01f48   /* Memory DMA Stream 2 Source Configuration Register */
924 
#define                  MDMA_S2_X_COUNT  0xffc01f50   /* Memory DMA Stream 2 Source X Count Register */
925 
#define                 MDMA_S2_X_MODIFY  0xffc01f54   /* Memory DMA Stream 2 Source X Modify Register */
926 
#define                  MDMA_S2_Y_COUNT  0xffc01f58   /* Memory DMA Stream 2 Source Y Count Register */
927 
#define                 MDMA_S2_Y_MODIFY  0xffc01f5c   /* Memory DMA Stream 2 Source Y Modify Register */
928 
#define            MDMA_S2_CURR_DESC_PTR  0xffc01f60   /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
929 
#define                MDMA_S2_CURR_ADDR  0xffc01f64   /* Memory DMA Stream 2 Source Current Address Register */
930 
#define               MDMA_S2_IRQ_STATUS  0xffc01f68   /* Memory DMA Stream 2 Source Interrupt/Status Register */
931 
#define           MDMA_S2_PERIPHERAL_MAP  0xffc01f6c   /* Memory DMA Stream 2 Source Peripheral Map Register */
932 
#define             MDMA_S2_CURR_X_COUNT  0xffc01f70   /* Memory DMA Stream 2 Source Current X Count Register */
933 
#define             MDMA_S2_CURR_Y_COUNT  0xffc01f78   /* Memory DMA Stream 2 Source Current Y Count Register */
934 
 
935 
/* MDMA Stream 3 Registers */
936 
 
937 
#define            MDMA_D3_NEXT_DESC_PTR  0xffc01f80   /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
938 
#define               MDMA_D3_START_ADDR  0xffc01f84   /* Memory DMA Stream 3 Destination Start Address Register */
939 
#define                   MDMA_D3_CONFIG  0xffc01f88   /* Memory DMA Stream 3 Destination Configuration Register */
940 
#define                  MDMA_D3_X_COUNT  0xffc01f90   /* Memory DMA Stream 3 Destination X Count Register */
941 
#define                 MDMA_D3_X_MODIFY  0xffc01f94   /* Memory DMA Stream 3 Destination X Modify Register */
942 
#define                  MDMA_D3_Y_COUNT  0xffc01f98   /* Memory DMA Stream 3 Destination Y Count Register */
943 
#define                 MDMA_D3_Y_MODIFY  0xffc01f9c   /* Memory DMA Stream 3 Destination Y Modify Register */
944 
#define            MDMA_D3_CURR_DESC_PTR  0xffc01fa0   /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
945 
#define                MDMA_D3_CURR_ADDR  0xffc01fa4   /* Memory DMA Stream 3 Destination Current Address Register */
946 
#define               MDMA_D3_IRQ_STATUS  0xffc01fa8   /* Memory DMA Stream 3 Destination Interrupt/Status Register */
947 
#define           MDMA_D3_PERIPHERAL_MAP  0xffc01fac   /* Memory DMA Stream 3 Destination Peripheral Map Register */
948 
#define             MDMA_D3_CURR_X_COUNT  0xffc01fb0   /* Memory DMA Stream 3 Destination Current X Count Register */
949 
#define             MDMA_D3_CURR_Y_COUNT  0xffc01fb8   /* Memory DMA Stream 3 Destination Current Y Count Register */
950 
#define            MDMA_S3_NEXT_DESC_PTR  0xffc01fc0   /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
951 
#define               MDMA_S3_START_ADDR  0xffc01fc4   /* Memory DMA Stream 3 Source Start Address Register */
952 
#define                   MDMA_S3_CONFIG  0xffc01fc8   /* Memory DMA Stream 3 Source Configuration Register */
953 
#define                  MDMA_S3_X_COUNT  0xffc01fd0   /* Memory DMA Stream 3 Source X Count Register */
954 
#define                 MDMA_S3_X_MODIFY  0xffc01fd4   /* Memory DMA Stream 3 Source X Modify Register */
955 
#define                  MDMA_S3_Y_COUNT  0xffc01fd8   /* Memory DMA Stream 3 Source Y Count Register */
956 
#define                 MDMA_S3_Y_MODIFY  0xffc01fdc   /* Memory DMA Stream 3 Source Y Modify Register */
957 
#define            MDMA_S3_CURR_DESC_PTR  0xffc01fe0   /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
958 
#define                MDMA_S3_CURR_ADDR  0xffc01fe4   /* Memory DMA Stream 3 Source Current Address Register */
959 
#define               MDMA_S3_IRQ_STATUS  0xffc01fe8   /* Memory DMA Stream 3 Source Interrupt/Status Register */
960 
#define           MDMA_S3_PERIPHERAL_MAP  0xffc01fec   /* Memory DMA Stream 3 Source Peripheral Map Register */
961 
#define             MDMA_S3_CURR_X_COUNT  0xffc01ff0   /* Memory DMA Stream 3 Source Current X Count Register */
962 
#define             MDMA_S3_CURR_Y_COUNT  0xffc01ff8   /* Memory DMA Stream 3 Source Current Y Count Register */
963 
 
964 
/* UART1 Registers */
965 
 
966 
#define                        UART1_DLL  0xffc02000   /* Divisor Latch Low Byte */
967 
#define                        UART1_DLH  0xffc02004   /* Divisor Latch High Byte */
968 
#define                       UART1_GCTL  0xffc02008   /* Global Control Register */
969 
#define                        UART1_LCR  0xffc0200c   /* Line Control Register */
970 
#define                        UART1_MCR  0xffc02010   /* Modem Control Register */
971 
#define                        UART1_LSR  0xffc02014   /* Line Status Register */
972 
#define                        UART1_MSR  0xffc02018   /* Modem Status Register */
973 
#define                        UART1_SCR  0xffc0201c   /* Scratch Register */
974 
#define                    UART1_IER_SET  0xffc02020   /* Interrupt Enable Register Set */
975 
#define                  UART1_IER_CLEAR  0xffc02024   /* Interrupt Enable Register Clear */
976 
#define                        UART1_THR  0xffc02028   /* Transmit Hold Register */
977 
#define                        UART1_RBR  0xffc0202c   /* Receive Buffer Register */
978 
 
979 
/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
980 
 
981 
/* SPI1 Registers */
982 
 
983 
#define                         SPI1_CTL  0xffc02300   /* SPI1 Control Register */
984 
#define                         SPI1_FLG  0xffc02304   /* SPI1 Flag Register */
985 
#define                        SPI1_STAT  0xffc02308   /* SPI1 Status Register */
986 
#define                        SPI1_TDBR  0xffc0230c   /* SPI1 Transmit Data Buffer Register */
987 
#define                        SPI1_RDBR  0xffc02310   /* SPI1 Receive Data Buffer Register */
988 
#define                        SPI1_BAUD  0xffc02314   /* SPI1 Baud Rate Register */
989 
#define                      SPI1_SHADOW  0xffc02318   /* SPI1 Receive Data Buffer Shadow Register */
990 
 
991 
/* SPORT2 Registers */
992 
 
993 
#define                      SPORT2_TCR1  0xffc02500   /* SPORT2 Transmit Configuration 1 Register */
994 
#define                      SPORT2_TCR2  0xffc02504   /* SPORT2 Transmit Configuration 2 Register */
995 
#define                   SPORT2_TCLKDIV  0xffc02508   /* SPORT2 Transmit Serial Clock Divider Register */
996 
#define                    SPORT2_TFSDIV  0xffc0250c   /* SPORT2 Transmit Frame Sync Divider Register */
997 
#define                        SPORT2_TX  0xffc02510   /* SPORT2 Transmit Data Register */
998 
#define                        SPORT2_RX  0xffc02518   /* SPORT2 Receive Data Register */
999 
#define                      SPORT2_RCR1  0xffc02520   /* SPORT2 Receive Configuration 1 Register */
1000 
#define                      SPORT2_RCR2  0xffc02524   /* SPORT2 Receive Configuration 2 Register */
1001 
#define                   SPORT2_RCLKDIV  0xffc02528   /* SPORT2 Receive Serial Clock Divider Register */
1002 
#define                    SPORT2_RFSDIV  0xffc0252c   /* SPORT2 Receive Frame Sync Divider Register */
1003 
#define                      SPORT2_STAT  0xffc02530   /* SPORT2 Status Register */
1004 
#define                      SPORT2_CHNL  0xffc02534   /* SPORT2 Current Channel Register */
1005 
#define                     SPORT2_MCMC1  0xffc02538   /* SPORT2 Multi channel Configuration Register 1 */
1006 
#define                     SPORT2_MCMC2  0xffc0253c   /* SPORT2 Multi channel Configuration Register 2 */
1007 
#define                     SPORT2_MTCS0  0xffc02540   /* SPORT2 Multi channel Transmit Select Register 0 */
1008 
#define                     SPORT2_MTCS1  0xffc02544   /* SPORT2 Multi channel Transmit Select Register 1 */
1009 
#define                     SPORT2_MTCS2  0xffc02548   /* SPORT2 Multi channel Transmit Select Register 2 */
1010 
#define                     SPORT2_MTCS3  0xffc0254c   /* SPORT2 Multi channel Transmit Select Register 3 */
1011 
#define                     SPORT2_MRCS0  0xffc02550   /* SPORT2 Multi channel Receive Select Register 0 */
1012 
#define                     SPORT2_MRCS1  0xffc02554   /* SPORT2 Multi channel Receive Select Register 1 */
1013 
#define                     SPORT2_MRCS2  0xffc02558   /* SPORT2 Multi channel Receive Select Register 2 */
1014 
#define                     SPORT2_MRCS3  0xffc0255c   /* SPORT2 Multi channel Receive Select Register 3 */
1015 
 
1016 
/* SPORT3 Registers */
1017 
 
1018 
#define                      SPORT3_TCR1  0xffc02600   /* SPORT3 Transmit Configuration 1 Register */
1019 
#define                      SPORT3_TCR2  0xffc02604   /* SPORT3 Transmit Configuration 2 Register */
1020 
#define                   SPORT3_TCLKDIV  0xffc02608   /* SPORT3 Transmit Serial Clock Divider Register */
1021 
#define                    SPORT3_TFSDIV  0xffc0260c   /* SPORT3 Transmit Frame Sync Divider Register */
1022 
#define                        SPORT3_TX  0xffc02610   /* SPORT3 Transmit Data Register */
1023 
#define                        SPORT3_RX  0xffc02618   /* SPORT3 Receive Data Register */
1024 
#define                      SPORT3_RCR1  0xffc02620   /* SPORT3 Receive Configuration 1 Register */
1025 
#define                      SPORT3_RCR2  0xffc02624   /* SPORT3 Receive Configuration 2 Register */
1026 
#define                   SPORT3_RCLKDIV  0xffc02628   /* SPORT3 Receive Serial Clock Divider Register */
1027 
#define                    SPORT3_RFSDIV  0xffc0262c   /* SPORT3 Receive Frame Sync Divider Register */
1028 
#define                      SPORT3_STAT  0xffc02630   /* SPORT3 Status Register */
1029 
#define                      SPORT3_CHNL  0xffc02634   /* SPORT3 Current Channel Register */
1030 
#define                     SPORT3_MCMC1  0xffc02638   /* SPORT3 Multi channel Configuration Register 1 */
1031 
#define                     SPORT3_MCMC2  0xffc0263c   /* SPORT3 Multi channel Configuration Register 2 */
1032 
#define                     SPORT3_MTCS0  0xffc02640   /* SPORT3 Multi channel Transmit Select Register 0 */
1033 
#define                     SPORT3_MTCS1  0xffc02644   /* SPORT3 Multi channel Transmit Select Register 1 */
1034 
#define                     SPORT3_MTCS2  0xffc02648   /* SPORT3 Multi channel Transmit Select Register 2 */
1035 
#define                     SPORT3_MTCS3  0xffc0264c   /* SPORT3 Multi channel Transmit Select Register 3 */
1036 
#define                     SPORT3_MRCS0  0xffc02650   /* SPORT3 Multi channel Receive Select Register 0 */
1037 
#define                     SPORT3_MRCS1  0xffc02654   /* SPORT3 Multi channel Receive Select Register 1 */
1038 
#define                     SPORT3_MRCS2  0xffc02658   /* SPORT3 Multi channel Receive Select Register 2 */
1039 
#define                     SPORT3_MRCS3  0xffc0265c   /* SPORT3 Multi channel Receive Select Register 3 */
1040 
 
1041 
/* EPPI2 Registers */
1042 
 
1043 
#define                     EPPI2_STATUS  0xffc02900   /* EPPI2 Status Register */
1044 
#define                     EPPI2_HCOUNT  0xffc02904   /* EPPI2 Horizontal Transfer Count Register */
1045 
#define                     EPPI2_HDELAY  0xffc02908   /* EPPI2 Horizontal Delay Count Register */
1046 
#define                     EPPI2_VCOUNT  0xffc0290c   /* EPPI2 Vertical Transfer Count Register */
1047 
#define                     EPPI2_VDELAY  0xffc02910   /* EPPI2 Vertical Delay Count Register */
1048 
#define                      EPPI2_FRAME  0xffc02914   /* EPPI2 Lines per Frame Register */
1049 
#define                       EPPI2_LINE  0xffc02918   /* EPPI2 Samples per Line Register */
1050 
#define                     EPPI2_CLKDIV  0xffc0291c   /* EPPI2 Clock Divide Register */
1051 
#define                    EPPI2_CONTROL  0xffc02920   /* EPPI2 Control Register */
1052 
#define                   EPPI2_FS1W_HBL  0xffc02924   /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
1053 
#define                  EPPI2_FS1P_AVPL  0xffc02928   /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
1054 
#define                   EPPI2_FS2W_LVB  0xffc0292c   /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
1055 
#define                  EPPI2_FS2P_LAVF  0xffc02930   /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
1056 
#define                       EPPI2_CLIP  0xffc02934   /* EPPI2 Clipping Register */
1057 
 
1058 
/* CAN Controller 0 Config 1 Registers */
1059 
 
1060 
#define                         CAN0_MC1  0xffc02a00   /* CAN Controller 0 Mailbox Configuration Register 1 */
1061 
#define                         CAN0_MD1  0xffc02a04   /* CAN Controller 0 Mailbox Direction Register 1 */
1062 
#define                        CAN0_TRS1  0xffc02a08   /* CAN Controller 0 Transmit Request Set Register 1 */
1063 
#define                        CAN0_TRR1  0xffc02a0c   /* CAN Controller 0 Transmit Request Reset Register 1 */
1064 
#define                         CAN0_TA1  0xffc02a10   /* CAN Controller 0 Transmit Acknowledge Register 1 */
1065 
#define                         CAN0_AA1  0xffc02a14   /* CAN Controller 0 Abort Acknowledge Register 1 */
1066 
#define                        CAN0_RMP1  0xffc02a18   /* CAN Controller 0 Receive Message Pending Register 1 */
1067 
#define                        CAN0_RML1  0xffc02a1c   /* CAN Controller 0 Receive Message Lost Register 1 */
1068 
#define                      CAN0_MBTIF1  0xffc02a20   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
1069 
#define                      CAN0_MBRIF1  0xffc02a24   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
1070 
#define                       CAN0_MBIM1  0xffc02a28   /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
1071 
#define                        CAN0_RFH1  0xffc02a2c   /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
1072 
#define                       CAN0_OPSS1  0xffc02a30   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
1073 
 
1074 
/* CAN Controller 0 Config 2 Registers */
1075 
 
1076 
#define                         CAN0_MC2  0xffc02a40   /* CAN Controller 0 Mailbox Configuration Register 2 */
1077 
#define                         CAN0_MD2  0xffc02a44   /* CAN Controller 0 Mailbox Direction Register 2 */
1078 
#define                        CAN0_TRS2  0xffc02a48   /* CAN Controller 0 Transmit Request Set Register 2 */
1079 
#define                        CAN0_TRR2  0xffc02a4c   /* CAN Controller 0 Transmit Request Reset Register 2 */
1080 
#define                         CAN0_TA2  0xffc02a50   /* CAN Controller 0 Transmit Acknowledge Register 2 */
1081 
#define                         CAN0_AA2  0xffc02a54   /* CAN Controller 0 Abort Acknowledge Register 2 */
1082 
#define                        CAN0_RMP2  0xffc02a58   /* CAN Controller 0 Receive Message Pending Register 2 */
1083 
#define                        CAN0_RML2  0xffc02a5c   /* CAN Controller 0 Receive Message Lost Register 2 */
1084 
#define                      CAN0_MBTIF2  0xffc02a60   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
1085 
#define                      CAN0_MBRIF2  0xffc02a64   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
1086 
#define                       CAN0_MBIM2  0xffc02a68   /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
1087 
#define                        CAN0_RFH2  0xffc02a6c   /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
1088 
#define                       CAN0_OPSS2  0xffc02a70   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
1089 
 
1090 
/* CAN Controller 0 Clock/Interrupt/Counter Registers */
1091 
 
1092 
#define                       CAN0_CLOCK  0xffc02a80   /* CAN Controller 0 Clock Register */
1093 
#define                      CAN0_TIMING  0xffc02a84   /* CAN Controller 0 Timing Register */
1094 
#define                       CAN0_DEBUG  0xffc02a88   /* CAN Controller 0 Debug Register */
1095 
#define                      CAN0_STATUS  0xffc02a8c   /* CAN Controller 0 Global Status Register */
1096 
#define                         CAN0_CEC  0xffc02a90   /* CAN Controller 0 Error Counter Register */
1097 
#define                         CAN0_GIS  0xffc02a94   /* CAN Controller 0 Global Interrupt Status Register */
1098 
#define                         CAN0_GIM  0xffc02a98   /* CAN Controller 0 Global Interrupt Mask Register */
1099 
#define                         CAN0_GIF  0xffc02a9c   /* CAN Controller 0 Global Interrupt Flag Register */
1100 
#define                     CAN0_CONTROL  0xffc02aa0   /* CAN Controller 0 Master Control Register */
1101 
#define                        CAN0_INTR  0xffc02aa4   /* CAN Controller 0 Interrupt Pending Register */
1102 
#define                        CAN0_MBTD  0xffc02aac   /* CAN Controller 0 Mailbox Temporary Disable Register */
1103 
#define                         CAN0_EWR  0xffc02ab0   /* CAN Controller 0 Programmable Warning Level Register */
1104 
#define                         CAN0_ESR  0xffc02ab4   /* CAN Controller 0 Error Status Register */
1105 
#define                       CAN0_UCCNT  0xffc02ac4   /* CAN Controller 0 Universal Counter Register */
1106 
#define                        CAN0_UCRC  0xffc02ac8   /* Universal Counter Reload/Capture Register */
1107 
#define                       CAN0_UCCNF  0xffc02acc   /* CAN Controller 0 Universal Counter Configuration Register */
1108 
 
1109 
/* CAN Controller 0 Acceptance Registers */
1110 
 
1111 
#define                       CAN0_AM00L  0xffc02b00   /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
1112 
#define                       CAN0_AM00H  0xffc02b04   /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
1113 
#define                       CAN0_AM01L  0xffc02b08   /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
1114 
#define                       CAN0_AM01H  0xffc02b0c   /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
1115 
#define                       CAN0_AM02L  0xffc02b10   /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
1116 
#define                       CAN0_AM02H  0xffc02b14   /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
1117 
#define                       CAN0_AM03L  0xffc02b18   /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
1118 
#define                       CAN0_AM03H  0xffc02b1c   /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
1119 
#define                       CAN0_AM04L  0xffc02b20   /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
1120 
#define                       CAN0_AM04H  0xffc02b24   /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
1121 
#define                       CAN0_AM05L  0xffc02b28   /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
1122 
#define                       CAN0_AM05H  0xffc02b2c   /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
1123 
#define                       CAN0_AM06L  0xffc02b30   /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
1124 
#define                       CAN0_AM06H  0xffc02b34   /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
1125 
#define                       CAN0_AM07L  0xffc02b38   /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
1126 
#define                       CAN0_AM07H  0xffc02b3c   /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
1127 
#define                       CAN0_AM08L  0xffc02b40   /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
1128 
#define                       CAN0_AM08H  0xffc02b44   /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
1129 
#define                       CAN0_AM09L  0xffc02b48   /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
1130 
#define                       CAN0_AM09H  0xffc02b4c   /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
1131 
#define                       CAN0_AM10L  0xffc02b50   /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
1132 
#define                       CAN0_AM10H  0xffc02b54   /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
1133 
#define                       CAN0_AM11L  0xffc02b58   /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
1134 
#define                       CAN0_AM11H  0xffc02b5c   /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
1135 
#define                       CAN0_AM12L  0xffc02b60   /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
1136 
#define                       CAN0_AM12H  0xffc02b64   /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
1137 
#define                       CAN0_AM13L  0xffc02b68   /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
1138 
#define                       CAN0_AM13H  0xffc02b6c   /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
1139 
#define                       CAN0_AM14L  0xffc02b70   /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
1140 
#define                       CAN0_AM14H  0xffc02b74   /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
1141 
#define                       CAN0_AM15L  0xffc02b78   /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
1142 
#define                       CAN0_AM15H  0xffc02b7c   /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
1143 
 
1144 
/* CAN Controller 0 Acceptance Registers */
1145 
 
1146 
#define                       CAN0_AM16L  0xffc02b80   /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
1147 
#define                       CAN0_AM16H  0xffc02b84   /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
1148 
#define                       CAN0_AM17L  0xffc02b88   /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
1149 
#define                       CAN0_AM17H  0xffc02b8c   /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
1150 
#define                       CAN0_AM18L  0xffc02b90   /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
1151 
#define                       CAN0_AM18H  0xffc02b94   /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
1152 
#define                       CAN0_AM19L  0xffc02b98   /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
1153 
#define                       CAN0_AM19H  0xffc02b9c   /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
1154 
#define                       CAN0_AM20L  0xffc02ba0   /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
1155 
#define                       CAN0_AM20H  0xffc02ba4   /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
1156 
#define                       CAN0_AM21L  0xffc02ba8   /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
1157 
#define                       CAN0_AM21H  0xffc02bac   /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
1158 
#define                       CAN0_AM22L  0xffc02bb0   /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
1159 
#define                       CAN0_AM22H  0xffc02bb4   /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
1160 
#define                       CAN0_AM23L  0xffc02bb8   /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
1161 
#define                       CAN0_AM23H  0xffc02bbc   /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
1162 
#define                       CAN0_AM24L  0xffc02bc0   /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
1163 
#define                       CAN0_AM24H  0xffc02bc4   /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
1164 
#define                       CAN0_AM25L  0xffc02bc8   /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
1165 
#define                       CAN0_AM25H  0xffc02bcc   /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
1166 
#define                       CAN0_AM26L  0xffc02bd0   /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
1167 
#define                       CAN0_AM26H  0xffc02bd4   /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
1168 
#define                       CAN0_AM27L  0xffc02bd8   /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
1169 
#define                       CAN0_AM27H  0xffc02bdc   /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
1170 
#define                       CAN0_AM28L  0xffc02be0   /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
1171 
#define                       CAN0_AM28H  0xffc02be4   /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
1172 
#define                       CAN0_AM29L  0xffc02be8   /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
1173 
#define                       CAN0_AM29H  0xffc02bec   /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
1174 
#define                       CAN0_AM30L  0xffc02bf0   /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
1175 
#define                       CAN0_AM30H  0xffc02bf4   /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
1176 
#define                       CAN0_AM31L  0xffc02bf8   /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
1177 
#define                       CAN0_AM31H  0xffc02bfc   /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
1178 
 
1179 
/* CAN Controller 0 Mailbox Data Registers */
1180 
 
1181 
#define                  CAN0_MB00_DATA0  0xffc02c00   /* CAN Controller 0 Mailbox 0 Data 0 Register */
1182 
#define                  CAN0_MB00_DATA1  0xffc02c04   /* CAN Controller 0 Mailbox 0 Data 1 Register */
1183 
#define                  CAN0_MB00_DATA2  0xffc02c08   /* CAN Controller 0 Mailbox 0 Data 2 Register */
1184 
#define                  CAN0_MB00_DATA3  0xffc02c0c   /* CAN Controller 0 Mailbox 0 Data 3 Register */
1185 
#define                 CAN0_MB00_LENGTH  0xffc02c10   /* CAN Controller 0 Mailbox 0 Length Register */
1186 
#define              CAN0_MB00_TIMESTAMP  0xffc02c14   /* CAN Controller 0 Mailbox 0 Timestamp Register */
1187 
#define                    CAN0_MB00_ID0  0xffc02c18   /* CAN Controller 0 Mailbox 0 ID0 Register */
1188 
#define                    CAN0_MB00_ID1  0xffc02c1c   /* CAN Controller 0 Mailbox 0 ID1 Register */
1189 
#define                  CAN0_MB01_DATA0  0xffc02c20   /* CAN Controller 0 Mailbox 1 Data 0 Register */
1190 
#define                  CAN0_MB01_DATA1  0xffc02c24   /* CAN Controller 0 Mailbox 1 Data 1 Register */
1191 
#define                  CAN0_MB01_DATA2  0xffc02c28   /* CAN Controller 0 Mailbox 1 Data 2 Register */
1192 
#define                  CAN0_MB01_DATA3  0xffc02c2c   /* CAN Controller 0 Mailbox 1 Data 3 Register */
1193 
#define                 CAN0_MB01_LENGTH  0xffc02c30   /* CAN Controller 0 Mailbox 1 Length Register */
1194 
#define              CAN0_MB01_TIMESTAMP  0xffc02c34   /* CAN Controller 0 Mailbox 1 Timestamp Register */
1195 
#define                    CAN0_MB01_ID0  0xffc02c38   /* CAN Controller 0 Mailbox 1 ID0 Register */
1196 
#define                    CAN0_MB01_ID1  0xffc02c3c   /* CAN Controller 0 Mailbox 1 ID1 Register */
1197 
#define                  CAN0_MB02_DATA0  0xffc02c40   /* CAN Controller 0 Mailbox 2 Data 0 Register */
1198 
#define                  CAN0_MB02_DATA1  0xffc02c44   /* CAN Controller 0 Mailbox 2 Data 1 Register */
1199 
#define                  CAN0_MB02_DATA2  0xffc02c48   /* CAN Controller 0 Mailbox 2 Data 2 Register */
1200 
#define                  CAN0_MB02_DATA3  0xffc02c4c   /* CAN Controller 0 Mailbox 2 Data 3 Register */
1201 
#define                 CAN0_MB02_LENGTH  0xffc02c50   /* CAN Controller 0 Mailbox 2 Length Register */
1202 
#define              CAN0_MB02_TIMESTAMP  0xffc02c54   /* CAN Controller 0 Mailbox 2 Timestamp Register */
1203 
#define                    CAN0_MB02_ID0  0xffc02c58   /* CAN Controller 0 Mailbox 2 ID0 Register */
1204 
#define                    CAN0_MB02_ID1  0xffc02c5c   /* CAN Controller 0 Mailbox 2 ID1 Register */
1205 
#define                  CAN0_MB03_DATA0  0xffc02c60   /* CAN Controller 0 Mailbox 3 Data 0 Register */
1206 
#define                  CAN0_MB03_DATA1  0xffc02c64   /* CAN Controller 0 Mailbox 3 Data 1 Register */
1207 
#define                  CAN0_MB03_DATA2  0xffc02c68   /* CAN Controller 0 Mailbox 3 Data 2 Register */
1208 
#define                  CAN0_MB03_DATA3  0xffc02c6c   /* CAN Controller 0 Mailbox 3 Data 3 Register */
1209 
#define                 CAN0_MB03_LENGTH  0xffc02c70   /* CAN Controller 0 Mailbox 3 Length Register */
1210 
#define              CAN0_MB03_TIMESTAMP  0xffc02c74   /* CAN Controller 0 Mailbox 3 Timestamp Register */
1211 
#define                    CAN0_MB03_ID0  0xffc02c78   /* CAN Controller 0 Mailbox 3 ID0 Register */
1212 
#define                    CAN0_MB03_ID1  0xffc02c7c   /* CAN Controller 0 Mailbox 3 ID1 Register */
1213 
#define                  CAN0_MB04_DATA0  0xffc02c80   /* CAN Controller 0 Mailbox 4 Data 0 Register */
1214 
#define                  CAN0_MB04_DATA1  0xffc02c84   /* CAN Controller 0 Mailbox 4 Data 1 Register */
1215 
#define                  CAN0_MB04_DATA2  0xffc02c88   /* CAN Controller 0 Mailbox 4 Data 2 Register */
1216 
#define                  CAN0_MB04_DATA3  0xffc02c8c   /* CAN Controller 0 Mailbox 4 Data 3 Register */
1217 
#define                 CAN0_MB04_LENGTH  0xffc02c90   /* CAN Controller 0 Mailbox 4 Length Register */
1218 
#define              CAN0_MB04_TIMESTAMP  0xffc02c94   /* CAN Controller 0 Mailbox 4 Timestamp Register */
1219 
#define                    CAN0_MB04_ID0  0xffc02c98   /* CAN Controller 0 Mailbox 4 ID0 Register */
1220 
#define                    CAN0_MB04_ID1  0xffc02c9c   /* CAN Controller 0 Mailbox 4 ID1 Register */
1221 
#define                  CAN0_MB05_DATA0  0xffc02ca0   /* CAN Controller 0 Mailbox 5 Data 0 Register */
1222 
#define                  CAN0_MB05_DATA1  0xffc02ca4   /* CAN Controller 0 Mailbox 5 Data 1 Register */
1223 
#define                  CAN0_MB05_DATA2  0xffc02ca8   /* CAN Controller 0 Mailbox 5 Data 2 Register */
1224 
#define                  CAN0_MB05_DATA3  0xffc02cac   /* CAN Controller 0 Mailbox 5 Data 3 Register */
1225 
#define                 CAN0_MB05_LENGTH  0xffc02cb0   /* CAN Controller 0 Mailbox 5 Length Register */
1226 
#define              CAN0_MB05_TIMESTAMP  0xffc02cb4   /* CAN Controller 0 Mailbox 5 Timestamp Register */
1227 
#define                    CAN0_MB05_ID0  0xffc02cb8   /* CAN Controller 0 Mailbox 5 ID0 Register */
1228 
#define                    CAN0_MB05_ID1  0xffc02cbc   /* CAN Controller 0 Mailbox 5 ID1 Register */
1229 
#define                  CAN0_MB06_DATA0  0xffc02cc0   /* CAN Controller 0 Mailbox 6 Data 0 Register */
1230 
#define                  CAN0_MB06_DATA1  0xffc02cc4   /* CAN Controller 0 Mailbox 6 Data 1 Register */
1231 
#define                  CAN0_MB06_DATA2  0xffc02cc8   /* CAN Controller 0 Mailbox 6 Data 2 Register */
1232 
#define                  CAN0_MB06_DATA3  0xffc02ccc   /* CAN Controller 0 Mailbox 6 Data 3 Register */
1233 
#define                 CAN0_MB06_LENGTH  0xffc02cd0   /* CAN Controller 0 Mailbox 6 Length Register */
1234 
#define              CAN0_MB06_TIMESTAMP  0xffc02cd4   /* CAN Controller 0 Mailbox 6 Timestamp Register */
1235 
#define                    CAN0_MB06_ID0  0xffc02cd8   /* CAN Controller 0 Mailbox 6 ID0 Register */
1236 
#define                    CAN0_MB06_ID1  0xffc02cdc   /* CAN Controller 0 Mailbox 6 ID1 Register */
1237 
#define                  CAN0_MB07_DATA0  0xffc02ce0   /* CAN Controller 0 Mailbox 7 Data 0 Register */
1238 
#define                  CAN0_MB07_DATA1  0xffc02ce4   /* CAN Controller 0 Mailbox 7 Data 1 Register */
1239 
#define                  CAN0_MB07_DATA2  0xffc02ce8   /* CAN Controller 0 Mailbox 7 Data 2 Register */
1240 
#define                  CAN0_MB07_DATA3  0xffc02cec   /* CAN Controller 0 Mailbox 7 Data 3 Register */
1241 
#define                 CAN0_MB07_LENGTH  0xffc02cf0   /* CAN Controller 0 Mailbox 7 Length Register */
1242 
#define              CAN0_MB07_TIMESTAMP  0xffc02cf4   /* CAN Controller 0 Mailbox 7 Timestamp Register */
1243 
#define                    CAN0_MB07_ID0  0xffc02cf8   /* CAN Controller 0 Mailbox 7 ID0 Register */
1244 
#define                    CAN0_MB07_ID1  0xffc02cfc   /* CAN Controller 0 Mailbox 7 ID1 Register */
1245 
#define                  CAN0_MB08_DATA0  0xffc02d00   /* CAN Controller 0 Mailbox 8 Data 0 Register */
1246 
#define                  CAN0_MB08_DATA1  0xffc02d04   /* CAN Controller 0 Mailbox 8 Data 1 Register */
1247 
#define                  CAN0_MB08_DATA2  0xffc02d08   /* CAN Controller 0 Mailbox 8 Data 2 Register */
1248 
#define                  CAN0_MB08_DATA3  0xffc02d0c   /* CAN Controller 0 Mailbox 8 Data 3 Register */
1249 
#define                 CAN0_MB08_LENGTH  0xffc02d10   /* CAN Controller 0 Mailbox 8 Length Register */
1250 
#define              CAN0_MB08_TIMESTAMP  0xffc02d14   /* CAN Controller 0 Mailbox 8 Timestamp Register */
1251 
#define                    CAN0_MB08_ID0  0xffc02d18   /* CAN Controller 0 Mailbox 8 ID0 Register */
1252 
#define                    CAN0_MB08_ID1  0xffc02d1c   /* CAN Controller 0 Mailbox 8 ID1 Register */
1253 
#define                  CAN0_MB09_DATA0  0xffc02d20   /* CAN Controller 0 Mailbox 9 Data 0 Register */
1254 
#define                  CAN0_MB09_DATA1  0xffc02d24   /* CAN Controller 0 Mailbox 9 Data 1 Register */
1255 
#define                  CAN0_MB09_DATA2  0xffc02d28   /* CAN Controller 0 Mailbox 9 Data 2 Register */
1256 
#define                  CAN0_MB09_DATA3  0xffc02d2c   /* CAN Controller 0 Mailbox 9 Data 3 Register */
1257 
#define                 CAN0_MB09_LENGTH  0xffc02d30   /* CAN Controller 0 Mailbox 9 Length Register */
1258 
#define              CAN0_MB09_TIMESTAMP  0xffc02d34   /* CAN Controller 0 Mailbox 9 Timestamp Register */
1259 
#define                    CAN0_MB09_ID0  0xffc02d38   /* CAN Controller 0 Mailbox 9 ID0 Register */
1260 
#define                    CAN0_MB09_ID1  0xffc02d3c   /* CAN Controller 0 Mailbox 9 ID1 Register */
1261 
#define                  CAN0_MB10_DATA0  0xffc02d40   /* CAN Controller 0 Mailbox 10 Data 0 Register */
1262 
#define                  CAN0_MB10_DATA1  0xffc02d44   /* CAN Controller 0 Mailbox 10 Data 1 Register */
1263 
#define                  CAN0_MB10_DATA2  0xffc02d48   /* CAN Controller 0 Mailbox 10 Data 2 Register */
1264 
#define                  CAN0_MB10_DATA3  0xffc02d4c   /* CAN Controller 0 Mailbox 10 Data 3 Register */
1265 
#define                 CAN0_MB10_LENGTH  0xffc02d50   /* CAN Controller 0 Mailbox 10 Length Register */
1266 
#define              CAN0_MB10_TIMESTAMP  0xffc02d54   /* CAN Controller 0 Mailbox 10 Timestamp Register */
1267 
#define                    CAN0_MB10_ID0  0xffc02d58   /* CAN Controller 0 Mailbox 10 ID0 Register */
1268 
#define                    CAN0_MB10_ID1  0xffc02d5c   /* CAN Controller 0 Mailbox 10 ID1 Register */
1269 
#define                  CAN0_MB11_DATA0  0xffc02d60   /* CAN Controller 0 Mailbox 11 Data 0 Register */
1270 
#define                  CAN0_MB11_DATA1  0xffc02d64   /* CAN Controller 0 Mailbox 11 Data 1 Register */
1271 
#define                  CAN0_MB11_DATA2  0xffc02d68   /* CAN Controller 0 Mailbox 11 Data 2 Register */
1272 
#define                  CAN0_MB11_DATA3  0xffc02d6c   /* CAN Controller 0 Mailbox 11 Data 3 Register */
1273 
#define                 CAN0_MB11_LENGTH  0xffc02d70   /* CAN Controller 0 Mailbox 11 Length Register */
1274 
#define              CAN0_MB11_TIMESTAMP  0xffc02d74   /* CAN Controller 0 Mailbox 11 Timestamp Register */
1275 
#define                    CAN0_MB11_ID0  0xffc02d78   /* CAN Controller 0 Mailbox 11 ID0 Register */
1276 
#define                    CAN0_MB11_ID1  0xffc02d7c   /* CAN Controller 0 Mailbox 11 ID1 Register */
1277 
#define                  CAN0_MB12_DATA0  0xffc02d80   /* CAN Controller 0 Mailbox 12 Data 0 Register */
1278 
#define                  CAN0_MB12_DATA1  0xffc02d84   /* CAN Controller 0 Mailbox 12 Data 1 Register */
1279 
#define                  CAN0_MB12_DATA2  0xffc02d88   /* CAN Controller 0 Mailbox 12 Data 2 Register */
1280 
#define                  CAN0_MB12_DATA3  0xffc02d8c   /* CAN Controller 0 Mailbox 12 Data 3 Register */
1281 
#define                 CAN0_MB12_LENGTH  0xffc02d90   /* CAN Controller 0 Mailbox 12 Length Register */
1282 
#define              CAN0_MB12_TIMESTAMP  0xffc02d94   /* CAN Controller 0 Mailbox 12 Timestamp Register */
1283 
#define                    CAN0_MB12_ID0  0xffc02d98   /* CAN Controller 0 Mailbox 12 ID0 Register */
1284 
#define                    CAN0_MB12_ID1  0xffc02d9c   /* CAN Controller 0 Mailbox 12 ID1 Register */
1285 
#define                  CAN0_MB13_DATA0  0xffc02da0   /* CAN Controller 0 Mailbox 13 Data 0 Register */
1286 
#define                  CAN0_MB13_DATA1  0xffc02da4   /* CAN Controller 0 Mailbox 13 Data 1 Register */
1287 
#define                  CAN0_MB13_DATA2  0xffc02da8   /* CAN Controller 0 Mailbox 13 Data 2 Register */
1288 
#define                  CAN0_MB13_DATA3  0xffc02dac   /* CAN Controller 0 Mailbox 13 Data 3 Register */
1289 
#define                 CAN0_MB13_LENGTH  0xffc02db0   /* CAN Controller 0 Mailbox 13 Length Register */
1290 
#define              CAN0_MB13_TIMESTAMP  0xffc02db4   /* CAN Controller 0 Mailbox 13 Timestamp Register */
1291 
#define                    CAN0_MB13_ID0  0xffc02db8   /* CAN Controller 0 Mailbox 13 ID0 Register */
1292 
#define                    CAN0_MB13_ID1  0xffc02dbc   /* CAN Controller 0 Mailbox 13 ID1 Register */
1293 
#define                  CAN0_MB14_DATA0  0xffc02dc0   /* CAN Controller 0 Mailbox 14 Data 0 Register */
1294 
#define                  CAN0_MB14_DATA1  0xffc02dc4   /* CAN Controller 0 Mailbox 14 Data 1 Register */
1295 
#define                  CAN0_MB14_DATA2  0xffc02dc8   /* CAN Controller 0 Mailbox 14 Data 2 Register */
1296 
#define                  CAN0_MB14_DATA3  0xffc02dcc   /* CAN Controller 0 Mailbox 14 Data 3 Register */
1297 
#define                 CAN0_MB14_LENGTH  0xffc02dd0   /* CAN Controller 0 Mailbox 14 Length Register */
1298 
#define              CAN0_MB14_TIMESTAMP  0xffc02dd4   /* CAN Controller 0 Mailbox 14 Timestamp Register */
1299 
#define                    CAN0_MB14_ID0  0xffc02dd8   /* CAN Controller 0 Mailbox 14 ID0 Register */
1300 
#define                    CAN0_MB14_ID1  0xffc02ddc   /* CAN Controller 0 Mailbox 14 ID1 Register */
1301 
#define                  CAN0_MB15_DATA0  0xffc02de0   /* CAN Controller 0 Mailbox 15 Data 0 Register */
1302 
#define                  CAN0_MB15_DATA1  0xffc02de4   /* CAN Controller 0 Mailbox 15 Data 1 Register */
1303 
#define                  CAN0_MB15_DATA2  0xffc02de8   /* CAN Controller 0 Mailbox 15 Data 2 Register */
1304 
#define                  CAN0_MB15_DATA3  0xffc02dec   /* CAN Controller 0 Mailbox 15 Data 3 Register */
1305 
#define                 CAN0_MB15_LENGTH  0xffc02df0   /* CAN Controller 0 Mailbox 15 Length Register */
1306 
#define              CAN0_MB15_TIMESTAMP  0xffc02df4   /* CAN Controller 0 Mailbox 15 Timestamp Register */
1307 
#define                    CAN0_MB15_ID0  0xffc02df8   /* CAN Controller 0 Mailbox 15 ID0 Register */
1308 
#define                    CAN0_MB15_ID1  0xffc02dfc   /* CAN Controller 0 Mailbox 15 ID1 Register */
1309 
 
1310 
/* CAN Controller 0 Mailbox Data Registers */
1311 
 
1312 
#define                  CAN0_MB16_DATA0  0xffc02e00   /* CAN Controller 0 Mailbox 16 Data 0 Register */
1313 
#define                  CAN0_MB16_DATA1  0xffc02e04   /* CAN Controller 0 Mailbox 16 Data 1 Register */
1314 
#define                  CAN0_MB16_DATA2  0xffc02e08   /* CAN Controller 0 Mailbox 16 Data 2 Register */
1315 
#define                  CAN0_MB16_DATA3  0xffc02e0c   /* CAN Controller 0 Mailbox 16 Data 3 Register */
1316 
#define                 CAN0_MB16_LENGTH  0xffc02e10   /* CAN Controller 0 Mailbox 16 Length Register */
1317 
#define              CAN0_MB16_TIMESTAMP  0xffc02e14   /* CAN Controller 0 Mailbox 16 Timestamp Register */
1318 
#define                    CAN0_MB16_ID0  0xffc02e18   /* CAN Controller 0 Mailbox 16 ID0 Register */
1319 
#define                    CAN0_MB16_ID1  0xffc02e1c   /* CAN Controller 0 Mailbox 16 ID1 Register */
1320 
#define                  CAN0_MB17_DATA0  0xffc02e20   /* CAN Controller 0 Mailbox 17 Data 0 Register */
1321 
#define                  CAN0_MB17_DATA1  0xffc02e24   /* CAN Controller 0 Mailbox 17 Data 1 Register */
1322 
#define                  CAN0_MB17_DATA2  0xffc02e28   /* CAN Controller 0 Mailbox 17 Data 2 Register */
1323 
#define                  CAN0_MB17_DATA3  0xffc02e2c   /* CAN Controller 0 Mailbox 17 Data 3 Register */
1324 
#define                 CAN0_MB17_LENGTH  0xffc02e30   /* CAN Controller 0 Mailbox 17 Length Register */
1325 
#define              CAN0_MB17_TIMESTAMP  0xffc02e34   /* CAN Controller 0 Mailbox 17 Timestamp Register */
1326 
#define                    CAN0_MB17_ID0  0xffc02e38   /* CAN Controller 0 Mailbox 17 ID0 Register */
1327 
#define                    CAN0_MB17_ID1  0xffc02e3c   /* CAN Controller 0 Mailbox 17 ID1 Register */
1328 
#define                  CAN0_MB18_DATA0  0xffc02e40   /* CAN Controller 0 Mailbox 18 Data 0 Register */
1329 
#define                  CAN0_MB18_DATA1  0xffc02e44   /* CAN Controller 0 Mailbox 18 Data 1 Register */
1330 
#define                  CAN0_MB18_DATA2  0xffc02e48   /* CAN Controller 0 Mailbox 18 Data 2 Register */
1331 
#define                  CAN0_MB18_DATA3  0xffc02e4c   /* CAN Controller 0 Mailbox 18 Data 3 Register */
1332 
#define                 CAN0_MB18_LENGTH  0xffc02e50   /* CAN Controller 0 Mailbox 18 Length Register */
1333 
#define              CAN0_MB18_TIMESTAMP  0xffc02e54   /* CAN Controller 0 Mailbox 18 Timestamp Register */
1334 
#define                    CAN0_MB18_ID0  0xffc02e58   /* CAN Controller 0 Mailbox 18 ID0 Register */
1335 
#define                    CAN0_MB18_ID1  0xffc02e5c   /* CAN Controller 0 Mailbox 18 ID1 Register */
1336 
#define                  CAN0_MB19_DATA0  0xffc02e60   /* CAN Controller 0 Mailbox 19 Data 0 Register */
1337 
#define                  CAN0_MB19_DATA1  0xffc02e64   /* CAN Controller 0 Mailbox 19 Data 1 Register */
1338 
#define                  CAN0_MB19_DATA2  0xffc02e68   /* CAN Controller 0 Mailbox 19 Data 2 Register */
1339 
#define                  CAN0_MB19_DATA3  0xffc02e6c   /* CAN Controller 0 Mailbox 19 Data 3 Register */
1340 
#define                 CAN0_MB19_LENGTH  0xffc02e70   /* CAN Controller 0 Mailbox 19 Length Register */
1341 
#define              CAN0_MB19_TIMESTAMP  0xffc02e74   /* CAN Controller 0 Mailbox 19 Timestamp Register */
1342 
#define                    CAN0_MB19_ID0  0xffc02e78   /* CAN Controller 0 Mailbox 19 ID0 Register */
1343 
#define                    CAN0_MB19_ID1  0xffc02e7c   /* CAN Controller 0 Mailbox 19 ID1 Register */
1344 
#define                  CAN0_MB20_DATA0  0xffc02e80   /* CAN Controller 0 Mailbox 20 Data 0 Register */
1345 
#define                  CAN0_MB20_DATA1  0xffc02e84   /* CAN Controller 0 Mailbox 20 Data 1 Register */
1346 
#define                  CAN0_MB20_DATA2  0xffc02e88   /* CAN Controller 0 Mailbox 20 Data 2 Register */
1347 
#define                  CAN0_MB20_DATA3  0xffc02e8c   /* CAN Controller 0 Mailbox 20 Data 3 Register */
1348 
#define                 CAN0_MB20_LENGTH  0xffc02e90   /* CAN Controller 0 Mailbox 20 Length Register */
1349 
#define              CAN0_MB20_TIMESTAMP  0xffc02e94   /* CAN Controller 0 Mailbox 20 Timestamp Register */
1350 
#define                    CAN0_MB20_ID0  0xffc02e98   /* CAN Controller 0 Mailbox 20 ID0 Register */
1351 
#define                    CAN0_MB20_ID1  0xffc02e9c   /* CAN Controller 0 Mailbox 20 ID1 Register */
1352 
#define                  CAN0_MB21_DATA0  0xffc02ea0   /* CAN Controller 0 Mailbox 21 Data 0 Register */
1353 
#define                  CAN0_MB21_DATA1  0xffc02ea4   /* CAN Controller 0 Mailbox 21 Data 1 Register */
1354 
#define                  CAN0_MB21_DATA2  0xffc02ea8   /* CAN Controller 0 Mailbox 21 Data 2 Register */
1355 
#define                  CAN0_MB21_DATA3  0xffc02eac   /* CAN Controller 0 Mailbox 21 Data 3 Register */
1356 
#define                 CAN0_MB21_LENGTH  0xffc02eb0   /* CAN Controller 0 Mailbox 21 Length Register */
1357 
#define              CAN0_MB21_TIMESTAMP  0xffc02eb4   /* CAN Controller 0 Mailbox 21 Timestamp Register */
1358 
#define                    CAN0_MB21_ID0  0xffc02eb8   /* CAN Controller 0 Mailbox 21 ID0 Register */
1359 
#define                    CAN0_MB21_ID1  0xffc02ebc   /* CAN Controller 0 Mailbox 21 ID1 Register */
1360 
#define                  CAN0_MB22_DATA0  0xffc02ec0   /* CAN Controller 0 Mailbox 22 Data 0 Register */
1361 
#define                  CAN0_MB22_DATA1  0xffc02ec4   /* CAN Controller 0 Mailbox 22 Data 1 Register */
1362 
#define                  CAN0_MB22_DATA2  0xffc02ec8   /* CAN Controller 0 Mailbox 22 Data 2 Register */
1363 
#define                  CAN0_MB22_DATA3  0xffc02ecc   /* CAN Controller 0 Mailbox 22 Data 3 Register */
1364 
#define                 CAN0_MB22_LENGTH  0xffc02ed0   /* CAN Controller 0 Mailbox 22 Length Register */
1365 
#define              CAN0_MB22_TIMESTAMP  0xffc02ed4   /* CAN Controller 0 Mailbox 22 Timestamp Register */
1366 
#define                    CAN0_MB22_ID0  0xffc02ed8   /* CAN Controller 0 Mailbox 22 ID0 Register */
1367 
#define                    CAN0_MB22_ID1  0xffc02edc   /* CAN Controller 0 Mailbox 22 ID1 Register */
1368 
#define                  CAN0_MB23_DATA0  0xffc02ee0   /* CAN Controller 0 Mailbox 23 Data 0 Register */
1369 
#define                  CAN0_MB23_DATA1  0xffc02ee4   /* CAN Controller 0 Mailbox 23 Data 1 Register */
1370 
#define                  CAN0_MB23_DATA2  0xffc02ee8   /* CAN Controller 0 Mailbox 23 Data 2 Register */
1371 
#define                  CAN0_MB23_DATA3  0xffc02eec   /* CAN Controller 0 Mailbox 23 Data 3 Register */
1372 
#define                 CAN0_MB23_LENGTH  0xffc02ef0   /* CAN Controller 0 Mailbox 23 Length Register */
1373 
#define              CAN0_MB23_TIMESTAMP  0xffc02ef4   /* CAN Controller 0 Mailbox 23 Timestamp Register */
1374 
#define                    CAN0_MB23_ID0  0xffc02ef8   /* CAN Controller 0 Mailbox 23 ID0 Register */
1375 
#define                    CAN0_MB23_ID1  0xffc02efc   /* CAN Controller 0 Mailbox 23 ID1 Register */
1376 
#define                  CAN0_MB24_DATA0  0xffc02f00   /* CAN Controller 0 Mailbox 24 Data 0 Register */
1377 
#define                  CAN0_MB24_DATA1  0xffc02f04   /* CAN Controller 0 Mailbox 24 Data 1 Register */
1378 
#define                  CAN0_MB24_DATA2  0xffc02f08   /* CAN Controller 0 Mailbox 24 Data 2 Register */
1379 
#define                  CAN0_MB24_DATA3  0xffc02f0c   /* CAN Controller 0 Mailbox 24 Data 3 Register */
1380 
#define                 CAN0_MB24_LENGTH  0xffc02f10   /* CAN Controller 0 Mailbox 24 Length Register */
1381 
#define              CAN0_MB24_TIMESTAMP  0xffc02f14   /* CAN Controller 0 Mailbox 24 Timestamp Register */
1382 
#define                    CAN0_MB24_ID0  0xffc02f18   /* CAN Controller 0 Mailbox 24 ID0 Register */
1383 
#define                    CAN0_MB24_ID1  0xffc02f1c   /* CAN Controller 0 Mailbox 24 ID1 Register */
1384 
#define                  CAN0_MB25_DATA0  0xffc02f20   /* CAN Controller 0 Mailbox 25 Data 0 Register */
1385 
#define                  CAN0_MB25_DATA1  0xffc02f24   /* CAN Controller 0 Mailbox 25 Data 1 Register */
1386 
#define                  CAN0_MB25_DATA2  0xffc02f28   /* CAN Controller 0 Mailbox 25 Data 2 Register */
1387 
#define                  CAN0_MB25_DATA3  0xffc02f2c   /* CAN Controller 0 Mailbox 25 Data 3 Register */
1388 
#define                 CAN0_MB25_LENGTH  0xffc02f30   /* CAN Controller 0 Mailbox 25 Length Register */
1389 
#define              CAN0_MB25_TIMESTAMP  0xffc02f34   /* CAN Controller 0 Mailbox 25 Timestamp Register */
1390 
#define                    CAN0_MB25_ID0  0xffc02f38   /* CAN Controller 0 Mailbox 25 ID0 Register */
1391 
#define                    CAN0_MB25_ID1  0xffc02f3c   /* CAN Controller 0 Mailbox 25 ID1 Register */
1392 
#define                  CAN0_MB26_DATA0  0xffc02f40   /* CAN Controller 0 Mailbox 26 Data 0 Register */
1393 
#define                  CAN0_MB26_DATA1  0xffc02f44   /* CAN Controller 0 Mailbox 26 Data 1 Register */
1394 
#define                  CAN0_MB26_DATA2  0xffc02f48   /* CAN Controller 0 Mailbox 26 Data 2 Register */
1395 
#define                  CAN0_MB26_DATA3  0xffc02f4c   /* CAN Controller 0 Mailbox 26 Data 3 Register */
1396 
#define                 CAN0_MB26_LENGTH  0xffc02f50   /* CAN Controller 0 Mailbox 26 Length Register */
1397 
#define              CAN0_MB26_TIMESTAMP  0xffc02f54   /* CAN Controller 0 Mailbox 26 Timestamp Register */
1398 
#define                    CAN0_MB26_ID0  0xffc02f58   /* CAN Controller 0 Mailbox 26 ID0 Register */
1399 
#define                    CAN0_MB26_ID1  0xffc02f5c   /* CAN Controller 0 Mailbox 26 ID1 Register */
1400 
#define                  CAN0_MB27_DATA0  0xffc02f60   /* CAN Controller 0 Mailbox 27 Data 0 Register */
1401 
#define                  CAN0_MB27_DATA1  0xffc02f64   /* CAN Controller 0 Mailbox 27 Data 1 Register */
1402 
#define                  CAN0_MB27_DATA2  0xffc02f68   /* CAN Controller 0 Mailbox 27 Data 2 Register */
1403 
#define                  CAN0_MB27_DATA3  0xffc02f6c   /* CAN Controller 0 Mailbox 27 Data 3 Register */
1404 
#define                 CAN0_MB27_LENGTH  0xffc02f70   /* CAN Controller 0 Mailbox 27 Length Register */
1405 
#define              CAN0_MB27_TIMESTAMP  0xffc02f74   /* CAN Controller 0 Mailbox 27 Timestamp Register */
1406 
#define                    CAN0_MB27_ID0  0xffc02f78   /* CAN Controller 0 Mailbox 27 ID0 Register */
1407 
#define                    CAN0_MB27_ID1  0xffc02f7c   /* CAN Controller 0 Mailbox 27 ID1 Register */
1408 
#define                  CAN0_MB28_DATA0  0xffc02f80   /* CAN Controller 0 Mailbox 28 Data 0 Register */
1409 
#define                  CAN0_MB28_DATA1  0xffc02f84   /* CAN Controller 0 Mailbox 28 Data 1 Register */
1410 
#define                  CAN0_MB28_DATA2  0xffc02f88   /* CAN Controller 0 Mailbox 28 Data 2 Register */
1411 
#define                  CAN0_MB28_DATA3  0xffc02f8c   /* CAN Controller 0 Mailbox 28 Data 3 Register */
1412 
#define                 CAN0_MB28_LENGTH  0xffc02f90   /* CAN Controller 0 Mailbox 28 Length Register */
1413 
#define              CAN0_MB28_TIMESTAMP  0xffc02f94   /* CAN Controller 0 Mailbox 28 Timestamp Register */
1414 
#define                    CAN0_MB28_ID0  0xffc02f98   /* CAN Controller 0 Mailbox 28 ID0 Register */
1415 
#define                    CAN0_MB28_ID1  0xffc02f9c   /* CAN Controller 0 Mailbox 28 ID1 Register */
1416 
#define                  CAN0_MB29_DATA0  0xffc02fa0   /* CAN Controller 0 Mailbox 29 Data 0 Register */
1417 
#define                  CAN0_MB29_DATA1  0xffc02fa4   /* CAN Controller 0 Mailbox 29 Data 1 Register */
1418 
#define                  CAN0_MB29_DATA2  0xffc02fa8   /* CAN Controller 0 Mailbox 29 Data 2 Register */
1419 
#define                  CAN0_MB29_DATA3  0xffc02fac   /* CAN Controller 0 Mailbox 29 Data 3 Register */
1420 
#define                 CAN0_MB29_LENGTH  0xffc02fb0   /* CAN Controller 0 Mailbox 29 Length Register */
1421 
#define              CAN0_MB29_TIMESTAMP  0xffc02fb4   /* CAN Controller 0 Mailbox 29 Timestamp Register */
1422 
#define                    CAN0_MB29_ID0  0xffc02fb8   /* CAN Controller 0 Mailbox 29 ID0 Register */
1423 
#define                    CAN0_MB29_ID1  0xffc02fbc   /* CAN Controller 0 Mailbox 29 ID1 Register */
1424 
#define                  CAN0_MB30_DATA0  0xffc02fc0   /* CAN Controller 0 Mailbox 30 Data 0 Register */
1425 
#define                  CAN0_MB30_DATA1  0xffc02fc4   /* CAN Controller 0 Mailbox 30 Data 1 Register */
1426 
#define                  CAN0_MB30_DATA2  0xffc02fc8   /* CAN Controller 0 Mailbox 30 Data 2 Register */
1427 
#define                  CAN0_MB30_DATA3  0xffc02fcc   /* CAN Controller 0 Mailbox 30 Data 3 Register */
1428 
#define                 CAN0_MB30_LENGTH  0xffc02fd0   /* CAN Controller 0 Mailbox 30 Length Register */
1429 
#define              CAN0_MB30_TIMESTAMP  0xffc02fd4   /* CAN Controller 0 Mailbox 30 Timestamp Register */
1430 
#define                    CAN0_MB30_ID0  0xffc02fd8   /* CAN Controller 0 Mailbox 30 ID0 Register */
1431 
#define                    CAN0_MB30_ID1  0xffc02fdc   /* CAN Controller 0 Mailbox 30 ID1 Register */
1432 
#define                  CAN0_MB31_DATA0  0xffc02fe0   /* CAN Controller 0 Mailbox 31 Data 0 Register */
1433 
#define                  CAN0_MB31_DATA1  0xffc02fe4   /* CAN Controller 0 Mailbox 31 Data 1 Register */
1434 
#define                  CAN0_MB31_DATA2  0xffc02fe8   /* CAN Controller 0 Mailbox 31 Data 2 Register */
1435 
#define                  CAN0_MB31_DATA3  0xffc02fec   /* CAN Controller 0 Mailbox 31 Data 3 Register */
1436 
#define                 CAN0_MB31_LENGTH  0xffc02ff0   /* CAN Controller 0 Mailbox 31 Length Register */
1437 
#define              CAN0_MB31_TIMESTAMP  0xffc02ff4   /* CAN Controller 0 Mailbox 31 Timestamp Register */
1438 
#define                    CAN0_MB31_ID0  0xffc02ff8   /* CAN Controller 0 Mailbox 31 ID0 Register */
1439 
#define                    CAN0_MB31_ID1  0xffc02ffc   /* CAN Controller 0 Mailbox 31 ID1 Register */
1440 
 
1441 
/* UART3 Registers */
1442 
 
1443 
#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
1444 
#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
1445 
#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
1446 
#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
1447 
#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
1448 
#define                        UART3_LSR  0xffc03114   /* Line Status Register */
1449 
#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
1450 
#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
1451 
#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
1452 
#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
1453 
#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
1454 
#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
1455 
 
1456 
/* NFC Registers */
1457 
 
1458 
#define                          NFC_CTL  0xffc03b00   /* NAND Control Register */
1459 
#define                         NFC_STAT  0xffc03b04   /* NAND Status Register */
1460 
#define                      NFC_IRQSTAT  0xffc03b08   /* NAND Interrupt Status Register */
1461 
#define                      NFC_IRQMASK  0xffc03b0c   /* NAND Interrupt Mask Register */
1462 
#define                         NFC_ECC0  0xffc03b10   /* NAND ECC Register 0 */
1463 
#define                         NFC_ECC1  0xffc03b14   /* NAND ECC Register 1 */
1464 
#define                         NFC_ECC2  0xffc03b18   /* NAND ECC Register 2 */
1465 
#define                         NFC_ECC3  0xffc03b1c   /* NAND ECC Register 3 */
1466 
#define                        NFC_COUNT  0xffc03b20   /* NAND ECC Count Register */
1467 
#define                          NFC_RST  0xffc03b24   /* NAND ECC Reset Register */
1468 
#define                        NFC_PGCTL  0xffc03b28   /* NAND Page Control Register */
1469 
#define                         NFC_READ  0xffc03b2c   /* NAND Read Data Register */
1470 
#define                         NFC_ADDR  0xffc03b40   /* NAND Address Register */
1471 
#define                          NFC_CMD  0xffc03b44   /* NAND Command Register */
1472 
#define                      NFC_DATA_WR  0xffc03b48   /* NAND Data Write Register */
1473 
#define                      NFC_DATA_RD  0xffc03b4c   /* NAND Data Read Register */
1474 
 
1475 
/* Counter Registers */
1476 
 
1477 
#define                       CNT_CONFIG  0xffc04200   /* Configuration Register */
1478 
#define                        CNT_IMASK  0xffc04204   /* Interrupt Mask Register */
1479 
#define                       CNT_STATUS  0xffc04208   /* Status Register */
1480 
#define                      CNT_COMMAND  0xffc0420c   /* Command Register */
1481 
#define                     CNT_DEBOUNCE  0xffc04210   /* Debounce Register */
1482 
#define                      CNT_COUNTER  0xffc04214   /* Counter Register */
1483 
#define                          CNT_MAX  0xffc04218   /* Maximal Count Register */
1484 
#define                          CNT_MIN  0xffc0421c   /* Minimal Count Register */
1485 
 
1486 
/* OTP/FUSE Registers */
1487 
 
1488 
#define                      OTP_CONTROL  0xffc04300   /* OTP/Fuse Control Register */
1489 
#define                          OTP_BEN  0xffc04304   /* OTP/Fuse Byte Enable */
1490 
#define                       OTP_STATUS  0xffc04308   /* OTP/Fuse Status */
1491 
#define                       OTP_TIMING  0xffc0430c   /* OTP/Fuse Access Timing */
1492 
 
1493 
/* Security Registers */
1494 
 
1495 
#define                    SECURE_SYSSWT  0xffc04320   /* Secure System Switches */
1496 
#define                   SECURE_CONTROL  0xffc04324   /* Secure Control */
1497 
#define                    SECURE_STATUS  0xffc04328   /* Secure Status */
1498 
 
1499 
/* DMA Peripheral Mux Register */
1500 
 
1501 
#define                    DMAC1_PERIMUX  0xffc04340   /* DMA Controller 1 Peripheral Multiplexer Register */
1502 
 
1503 
/* OTP Read/Write Data Buffer Registers */
1504 
 
1505 
#define                        OTP_DATA0  0xffc04380   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1506 
#define                        OTP_DATA1  0xffc04384   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1507 
#define                        OTP_DATA2  0xffc04388   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1508 
#define                        OTP_DATA3  0xffc0438c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1509 
 
1510 
/* Handshake MDMA 0 Registers */
1511 
 
1512 
#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
1513 
#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
1514 
#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
1515 
#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
1516 
#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
1517 
#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
1518 
#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
1519 
 
1520 
/* Handshake MDMA 1 Registers */
1521 
 
1522 
#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
1523 
#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
1524 
#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
1525 
#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
1526 
#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
1527 
#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
1528 
#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
1529 
 
1530 
/* ********************************************************** */
1531 
/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
1532 
/*     and MULTI BIT READ MACROS                              */
1533 
/* ********************************************************** */
1534 
 
1535 
/* Bit masks for SIC_IAR0 */
1536 
 
1537 
#define            IRQ_PLL_WAKEUP  0x1        /* PLL Wakeup */
1538 
#define           nIRQ_PLL_WAKEUP  0x0
1539 
 
1540 
/* Below is an alternate name that matches the 54x HRM and previous defBF532.h header,
1541 
   above matches previous defBF534.h header */
1542 
#define            PLL_WAKEUP_IRQ  0x1        /* PLL Wakeup Interrupt Request */
1543 
#define           nPLL_WAKEUP_IRQ  0x0
1544 
 
1545 
/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
1546 
 
1547 
#define              IRQ_DMA0_ERR  0x2        /* DMA Controller 0 Error */
1548 
#define             nIRQ_DMA0_ERR  0x0
1549 
#define             IRQ_EPPI0_ERR  0x4        /* EPPI0 Error */
1550 
#define            nIRQ_EPPI0_ERR  0x0
1551 
#define            IRQ_SPORT0_ERR  0x8        /* SPORT0 Error */
1552 
#define           nIRQ_SPORT0_ERR  0x0
1553 
#define            IRQ_SPORT1_ERR  0x10       /* SPORT1 Error */
1554 
#define           nIRQ_SPORT1_ERR  0x0
1555 
#define              IRQ_SPI0_ERR  0x20       /* SPI0 Error */
1556 
#define             nIRQ_SPI0_ERR  0x0
1557 
#define             IRQ_UART0_ERR  0x40       /* UART0 Error */
1558 
#define            nIRQ_UART0_ERR  0x0
1559 
#define                   IRQ_RTC  0x80       /* Real-Time Clock */
1560 
#define                  nIRQ_RTC  0x0
1561 
#define                 IRQ_DMA12  0x100      /* DMA Channel 12 */
1562 
#define                nIRQ_DMA12  0x0
1563 
#define                  IRQ_DMA0  0x200      /* DMA Channel 0 */
1564 
#define                 nIRQ_DMA0  0x0
1565 
#define                  IRQ_DMA1  0x400      /* DMA Channel 1 */
1566 
#define                 nIRQ_DMA1  0x0
1567 
#define                  IRQ_DMA2  0x800      /* DMA Channel 2 */
1568 
#define                 nIRQ_DMA2  0x0
1569 
#define                  IRQ_DMA3  0x1000     /* DMA Channel 3 */
1570 
#define                 nIRQ_DMA3  0x0
1571 
#define                  IRQ_DMA4  0x2000     /* DMA Channel 4 */
1572 
#define                 nIRQ_DMA4  0x0
1573 
#define                  IRQ_DMA6  0x4000     /* DMA Channel 6 */
1574 
#define                 nIRQ_DMA6  0x0
1575 
#define                  IRQ_DMA7  0x8000     /* DMA Channel 7 */
1576 
#define                 nIRQ_DMA7  0x0
1577 
#define                 IRQ_PINT0  0x80000    /* Pin Interrupt 0 */
1578 
#define                nIRQ_PINT0  0x0
1579 
#define                 IRQ_PINT1  0x100000   /* Pin Interrupt 1 */
1580 
#define                nIRQ_PINT1  0x0
1581 
#define                 IRQ_MDMA0  0x200000   /* Memory DMA Stream 0 */
1582 
#define                nIRQ_MDMA0  0x0
1583 
#define                 IRQ_MDMA1  0x400000   /* Memory DMA Stream 1 */
1584 
#define                nIRQ_MDMA1  0x0
1585 
#define                  IRQ_WDOG  0x800000   /* Watchdog Timer */
1586 
#define                 nIRQ_WDOG  0x0
1587 
#define              IRQ_DMA1_ERR  0x1000000  /* DMA Controller 1 Error */
1588 
#define             nIRQ_DMA1_ERR  0x0
1589 
#define            IRQ_SPORT2_ERR  0x2000000  /* SPORT2 Error */
1590 
#define           nIRQ_SPORT2_ERR  0x0
1591 
#define            IRQ_SPORT3_ERR  0x4000000  /* SPORT3 Error */
1592 
#define           nIRQ_SPORT3_ERR  0x0
1593 
#define               IRQ_MXVR_SD  0x8000000  /* MXVR Synchronous Data */
1594 
#define              nIRQ_MXVR_SD  0x0
1595 
#define              IRQ_SPI1_ERR  0x10000000 /* SPI1 Error */
1596 
#define             nIRQ_SPI1_ERR  0x0
1597 
#define              IRQ_SPI2_ERR  0x20000000 /* SPI2 Error */
1598 
#define             nIRQ_SPI2_ERR  0x0
1599 
#define             IRQ_UART1_ERR  0x40000000 /* UART1 Error */
1600 
#define            nIRQ_UART1_ERR  0x0
1601 
#define             IRQ_UART2_ERR  0x80000000 /* UART2 Error */
1602 
#define            nIRQ_UART2_ERR  0x0
1603 
 
1604 
/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
1605 
 
1606 
#define              IRQ_CAN0_ERR  0x1        /* CAN0 Error */
1607 
#define             nIRQ_CAN0_ERR  0x0
1608 
#define                 IRQ_DMA18  0x2        /* DMA Channel 18 */
1609 
#define                nIRQ_DMA18  0x0
1610 
#define                 IRQ_DMA19  0x4        /* DMA Channel 19 */
1611 
#define                nIRQ_DMA19  0x0
1612 
#define                 IRQ_DMA20  0x8        /* DMA Channel 20 */
1613 
#define                nIRQ_DMA20  0x0
1614 
#define                 IRQ_DMA21  0x10       /* DMA Channel 21 */
1615 
#define                nIRQ_DMA21  0x0
1616 
#define                 IRQ_DMA13  0x20       /* DMA Channel 13 */
1617 
#define                nIRQ_DMA13  0x0
1618 
#define                 IRQ_DMA14  0x40       /* DMA Channel 14 */
1619 
#define                nIRQ_DMA14  0x0
1620 
#define                  IRQ_DMA5  0x80       /* DMA Channel 5 */
1621 
#define                 nIRQ_DMA5  0x0
1622 
#define                 IRQ_DMA23  0x100      /* DMA Channel 23 */
1623 
#define                nIRQ_DMA23  0x0
1624 
#define                  IRQ_DMA8  0x200      /* DMA Channel 8 */
1625 
#define                 nIRQ_DMA8  0x0
1626 
#define                  IRQ_DMA9  0x400      /* DMA Channel 9 */
1627 
#define                 nIRQ_DMA9  0x0
1628 
#define                 IRQ_DMA10  0x800      /* DMA Channel 10 */
1629 
#define                nIRQ_DMA10  0x0
1630 
#define                 IRQ_DMA11  0x1000     /* DMA Channel 11 */
1631 
#define                nIRQ_DMA11  0x0
1632 
#define                  IRQ_TWI0  0x2000     /* TWI0 */
1633 
#define                 nIRQ_TWI0  0x0
1634 
#define                  IRQ_TWI1  0x4000     /* TWI1 */
1635 
#define                 nIRQ_TWI1  0x0
1636 
#define               IRQ_CAN0_RX  0x8000     /* CAN0 Receive */
1637 
#define              nIRQ_CAN0_RX  0x0
1638 
#define               IRQ_CAN0_TX  0x10000    /* CAN0 Transmit */
1639 
#define              nIRQ_CAN0_TX  0x0
1640 
#define                 IRQ_MDMA2  0x20000    /* Memory DMA Stream 0 */
1641 
#define                nIRQ_MDMA2  0x0
1642 
#define                 IRQ_MDMA3  0x40000    /* Memory DMA Stream 1 */
1643 
#define                nIRQ_MDMA3  0x0
1644 
#define             IRQ_MXVR_STAT  0x80000    /* MXVR Status */
1645 
#define            nIRQ_MXVR_STAT  0x0
1646 
#define               IRQ_MXVR_CM  0x100000   /* MXVR Control Message */
1647 
#define              nIRQ_MXVR_CM  0x0
1648 
#define               IRQ_MXVR_AP  0x200000   /* MXVR Asynchronous Packet */
1649 
#define              nIRQ_MXVR_AP  0x0
1650 
#define             IRQ_EPPI1_ERR  0x400000   /* EPPI1 Error */
1651 
#define            nIRQ_EPPI1_ERR  0x0
1652 
#define             IRQ_EPPI2_ERR  0x800000   /* EPPI2 Error */
1653 
#define            nIRQ_EPPI2_ERR  0x0
1654 
#define             IRQ_UART3_ERR  0x1000000  /* UART3 Error */
1655 
#define            nIRQ_UART3_ERR  0x0
1656 
#define         IRQ_HOSTDP_STATUS  0x2000000  /* Host DMA Port Error */
1657 
#define        nIRQ_HOSTDP_STATUS  0x0
1658 
#define               IRQ_USB_ERR  0x4000000  /* USB Error */
1659 
#define              nIRQ_USB_ERR  0x0
1660 
#define              IRQ_PIXC_ERR  0x8000000  /* Pixel Compositor Error */
1661 
#define             nIRQ_PIXC_ERR  0x0
1662 
#define               IRQ_NFC_ERR  0x10000000 /* Nand Flash Controller Error */
1663 
#define              nIRQ_NFC_ERR  0x0
1664 
#define             IRQ_ATAPI_ERR  0x20000000 /* ATAPI Error */
1665 
#define            nIRQ_ATAPI_ERR  0x0
1666 
#define              IRQ_CAN1_ERR  0x40000000 /* CAN1 Error */
1667 
#define             nIRQ_CAN1_ERR  0x0
1668 
#define             IRQ_DMAR0_ERR  0x80000000 /* DMAR0 Overflow Error */
1669 
#define            nIRQ_DMAR0_ERR  0x0
1670 
#define             IRQ_DMAR1_ERR  0x80000000 /* DMAR1 Overflow Error */
1671 
#define            nIRQ_DMAR1_ERR  0x0
1672 
#define                 IRQ_DMAR0  0x80000000 /* DMAR0 Block */
1673 
#define                nIRQ_DMAR0  0x0
1674 
#define                 IRQ_DMAR1  0x80000000 /* DMAR1 Block */
1675 
#define                nIRQ_DMAR1  0x0
1676 
 
1677 
/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
1678 
 
1679 
#define                 IRQ_DMA15  0x1        /* DMA Channel 15 */
1680 
#define                nIRQ_DMA15  0x0
1681 
#define                 IRQ_DMA16  0x2        /* DMA Channel 16 */
1682 
#define                nIRQ_DMA16  0x0
1683 
#define                 IRQ_DMA17  0x4        /* DMA Channel 17 */
1684 
#define                nIRQ_DMA17  0x0
1685 
#define                 IRQ_DMA22  0x8        /* DMA Channel 22 */
1686 
#define                nIRQ_DMA22  0x0
1687 
#define                   IRQ_CNT  0x10       /* Counter */
1688 
#define                  nIRQ_CNT  0x0
1689 
#define                   IRQ_KEY  0x20       /* Keypad */
1690 
#define                  nIRQ_KEY  0x0
1691 
#define               IRQ_CAN1_RX  0x40       /* CAN1 Receive */
1692 
#define              nIRQ_CAN1_RX  0x0
1693 
#define               IRQ_CAN1_TX  0x80       /* CAN1 Transmit */
1694 
#define              nIRQ_CAN1_TX  0x0
1695 
#define             IRQ_SDH_MASK0  0x100      /* SDH Mask 0 */
1696 
#define            nIRQ_SDH_MASK0  0x0
1697 
#define             IRQ_SDH_MASK1  0x200      /* SDH Mask 1 */
1698 
#define            nIRQ_SDH_MASK1  0x0
1699 
#define              IRQ_USB_EINT  0x400      /* USB Exception */
1700 
#define             nIRQ_USB_EINT  0x0
1701 
#define              IRQ_USB_INT0  0x800      /* USB Interrupt 0 */
1702 
#define             nIRQ_USB_INT0  0x0
1703 
#define              IRQ_USB_INT1  0x1000     /* USB Interrupt 1 */
1704 
#define             nIRQ_USB_INT1  0x0
1705 
#define              IRQ_USB_INT2  0x2000     /* USB Interrupt 2 */
1706 
#define             nIRQ_USB_INT2  0x0
1707 
#define            IRQ_USB_DMAINT  0x4000     /* USB DMA */
1708 
#define           nIRQ_USB_DMAINT  0x0
1709 
#define                   IRQ_OTP  0x8000     /* OTP Access Complete */
1710 
#define                  nIRQ_OTP  0x0
1711 
#define                IRQ_TIMER0  0x400000   /* Timer 0 */
1712 
#define               nIRQ_TIMER0  0x0
1713 
#define                IRQ_TIMER1  0x800000   /* Timer 1 */
1714 
#define               nIRQ_TIMER1  0x0
1715 
#define                IRQ_TIMER2  0x1000000  /* Timer 2 */
1716 
#define               nIRQ_TIMER2  0x0
1717 
#define                IRQ_TIMER3  0x2000000  /* Timer 3 */
1718 
#define               nIRQ_TIMER3  0x0
1719 
#define                IRQ_TIMER4  0x4000000  /* Timer 4 */
1720 
#define               nIRQ_TIMER4  0x0
1721 
#define                IRQ_TIMER5  0x8000000  /* Timer 5 */
1722 
#define               nIRQ_TIMER5  0x0
1723 
#define                IRQ_TIMER6  0x10000000 /* Timer 6 */
1724 
#define               nIRQ_TIMER6  0x0
1725 
#define                IRQ_TIMER7  0x20000000 /* Timer 7 */
1726 
#define               nIRQ_TIMER7  0x0
1727 
#define                 IRQ_PINT2  0x40000000 /* Pin Interrupt 2 */
1728 
#define                nIRQ_PINT2  0x0
1729 
#define                 IRQ_PINT3  0x80000000 /* Pin Interrupt 3 */
1730 
#define                nIRQ_PINT3  0x0
1731 
 
1732 
/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
1733 
 
1734 
#define                     DMAEN  0x1        /* DMA Channel Enable */
1735 
#define                    nDMAEN  0x0
1736 
#define                       WNR  0x2        /* DMA Direction */
1737 
#define                      nWNR  0x0
1738 
#define                    WDSIZE  0xc        /* Transfer Word Size */
1739 
#define                     DMA2D  0x10       /* DMA Mode */
1740 
#define                    nDMA2D  0x0
1741 
#define                      SYNC  0x20       /* Work Unit Transitions */
1742 
#define                     nSYNC  0x0
1743 
#define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
1744 
#define                   nDI_SEL  0x0
1745 
#define                     DI_EN  0x80       /* Data Interrupt Enable */
1746 
#define                    nDI_EN  0x0
1747 
#define                    NDSIZE  0xf00      /* Flex Descriptor Size */
1748 
#define                      FLOW  0xf000     /* Next Operation */
1749 
 
1750 
/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1751 
 
1752 
#define                  DMA_DONE  0x1        /* DMA Completion Interrupt Status */
1753 
#define                 nDMA_DONE  0x0
1754 
#define                   DMA_ERR  0x2        /* DMA Error Interrupt Status */
1755 
#define                  nDMA_ERR  0x0
1756 
#define                    DFETCH  0x4        /* DMA Descriptor Fetch */
1757 
#define                   nDFETCH  0x0
1758 
#define                   DMA_RUN  0x8        /* DMA Channel Running */
1759 
#define                  nDMA_RUN  0x0
1760 
 
1761 
/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1762 
 
1763 
#define                     CTYPE  0x40       /* DMA Channel Type */
1764 
#define                    nCTYPE  0x0
1765 
#define                      PMAP  0xf000     /* Peripheral Mapped To This Channel */
1766 
 
1767 
/* Bit masks for DMACx_TCPER */
1768 
 
1769 
#define        DCB_TRAFFIC_PERIOD  0xf        /* DCB Traffic Control Period */
1770 
#define        DEB_TRAFFIC_PERIOD  0xf0       /* DEB Traffic Control Period */
1771 
#define        DAB_TRAFFIC_PERIOD  0x700      /* DAB Traffic Control Period */
1772 
#define   MDMA_ROUND_ROBIN_PERIOD  0xf800     /* MDMA Round Robin Period */
1773 
 
1774 
/* Bit masks for DMACx_TCCNT */
1775 
 
1776 
#define         DCB_TRAFFIC_COUNT  0xf        /* DCB Traffic Control Count */
1777 
#define         DEB_TRAFFIC_COUNT  0xf0       /* DEB Traffic Control Count */
1778 
#define         DAB_TRAFFIC_COUNT  0x700      /* DAB Traffic Control Count */
1779 
#define    MDMA_ROUND_ROBIN_COUNT  0xf800     /* MDMA Round Robin Count */
1780 
 
1781 
/* Bit masks for DMAC1_PERIMUX */
1782 
 
1783 
#define                   PMUXSDH  0x1        /* Peripheral Select for DMA22 channel */
1784 
#define                  nPMUXSDH  0x0
1785 
 
1786 
/* Bit masks for EBIU_AMGCTL */
1787 
 
1788 
#define                    AMCKEN  0x1        /* Async Memory Enable */
1789 
#define                   nAMCKEN  0x0
1790 
#define                     AMBEN  0xe        /* Async bank enable */
1791 
 
1792 
/* EBIU_AMGCTL Masks (AMCKEN) */
1793 
#define CDPRIO                  0x0100        /* DMA has priority over core for for external accesses */
1794 
 
1795 
/* EBIU_AMGCTL Masks (AMBEN) */
1796 
#define AMBEN_NONE              0x0000        /* All Banks Disabled */
1797 
#define AMBEN_B0                0x0002        /* Enable Async Memory Bank 0 only */
1798 
#define AMBEN_B0_B1             0x0004        /* Enable Async Memory Banks 0 & 1 only */
1799 
#define AMBEN_B0_B1_B2          0x0006        /* Enable Async Memory Banks 0, 1, and 2 */
1800 
#define AMBEN_B0_B1_B2_B3       0x0008        /* Enable Async Memory Banks 0, 1,  2 and 3 */
1801 
#define AMBEN_ALL               0x0008        /* Enable All Async Memory Banks */
1802 
 
1803 
/* Bit masks for EBIU_AMBCTL0 */
1804 
 
1805 
#define                   B0RDYEN  0x1        /* Bank 0 ARDY Enable */
1806 
#define                  nB0RDYEN  0x0
1807 
#define                  B0RDYPOL  0x2        /* Bank 0 ARDY Polarity */
1808 
#define                 nB0RDYPOL  0x0
1809 
#define                      B0TT  0xc        /* Bank 0 transition time */
1810 
#define                      B0ST  0x30       /* Bank 0 Setup time */
1811 
#define                      B0HT  0xc0       /* Bank 0 Hold time */
1812 
#define                     B0RAT  0xf00      /* Bank 0 Read access time */
1813 
#define                     B0WAT  0xf000     /* Bank 0 write access time */
1814 
#define                   B1RDYEN  0x10000    /* Bank 1 ARDY Enable */
1815 
#define                  nB1RDYEN  0x0
1816 
#define                  B1RDYPOL  0x20000    /* Bank 1 ARDY Polarity */
1817 
#define                 nB1RDYPOL  0x0
1818 
#define                      B1TT  0xc0000    /* Bank 1 transition time */
1819 
#define                      B1ST  0x300000   /* Bank 1 Setup time */
1820 
#define                      B1HT  0xc00000   /* Bank 1 Hold time */
1821 
#define                     B1RAT  0xf000000  /* Bank 1 Read access time */
1822 
#define                     B1WAT  0xf0000000 /* Bank 1 write access time */
1823 
 
1824 
/* EBIU_AMBCTL0 Macros */
1825 
#ifdef _MISRA_RULES
1826 
#define SET_B1WAT(x)            (((x)&0xFu) << 28)   /* B1 Write Access Time = x cycles */
1827 
#define SET_B1RAT(x)            (((x)&0xFu) << 24)   /* B1 Read Access Time = x cycles */
1828 
#define SET_B1HT(x)             (((x)&0x3u) << 22)   /* B1 Hold Time (~Read/Write to ~AOE) = x cycles */
1829 
#define SET_B1ST(x)             (((x)&0x3u) << 20)   /* B1 Setup Time (AOE to Read/Write) = x cycle */
1830 
#define SET_B1TT(x)             (((x)&0x3u) << 18)   /* B1 Transition Time (Read to Write) = x cycles */
1831 
 
1832 
#define SET_B0WAT(x)            (((x)&0xFu) << 12)   /* B0 Write Access Time = x cycles */
1833 
#define SET_B0RAT(x)            (((x)&0xFu) << 8)    /* B0 Read Access Time = x cycles */
1834 
#define SET_B0HT(x)             (((x)&0x3u) << 6)    /* B0 Hold Time (~Read/Write to ~AOE) = x cycles */
1835 
#define SET_B0ST(x)             (((x)&0x3u) << 4)    /* B0 Setup Time (AOE to Read/Write) = x cycle */
1836 
#define SET_B0TT(x)             (((x)&0x3u) << 2)    /* B0 Transition Time (Read to Write) = x cycles */
1837 
#else
1838 
#define SET_B1WAT(x)            (((x)&0xF) << 28)   /* B1 Write Access Time = x cycles */
1839 
#define SET_B1RAT(x)            (((x)&0xF) << 24)   /* B1 Read Access Time = x cycles */
1840 
#define SET_B1HT(x)             (((x)&0x3) << 22)   /* B1 Hold Time (~Read/Write to ~AOE) = x cycles */
1841 
#define SET_B1ST(x)             (((x)&0x3) << 20)   /* B1 Setup Time (AOE to Read/Write) = x cycle */
1842 
#define SET_B1TT(x)             (((x)&0x3) << 18)   /* B1 Transition Time (Read to Write) = x cycles */
1843 
 
1844 
#define SET_B0WAT(x)            (((x)&0xF) << 12)   /* B0 Write Access Time = x cycles */
1845 
#define SET_B0RAT(x)            (((x)&0xF) << 8)    /* B0 Read Access Time = x cycles */
1846 
#define SET_B0HT(x)             (((x)&0x3) << 6)    /* B0 Hold Time (~Read/Write to ~AOE) = x cycles */
1847 
#define SET_B0ST(x)             (((x)&0x3) << 4)    /* B0 Setup Time (AOE to Read/Write) = x cycle */
1848 
#define SET_B0TT(x)             (((x)&0x3) << 2)    /* B0 Transition Time (Read to Write) = x cycles */
1849 
#endif /* _MISRA_RULES */
1850 
 
1851 
 
1852 
/* Bit masks for EBIU_AMBCTL1 */
1853 
 
1854 
#define                   B2RDYEN  0x1        /* Bank 2 ARDY Enable */
1855 
#define                  nB2RDYEN  0x0
1856 
#define                  B2RDYPOL  0x2        /* Bank 2 ARDY Polarity */
1857 
#define                 nB2RDYPOL  0x0
1858 
#define                      B2TT  0xc        /* Bank 2 transition time */
1859 
#define                      B2ST  0x30       /* Bank 2 Setup time */
1860 
#define                      B2HT  0xc0       /* Bank 2 Hold time */
1861 
#define                     B2RAT  0xf00      /* Bank 2 Read access time */
1862 
#define                     B2WAT  0xf000     /* Bank 2 write access time */
1863 
#define                   B3RDYEN  0x10000    /* Bank 3 ARDY Enable */
1864 
#define                  nB3RDYEN  0x0
1865 
#define                  B3RDYPOL  0x20000    /* Bank 3 ARDY Polarity */
1866 
#define                 nB3RDYPOL  0x0
1867 
#define                      B3TT  0xc0000    /* Bank 3 transition time */
1868 
#define                      B3ST  0x300000   /* Bank 3 Setup time */
1869 
#define                      B3HT  0xc00000   /* Bank 3 Hold time */
1870 
#define                     B3RAT  0xf000000  /* Bank 3 Read access time */
1871 
#define                     B3WAT  0xf0000000 /* Bank 3 write access time */
1872 
 
1873 
/* EBIU_AMBCTL1 Macros */
1874 
#ifdef _MISRA_RULES
1875 
#define SET_B3WAT(x)            (((x)&0xFu) << 28)   /* B3 Write Access Time = x cycles */
1876 
#define SET_B3RAT(x)            (((x)&0xFu) << 24)   /* B3 Read Access Time = x cycles */
1877 
#define SET_B3HT(x)             (((x)&0x3u) << 22)   /* B3 Hold Time (~Read/Write to ~AOE) = x cycles */
1878 
#define SET_B3ST(x)             (((x)&0x3u) << 20)   /* B3 Setup Time (AOE to Read/Write) = x cycle */
1879 
#define SET_B3TT(x)             (((x)&0x3u) << 18)   /* B3 Transition Time (Read to Write) = x cycles */
1880 
 
1881 
#define SET_B2WAT(x)            (((x)&0xFu) << 12)   /* B2 Write Access Time = x cycles */
1882 
#define SET_B2RAT(x)            (((x)&0xFu) << 8)    /* B2 Read Access Time = x cycles */
1883 
#define SET_B2HT(x)             (((x)&0x3u) << 6)    /* B2 Hold Time (~Read/Write to ~AOE) = x cycles */
1884 
#define SET_B2ST(x)             (((x)&0x3u) << 4)    /* B2 Setup Time (AOE to Read/Write) = x cycle */
1885 
#define SET_B2TT(x)             (((x)&0x3u) << 2)    /* B2 Transition Time (Read to Write) = x cycles */
1886 
#else
1887 
#define SET_B3WAT(x)            (((x)&0xF) << 28)   /* B3 Write Access Time = x cycles */
1888 
#define SET_B3RAT(x)            (((x)&0xF) << 24)   /* B3 Read Access Time = x cycles */
1889 
#define SET_B3HT(x)             (((x)&0x3) << 22)   /* B3 Hold Time (~Read/Write to ~AOE) = x cycles */
1890 
#define SET_B3ST(x)             (((x)&0x3) << 20)   /* B3 Setup Time (AOE to Read/Write) = x cycle */
1891 
#define SET_B3TT(x)             (((x)&0x3) << 18)   /* B3 Transition Time (Read to Write) = x cycles */
1892 
 
1893 
#define SET_B2WAT(x)            (((x)&0xF) << 12)   /* B2 Write Access Time = x cycles */
1894 
#define SET_B2RAT(x)            (((x)&0xF) << 8)    /* B2 Read Access Time = x cycles */
1895 
#define SET_B2HT(x)             (((x)&0x3) << 6)    /* B2 Hold Time (~Read/Write to ~AOE) = x cycles */
1896 
#define SET_B2ST(x)             (((x)&0x3) << 4)    /* B2 Setup Time (AOE to Read/Write) = x cycle */
1897 
#define SET_B2TT(x)             (((x)&0x3) << 2)    /* B2 Transition Time (Read to Write) = x cycles */
1898 
#endif /* _MISRA_RULES */
1899 
 
1900 
/* Bit masks for EBIU_MBSCTL */
1901 
 
1902 
#define                  AMSB0CTL  0x3        /* Async Memory Bank 0 select */
1903 
#define                  AMSB1CTL  0xc        /* Async Memory Bank 1 select */
1904 
#define                  AMSB2CTL  0x30       /* Async Memory Bank 2 select */
1905 
#define                  AMSB3CTL  0xc0       /* Async Memory Bank 3 select */
1906 
 
1907 
/* Bit masks for EBIU_MODE */
1908 
 
1909 
#define                    B0MODE  0x3        /* Async Memory Bank 0 Access Mode */
1910 
#define                    B1MODE  0xc        /* Async Memory Bank 1 Access Mode */
1911 
#define                    B2MODE  0x30       /* Async Memory Bank 2 Access Mode */
1912 
#define                    B3MODE  0xc0       /* Async Memory Bank 3 Access Mode */
1913 
 
1914 
/* Bit masks for EBIU_MODE (BOMODE) */
1915 
#define B0MODE_ASYNC            0x00000000          /* Bank 0 Access Mode - 00 - Asynchronous Mode */
1916 
#define B0MODE_FLASH            0x00000001          /* Bank 0 Access Mode - 01 - Asynchronous Flash Mode */
1917 
#define B0MODE_PAGE             0x00000002          /* Bank 0 Access Mode - 10 - Asynchronous Page Mode */
1918 
#define B0MODE_BURST            0x00000003          /* Bank 0 Access Mode - 11 - Synchronous (Burst) Mode */
1919 
 
1920 
/* Bit masks for EBIU_MODE (B1MODE) */
1921 
#define B1MODE_ASYNC            0x00000000          /* Bank 1 Access Mode - 00 - Asynchronous Mode */
1922 
#define B1MODE_FLASH            0x00000004          /* Bank 1 Access Mode - 01 - Asynchronous Flash Mode */
1923 
#define B1MODE_PAGE             0x00000008          /* Bank 1 Access Mode - 10 - Asynchronous Page Mode */
1924 
#define B1MODE_BURST            0x0000000C          /* Bank 1 Access Mode - 11 - Synchronous (Burst) Mode */
1925 
 
1926 
/* Bit masks for EBIU_MODE (B2MODE) */
1927 
#define B2MODE_ASYNC            0x00000000          /* Bank 2 Access Mode - 00 - Asynchronous Mode */
1928 
#define B2MODE_FLASH            0x00000010          /* Bank 2 Access Mode - 01 - Asynchronous Flash Mode */
1929 
#define B2MODE_PAGE             0x00000020          /* Bank 2 Access Mode - 10 - Asynchronous Page Mode */
1930 
#define B2MODE_BURST            0x00000030          /* Bank 2 Access Mode - 11 - Synchronous (Burst) Mode */
1931 
 
1932 
/* Bit masks for EBIU_MODE (B3MODE) */
1933 
#define B3MODE_ASYNC            0x00000000          /* Bank 3 Access Mode - 00 - Asynchronous Mode */
1934 
#define B3MODE_FLASH            0x00000040          /* Bank 3 Access Mode - 01 - Asynchronous Flash Mode */
1935 
#define B3MODE_PAGE             0x00000080          /* Bank 3 Access Mode - 10 - Asynchronous Page Mode */
1936 
#define B3MODE_BURST            0x000000C0          /* Bank 3 Access Mode - 11 - Synchronous (Burst) Mode */
1937 
 
1938 
/* Bit masks for EBIU_FCTL */
1939 
 
1940 
#define               TESTSETLOCK  0x1        /* Test set lock */
1941 
#define              nTESTSETLOCK  0x0
1942 
#define                      BCLK  0x6        /* Burst clock frequency */
1943 
#define                      PGWS  0x38       /* Page wait states */
1944 
#define                      PGSZ  0x40       /* Page size */
1945 
#define                     nPGSZ  0x0
1946 
#define                      RDDL  0x380      /* Read data delay */
1947 
 
1948 
/* Bit masks for EBIU_FCTL (BCLK) */
1949 
#define BCLK2                   0x00000002          /* Burst clock frequency: 01 - SCLK/2 */
1950 
#define BCLK3                   0x00000004          /* Burst clock frequency: 10 - SCLK/3 */
1951 
#define BCLK4                   0x00000006          /* Burst clock frequency: 11 - SCLK/4 */
1952 
 
1953 
/* Macros for EBIU_FCTL */
1954 
#ifdef _MISRA_RULES
1955 
#define SET_PGWS(x)             (((x)&0x7u) << 0x3)  /* PGWS[5:3] Page Wait States - 000 to 100 - 0 to 4 cycles */
1956 
#else
1957 
#define SET_PGWS(x)             (((x)&0x7) << 0x3)  /* PGWS[5:3] Page Wait States - 000 to 100 - 0 to 4 cycles */
1958 
#endif /* _MISRA_RULES */
1959 
                                                    /* Burst clock frequency: 00 - Reserved */
1960 
/* Bit masks for EBIU_ARBSTAT */
1961 
 
1962 
#define                   ARBSTAT  0x1        /* Arbitration status */
1963 
#define                  nARBSTAT  0x0
1964 
#define                    BGSTAT  0x2        /* Bus grant status */
1965 
#define                   nBGSTAT  0x0
1966 
 
1967 
/* Bit masks for EBIU_DDRCTL0 */
1968 
#define                     TREFI  0x3fff     /* Refresh Interval */
1969 
#define                      TRFC  0x3c000    /* Auto-refresh command period */
1970 
#define                       TRP  0x3c0000   /* Pre charge-to-active command period */
1971 
#define                      TRAS  0x3c00000  /* Min Active-to-pre charge time */
1972 
#define                       TRC  0x3c000000 /* Active-to-active time */
1973 
 
1974 
/* Macros for EBIU_DDRCTL0 */
1975 
#ifdef _MISRA_RULES
1976 
#define SET_tRC(x)              (((x)&0xFu) << 26)   /* tRC (Active-to-Active)[29:26] - Number of clock cycles from an active command to next active command (Default: 0x2) */
1977 
#define SET_tRAS(x)             (((x)&0xFu) << 22)   /* tRAS (Minimum Active-to-Precharge time) [3:0] - Number of clock cycles from an ACTIVE command until a PRE-CHARGE command is issued. To obtain this value, one should divide the minimum RAS to pre-charge delay of SDRAM by clock cycle time (Default: 0x6) */
1978 
#define SET_tRP(x)              (((x)&0xFu) << 18)   /* tRP (Precharge-to-Active Command period)[3:0] - Number of clock cycles needed for DDR to recover from a precharge command and ready to accept next active command (Default: 0x3) */
1979 
#define SET_tRFC(x)             (((x)&0xFu) << 14)   /* tRFC[3:0] AUTO-REFRESH Command Period[3:0] - Number of clock cycles needed for DDR to recover from a refresh to be ready for next active command (tRFC/Clock Period) (Default: 0xA) */
1980 
#define SET_tREFI(x)            ((x)&0x3FFFu)        /* tREFI (Refresh Interval)[13:0] - Number of clock cycles from one refresh cycle to next refresh cycle. To obtain this value, divide the DDR refresh period (tREF) by total number of rows to be refreshed. Then divide the result by total time. (Default: 0x0411) */
1981 
#else
1982 
#define SET_tRC(x)              (((x)&0xF) << 26)   /* tRC (Active-to-Active)[29:26] - Number of clock cycles from an active command to next active command (Default: 0x2) */
1983 
#define SET_tRAS(x)             (((x)&0xF) << 22)   /* tRAS (Minimum Active-to-Precharge time) [3:0] - Number of clock cycles from an ACTIVE command until a PRE-CHARGE command is issued. To obtain this value, one should divide the minimum RAS to pre-charge delay of SDRAM by clock cycle time (Default: 0x6) */
1984 
#define SET_tRP(x)              (((x)&0xF) << 18)   /* tRP (Precharge-to-Active Command period)[3:0] - Number of clock cycles needed for DDR to recover from a precharge command and ready to accept next active command (Default: 0x3) */
1985 
#define SET_tRFC(x)             (((x)&0xF) << 14)   /* tRFC[3:0] AUTO-REFRESH Command Period[3:0] - Number of clock cycles needed for DDR to recover from a refresh to be ready for next active command (tRFC/Clock Period) (Default: 0xA) */
1986 
#define SET_tREFI(x)            ((x)&0x3FFF)        /* tREFI (Refresh Interval)[13:0] - Number of clock cycles from one refresh cycle to next refresh cycle. To obtain this value, divide the DDR refresh period (tREF) by total number of rows to be refreshed. Then divide the result by total time. (Default: 0x0411) */
1987 
#endif /* _MISRA_RULES */
1988 
 
1989 
/* Bit masks for EBIU_DDRCTL1 */
1990 
 
1991 
#define                      TRCD  0xf        /* Active-to-Read/write delay */
1992 
#define                       MRD  0xf0       /* Mode register set to active */
1993 
#define                       TWR  0x300      /* Write Recovery time */
1994 
#define               DDRDATWIDTH  0x3000     /* DDR data width */
1995 
#define                  EXTBANKS  0xc000     /* External banks */
1996 
#define               DDRDEVWIDTH  0x30000    /* DDR device width */
1997 
#define                DDRDEVSIZE  0xc0000    /* DDR device size */
1998 
#define                     TWWTR  0xf0000000 /* Write-to-read delay */
1999 
 
2000 
/* Alternate names that match BF54x HRM */
2001 
#define              DDR_DATWIDTH  0x3000     /* DDR data width */
2002 
#define              DDR_DEVWIDTH  0x30000    /* DDR device width */
2003 
#define               DDR_DEVSIZE  0xc0000    /* DDR device size */
2004 
 
2005 
/* Masks for EBIU_DDRCTL1 (DDRDATWIDTH) [in HRM: DDR_DATWIDTH] */
2006 
#define DDR_DATAWIDTH           0x00002000          /* DDR_DATWIDTH Total DDR Data Width (16-bit Only) */
2007 
 
2008 
/* Masks for EBIU_DDRCTL1 (EXTBANKS) */
2009 
#define CS0                     0x00000000          /* EXTBANKS External Banks[15:14] */
2010 
#define CS0_CS1                 0x00004000          /* default */
2011 
 
2012 
/* Masks for EBIU_DDRCTL1 (DDRDEVWIDTH) [in HRM: DDR_DEVWIDTH] */
2013 
#define DDR_DEVWIDTH_4          0x00000000          /* DDR_DRVWIDTH DDR Device Width[17:16] */
2014 
#define DDR_DEVWIDTH_8          0x00010000
2015 
#define DDR_DEVWIDTH_16         0x00020000          /* default */
2016 
 
2017 
/* Masks for EBIU_DDRCTL1 (DDRDEVSIZE) [in HRM: DDR_DEVSIZE] */
2018 
#define DDR_DEVSIZE_512         0x00000000          /* DDR_DEVSIZE DDR Device Size[19:18] */
2019 
#define DDR_DEVSIZE_64          0x00040000
2020 
#define DDR_DEVSIZE_128         0x00080000
2021 
#define DDR_DEVSIZE_256         0x000C0000
2022 
 
2023 
/* Macros for EBIU_DDRCTL1 */
2024 
#ifdef _MISRA_RULES
2025 
#define SET_tWTR(x)             (((x)&0xFu) << 28)   /* tWTR (Write-to-Read Delay)[3:0] - The Write to read delay (last write data to the next read command) as specified by DDR Data sheet (Default: 0x0001) */
2026 
#define SET_tWR(x)              (((x)&0x3u) << 8)    /* tWR Write Recovery Time[9:8] */
2027 
#define SET_tMRD(x)             (((x)&0xFu) << 4)    /* tMRD Mode register set to active[7:4] */
2028 
#define SET_tRCD(x)             ((x)&0xFu)           /* tRCD ACTIVE-to-READ/WRITE delay[3:0] */
2029 
#else
2030 
#define SET_tWTR(x)             (((x)&0xF) << 28)   /* tWTR (Write-to-Read Delay)[3:0] - The Write to read delay (last write data to the next read command) as specified by DDR Data sheet (Default: 0x0001) */
2031 
#define SET_tWR(x)              (((x)&0x3) << 8)    /* tWR Write Recovery Time[9:8] */
2032 
#define SET_tMRD(x)             (((x)&0xF) << 4)    /* tMRD Mode register set to active[7:4] */
2033 
#define SET_tRCD(x)             ((x)&0xF)           /* tRCD ACTIVE-to-READ/WRITE delay[3:0] */
2034 
#endif /* _MISRA_RULES */
2035 
 
2036 
/* Bit masks for EBIU_DDRCTL2 */
2037 
#define               BURSTLENGTH  0x7        /* Burst length */
2038 
#define                CASLATENCY  0x70       /* CAS latency */
2039 
#define                  DLLRESET  0x100      /* DLL Reset */
2040 
#define                 nDLLRESET  0x0
2041 
#define                      REGE  0x1000     /* Register mode enable */
2042 
#define                     nREGE  0x0
2043 
 
2044 
/* Masks for EBIU_DDRCTL2 (BURSTLENGTH) */
2045 
#define BURSTLENGTH1            0x00000001          /* BURSTLENGTH Burst length[2:0] - 001 : Read Only value is set to a burst length of 2 */
2046 
 
2047 
/* Masks for EBIU_DDRCTL2 (CASLATENCY) */
2048 
/* CASLATENCY CAS Latency[6:4] - The number of clock cycles from assertion of read/write signal to SDRAM until first valid data on output from SDRAM. */
2049 
#define CASLATENCY15            0x00000050          /* 101 : 1.5 */
2050 
#define CASLATENCY2             0x00000020          /* 010 : 2 (Default) */
2051 
#define CASLATENCY25            0x00000060          /* 110 : 2.5 */
2052 
#define CASLATENCY3             0x00000030          /* 011 : 3 */
2053 
 
2054 
/* Masks for EBIU_DDRCTL2 (DLLRESET) */
2055 
#define DLL                     0x00000001          /* 0: Enable DLL */
2056 
#define nDLL                    0x0                 /* 0: Disable DLL (Default) */
2057 
#define DS                      0x00000002          /* Defaults to 1 ( Reduced Strength). This is the ONLY value supported */
2058 
#define nDS                     0x0
2059 
 
2060 
/* Bit masks for EBIU_DDRCTL3 */
2061 
#define                      PASR  0x7        /* Partial array self-refresh */
2062 
 
2063 
/* Bit masks for EBIU_DDRQUE */
2064 
#define                DEB0_PFLEN  0x3        /* Pre fetch length for DEB0 accesses */
2065 
#define                DEB1_PFLEN  0xc        /* Pre fetch length for DEB1 accesses */
2066 
#define                DEB2_PFLEN  0x30       /* Pre fetch length for DEB2 accesses */
2067 
#define          DEB_ARB_PRIORITY  0x700      /* Arbitration between DEB busses */
2068 
#define               DEB0_URGENT  0x1000     /* DEB0 Urgent */
2069 
#define              nDEB0_URGENT  0x0
2070 
#define               DEB1_URGENT  0x2000     /* DEB1 Urgent */
2071 
#define              nDEB1_URGENT  0x0
2072 
#define               DEB2_URGENT  0x4000     /* DEB2 Urgent */
2073 
#define              nDEB2_URGENT  0x0
2074 
 
2075 
/* Bit masks for EBIU_DDRQUE (DEB0_PFLEN) */
2076 
/* DEB0_PFLEN[1:0] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
2077 
#define DEB0_PFLEN0             0x00000000          /* 00 - (Single Access) */
2078 
#define DEB0_PFLEN4             0x00000001          /* 01 - 4 Half-words (Default) */
2079 
#define DEB0_PFLEN8             0x00000002          /* 10 - 8 Half-words */
2080 
#define DEB0_PFLEN16            0x00000003          /* 11 - 16Half-words */
2081 
/* performs, 16 bit read to DDR controller. Second edge is not used. */
2082 
 
2083 
/* Bit masks for EBIU_DDRQUE (DEB1_PFLEN) */
2084 
/* DEB1_PFLEN[3:2] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
2085 
#define DEB1_PFLEN0             0x00000000          /* 00 - (Single Access) */
2086 
#define DEB1_PFLEN4             0x00000004          /* 01 - 4 Half-words (Default) */
2087 
#define DEB1_PFLEN8             0x00000008          /* 10 - 8 Half-words */
2088 
#define DEB1_PFLEN16            0x0000000C          /* 11 - 16Half-words */
2089 
/* performs, 16 bit read to DDR controller. Second edge is not used. */
2090 
 
2091 
/* Bit masks for EBIU_DDRQUE (DEB2_PFLEN) */
2092 
/* DEB2_PFLEN[5:4] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
2093 
#define DEB2_PFLEN0             0x00000000          /* 00 - (Single Access) */
2094 
#define DEB2_PFLEN4             0x00000010          /* 01 - 4 Half-words (Default) */
2095 
#define DEB2_PFLEN8             0x00000020          /* 10 - 8 Half-words */
2096 
#define DEB2_PFLEN16            0x00000030          /* 11 - 16Half-words */
2097 
/* performs, 16 bit read to DDR controller. Second edge is not used. */
2098 
 
2099 
/* Bit masks for EBIU_DDRQUE (DEB_ARB_PRIORITY) */
2100 
/* DEB_ARB_PRIORITY[10:8] - Arbitration Priority between all DEB buses for External DDR Memory: */
2101 
#define DEB_ARB_PRIORITY0       0x00000000          /* 000 : DEB0>DEB1>DEB2 */
2102 
#define DEB_ARB_PRIORITY1       0x00000100          /* 001 : DEB1>DEB0>DEB2 (Default) */
2103 
#define DEB_ARB_PRIORITY2       0x00000200          /* 010 : DEB2>DEB0>DEB1 */
2104 
/* In addition the following fixed order of arbitration is maintained:
2105 
1. Core Lock Access
2106 
2. Urgent DMA Access
2107 
3. Core Access
2108 
4. Normal DMA Access
2109 
5. Prefetch Reads */
2110 
 
2111 
/* Bit masks for EBIU_ERRMST */
2112 
 
2113 
#define                DEB1_ERROR  0x1        /* DEB1 Error */
2114 
#define               nDEB1_ERROR  0x0
2115 
#define                DEB2_ERROR  0x2        /* DEB2 Error */
2116 
#define               nDEB2_ERROR  0x0
2117 
#define                DEB3_ERROR  0x4        /* DEB3 Error */
2118 
#define               nDEB3_ERROR  0x0
2119 
#define                CORE_ERROR  0x8        /* Core error */
2120 
#define               nCORE_ERROR  0x0
2121 
#define                DEB_MERROR  0x10       /* DEB1 Error (2nd) */
2122 
#define               nDEB_MERROR  0x0
2123 
#define               DEB2_MERROR  0x20       /* DEB2 Error (2nd) */
2124 
#define              nDEB2_MERROR  0x0
2125 
#define               DEB3_MERROR  0x40       /* DEB3 Error (2nd) */
2126 
#define              nDEB3_MERROR  0x0
2127 
#define               CORE_MERROR  0x80       /* Core Error (2nd) */
2128 
#define              nCORE_MERROR  0x0
2129 
 
2130 
/* Bit masks for EBIU_ERRADD */
2131 
 
2132 
#define             ERROR_ADDRESS  0xffffffff /* Error Address */
2133 
 
2134 
/* Bit masks for EBIU_RSTCTL */
2135 
 
2136 
#define                 DDRSRESET  0x1        /* DDR soft reset */
2137 
#define                nDDRSRESET  0x0
2138 
#define               PFTCHSRESET  0x4        /* DDR prefetch reset */
2139 
#define              nPFTCHSRESET  0x0
2140 
#define                     SRREQ  0x8        /* Self-refresh request */
2141 
#define                    nSRREQ  0x0
2142 
#define                     SRACK  0x10       /* Self-refresh acknowledge */
2143 
#define                    nSRACK  0x0
2144 
 
2145 
/* Bit masks for EBIU_DDRBRC0 */
2146 
 
2147 
#define                      BRC0  0xffffffff /* Count */
2148 
 
2149 
/* Bit masks for EBIU_DDRBRC1 */
2150 
 
2151 
#define                      BRC1  0xffffffff /* Count */
2152 
 
2153 
/* Bit masks for EBIU_DDRBRC2 */
2154 
 
2155 
#define                      BRC2  0xffffffff /* Count */
2156 
 
2157 
/* Bit masks for EBIU_DDRBRC3 */
2158 
 
2159 
#define                      BRC3  0xffffffff /* Count */
2160 
 
2161 
/* Bit masks for EBIU_DDRBRC4 */
2162 
 
2163 
#define                      BRC4  0xffffffff /* Count */
2164 
 
2165 
/* Bit masks for EBIU_DDRBRC5 */
2166 
 
2167 
#define                      BRC5  0xffffffff /* Count */
2168 
 
2169 
/* Bit masks for EBIU_DDRBRC6 */
2170 
 
2171 
#define                      BRC6  0xffffffff /* Count */
2172 
 
2173 
/* Bit masks for EBIU_DDRBRC7 */
2174 
 
2175 
#define                      BRC7  0xffffffff /* Count */
2176 
 
2177 
/* Bit masks for EBIU_DDRBWC0 */
2178 
 
2179 
#define                      BWC0  0xffffffff /* Count */
2180 
 
2181 
/* Bit masks for EBIU_DDRBWC1 */
2182 
 
2183 
#define                      BWC1  0xffffffff /* Count */
2184 
 
2185 
/* Bit masks for EBIU_DDRBWC2 */
2186 
 
2187 
#define                      BWC2  0xffffffff /* Count */
2188 
 
2189 
/* Bit masks for EBIU_DDRBWC3 */
2190 
 
2191 
#define                      BWC3  0xffffffff /* Count */
2192 
 
2193 
/* Bit masks for EBIU_DDRBWC4 */
2194 
 
2195 
#define                      BWC4  0xffffffff /* Count */
2196 
 
2197 
/* Bit masks for EBIU_DDRBWC5 */
2198 
 
2199 
#define                      BWC5  0xffffffff /* Count */
2200 
 
2201 
/* Bit masks for EBIU_DDRBWC6 */
2202 
 
2203 
#define                      BWC6  0xffffffff /* Count */
2204 
 
2205 
/* Bit masks for EBIU_DDRBWC7 */
2206 
 
2207 
#define                      BWC7  0xffffffff /* Count */
2208 
 
2209 
/* Bit masks for EBIU_DDRACCT */
2210 
 
2211 
#define                      ACCT  0xffffffff /* Count */
2212 
 
2213 
/* Bit masks for EBIU_DDRTACT */
2214 
 
2215 
#define                      TECT  0xffffffff /* Count */
2216 
 
2217 
/* Bit masks for EBIU_DDRARCT */
2218 
 
2219 
#define                      ARCT  0xffffffff /* Count */
2220 
 
2221 
/* Bit masks for EBIU_DDRGC0 */
2222 
 
2223 
#define                       GC0  0xffffffff /* Count */
2224 
 
2225 
/* Bit masks for EBIU_DDRGC1 */
2226 
 
2227 
#define                       GC1  0xffffffff /* Count */
2228 
 
2229 
/* Bit masks for EBIU_DDRGC2 */
2230 
 
2231 
#define                       GC2  0xffffffff /* Count */
2232 
 
2233 
/* Bit masks for EBIU_DDRGC3 */
2234 
 
2235 
#define                       GC3  0xffffffff /* Count */
2236 
 
2237 
/* Bit masks for EBIU_DDRMCEN */
2238 
 
2239 
#define                B0WCENABLE  0x1        /* Bank 0 write count enable */
2240 
#define               nB0WCENABLE  0x0
2241 
#define                B1WCENABLE  0x2        /* Bank 1 write count enable */
2242 
#define               nB1WCENABLE  0x0
2243 
#define                B2WCENABLE  0x4        /* Bank 2 write count enable */
2244 
#define               nB2WCENABLE  0x0
2245 
#define                B3WCENABLE  0x8        /* Bank 3 write count enable */
2246 
#define               nB3WCENABLE  0x0
2247 
#define                B4WCENABLE  0x10       /* Bank 4 write count enable */
2248 
#define               nB4WCENABLE  0x0
2249 
#define                B5WCENABLE  0x20       /* Bank 5 write count enable */
2250 
#define               nB5WCENABLE  0x0
2251 
#define                B6WCENABLE  0x40       /* Bank 6 write count enable */
2252 
#define               nB6WCENABLE  0x0
2253 
#define                B7WCENABLE  0x80       /* Bank 7 write count enable */
2254 
#define               nB7WCENABLE  0x0
2255 
#define                B0RCENABLE  0x100      /* Bank 0 read count enable */
2256 
#define               nB0RCENABLE  0x0
2257 
#define                B1RCENABLE  0x200      /* Bank 1 read count enable */
2258 
#define               nB1RCENABLE  0x0
2259 
#define                B2RCENABLE  0x400      /* Bank 2 read count enable */
2260 
#define               nB2RCENABLE  0x0
2261 
#define                B3RCENABLE  0x800      /* Bank 3 read count enable */
2262 
#define               nB3RCENABLE  0x0
2263 
#define                B4RCENABLE  0x1000     /* Bank 4 read count enable */
2264 
#define               nB4RCENABLE  0x0
2265 
#define                B5RCENABLE  0x2000     /* Bank 5 read count enable */
2266 
#define               nB5RCENABLE  0x0
2267 
#define                B6RCENABLE  0x4000     /* Bank 6 read count enable */
2268 
#define               nB6RCENABLE  0x0
2269 
#define                B7RCENABLE  0x8000     /* Bank 7 read count enable */
2270 
#define               nB7RCENABLE  0x0
2271 
#define             ROWACTCENABLE  0x10000    /* DDR Row activate count enable */
2272 
#define            nROWACTCENABLE  0x0
2273 
#define                RWTCENABLE  0x20000    /* DDR R/W Turn around count enable */
2274 
#define               nRWTCENABLE  0x0
2275 
#define                 ARCENABLE  0x40000    /* DDR Auto-refresh count enable */
2276 
#define                nARCENABLE  0x0
2277 
#define                 GC0ENABLE  0x100000   /* DDR Grant count 0 enable */
2278 
#define                nGC0ENABLE  0x0
2279 
#define                 GC1ENABLE  0x200000   /* DDR Grant count 1 enable */
2280 
#define                nGC1ENABLE  0x0
2281 
#define                 GC2ENABLE  0x400000   /* DDR Grant count 2 enable */
2282 
#define                nGC2ENABLE  0x0
2283 
#define                 GC3ENABLE  0x800000   /* DDR Grant count 3 enable */
2284 
#define                nGC3ENABLE  0x0
2285 
#define                 GCCONTROL  0x3000000  /* DDR Grant Count Control */
2286 
 
2287 
/* Bit masks for EBIU_DDRMCCL */
2288 
 
2289 
#define                 CB0WCOUNT  0x1        /* Clear write count 0 */
2290 
#define                nCB0WCOUNT  0x0
2291 
#define                 CB1WCOUNT  0x2        /* Clear write count 1 */
2292 
#define                nCB1WCOUNT  0x0
2293 
#define                 CB2WCOUNT  0x4        /* Clear write count 2 */
2294 
#define                nCB2WCOUNT  0x0
2295 
#define                 CB3WCOUNT  0x8        /* Clear write count 3 */
2296 
#define                nCB3WCOUNT  0x0
2297 
#define                 CB4WCOUNT  0x10       /* Clear write count 4 */
2298 
#define                nCB4WCOUNT  0x0
2299 
#define                 CB5WCOUNT  0x20       /* Clear write count 5 */
2300 
#define                nCB5WCOUNT  0x0
2301 
#define                 CB6WCOUNT  0x40       /* Clear write count 6 */
2302 
#define                nCB6WCOUNT  0x0
2303 
#define                 CB7WCOUNT  0x80       /* Clear write count 7 */
2304 
#define                nCB7WCOUNT  0x0
2305 
#define                  CBRCOUNT  0x100      /* Clear read count 0 */
2306 
#define                 nCBRCOUNT  0x0
2307 
#define                 CB1RCOUNT  0x200      /* Clear read count 1 */
2308 
#define                nCB1RCOUNT  0x0
2309 
#define                 CB2RCOUNT  0x400      /* Clear read count 2 */
2310 
#define                nCB2RCOUNT  0x0
2311 
#define                 CB3RCOUNT  0x800      /* Clear read count 3 */
2312 
#define                nCB3RCOUNT  0x0
2313 
#define                 CB4RCOUNT  0x1000     /* Clear read count 4 */
2314 
#define                nCB4RCOUNT  0x0
2315 
#define                 CB5RCOUNT  0x2000     /* Clear read count 5 */
2316 
#define                nCB5RCOUNT  0x0
2317 
#define                 CB6RCOUNT  0x4000     /* Clear read count 6 */
2318 
#define                nCB6RCOUNT  0x0
2319 
#define                 CB7RCOUNT  0x8000     /* Clear read count 7 */
2320 
#define                nCB7RCOUNT  0x0
2321 
#define                  CRACOUNT  0x10000    /* Clear row activation count */
2322 
#define                 nCRACOUNT  0x0
2323 
#define                CRWTACOUNT  0x20000    /* Clear R/W turn-around count */
2324 
#define               nCRWTACOUNT  0x0
2325 
#define                  CARCOUNT  0x40000    /* Clear auto-refresh count */
2326 
#define                 nCARCOUNT  0x0
2327 
#define                  CG0COUNT  0x100000   /* Clear grant count 0 */
2328 
#define                 nCG0COUNT  0x0
2329 
#define                  CG1COUNT  0x200000   /* Clear grant count 1 */
2330 
#define                 nCG1COUNT  0x0
2331 
#define                  CG2COUNT  0x400000   /* Clear grant count 2 */
2332 
#define                 nCG2COUNT  0x0
2333 
#define                  CG3COUNT  0x800000   /* Clear grant count 3 */
2334 
#define                 nCG3COUNT  0x0
2335 
 
2336 
/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
2337 
 
2338 
#define                       Px0  0x1        /* GPIO 0 */
2339 
#define                      nPx0  0x0
2340 
#define                       Px1  0x2        /* GPIO 1 */
2341 
#define                      nPx1  0x0
2342 
#define                       Px2  0x4        /* GPIO 2 */
2343 
#define                      nPx2  0x0
2344 
#define                       Px3  0x8        /* GPIO 3 */
2345 
#define                      nPx3  0x0
2346 
#define                       Px4  0x10       /* GPIO 4 */
2347 
#define                      nPx4  0x0
2348 
#define                       Px5  0x20       /* GPIO 5 */
2349 
#define                      nPx5  0x0
2350 
#define                       Px6  0x40       /* GPIO 6 */
2351 
#define                      nPx6  0x0
2352 
#define                       Px7  0x80       /* GPIO 7 */
2353 
#define                      nPx7  0x0
2354 
#define                       Px8  0x100      /* GPIO 8 */
2355 
#define                      nPx8  0x0
2356 
#define                       Px9  0x200      /* GPIO 9 */
2357 
#define                      nPx9  0x0
2358 
#define                      Px10  0x400      /* GPIO 10 */
2359 
#define                     nPx10  0x0
2360 
#define                      Px11  0x800      /* GPIO 11 */
2361 
#define                     nPx11  0x0
2362 
#define                      Px12  0x1000     /* GPIO 12 */
2363 
#define                     nPx12  0x0
2364 
#define                      Px13  0x2000     /* GPIO 13 */
2365 
#define                     nPx13  0x0
2366 
#define                      Px14  0x4000     /* GPIO 14 */
2367 
#define                     nPx14  0x0
2368 
#define                      Px15  0x8000     /* GPIO 15 */
2369 
#define                     nPx15  0x0
2370 
 
2371 
/* Bit masks for PORTA_MUX - PORTJ_MUX */
2372 
 
2373 
#define                      PxM0  0x3        /* GPIO Mux 0 */
2374 
#define                      PxM1  0xc        /* GPIO Mux 1 */
2375 
#define                      PxM2  0x30       /* GPIO Mux 2 */
2376 
#define                      PxM3  0xc0       /* GPIO Mux 3 */
2377 
#define                      PxM4  0x300      /* GPIO Mux 4 */
2378 
#define                      PxM5  0xc00      /* GPIO Mux 5 */
2379 
#define                      PxM6  0x3000     /* GPIO Mux 6 */
2380 
#define                      PxM7  0xc000     /* GPIO Mux 7 */
2381 
#define                      PxM8  0x30000    /* GPIO Mux 8 */
2382 
#define                      PxM9  0xc0000    /* GPIO Mux 9 */
2383 
#define                     PxM10  0x300000   /* GPIO Mux 10 */
2384 
#define                     PxM11  0xc00000   /* GPIO Mux 11 */
2385 
#define                     PxM12  0x3000000  /* GPIO Mux 12 */
2386 
#define                     PxM13  0xc000000  /* GPIO Mux 13 */
2387 
#define                     PxM14  0x30000000 /* GPIO Mux 14 */
2388 
#define                     PxM15  0xc0000000 /* GPIO Mux 15 */
2389 
 
2390 
 
2391 
/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
2392 
 
2393 
#define                       IB0  0x1        /* Interrupt Bit 0 */
2394 
#define                      nIB0  0x0
2395 
#define                       IB1  0x2        /* Interrupt Bit 1 */
2396 
#define                      nIB1  0x0
2397 
#define                       IB2  0x4        /* Interrupt Bit 2 */
2398 
#define                      nIB2  0x0
2399 
#define                       IB3  0x8        /* Interrupt Bit 3 */
2400 
#define                      nIB3  0x0
2401 
#define                       IB4  0x10       /* Interrupt Bit 4 */
2402 
#define                      nIB4  0x0
2403 
#define                       IB5  0x20       /* Interrupt Bit 5 */
2404 
#define                      nIB5  0x0
2405 
#define                       IB6  0x40       /* Interrupt Bit 6 */
2406 
#define                      nIB6  0x0
2407 
#define                       IB7  0x80       /* Interrupt Bit 7 */
2408 
#define                      nIB7  0x0
2409 
#define                       IB8  0x100      /* Interrupt Bit 8 */
2410 
#define                      nIB8  0x0
2411 
#define                       IB9  0x200      /* Interrupt Bit 9 */
2412 
#define                      nIB9  0x0
2413 
#define                      IB10  0x400      /* Interrupt Bit 10 */
2414 
#define                     nIB10  0x0
2415 
#define                      IB11  0x800      /* Interrupt Bit 11 */
2416 
#define                     nIB11  0x0
2417 
#define                      IB12  0x1000     /* Interrupt Bit 12 */
2418 
#define                     nIB12  0x0
2419 
#define                      IB13  0x2000     /* Interrupt Bit 13 */
2420 
#define                     nIB13  0x0
2421 
#define                      IB14  0x4000     /* Interrupt Bit 14 */
2422 
#define                     nIB14  0x0
2423 
#define                      IB15  0x8000     /* Interrupt Bit 15 */
2424 
#define                     nIB15  0x0
2425 
 
2426 
/* Bit masks for TIMERx_CONFIG */
2427 
 
2428 
#define                     TMODE  0x3        /* Timer Mode */
2429 
#define                  PULSE_HI  0x4        /* Pulse Polarity */
2430 
#define                 nPULSE_HI  0x0
2431 
#define                PERIOD_CNT  0x8        /* Period Count */
2432 
#define               nPERIOD_CNT  0x0
2433 
#define                   IRQ_ENA  0x10       /* Interrupt Request Enable */
2434 
#define                  nIRQ_ENA  0x0
2435 
#define                   TIN_SEL  0x20       /* Timer Input Select */
2436 
#define                  nTIN_SEL  0x0
2437 
#define                   OUT_DIS  0x40       /* Output Pad Disable */
2438 
#define                  nOUT_DIS  0x0
2439 
#define                   CLK_SEL  0x80       /* Timer Clock Select */
2440 
#define                  nCLK_SEL  0x0
2441 
#define                 TOGGLE_HI  0x100      /* Toggle Mode */
2442 
#define                nTOGGLE_HI  0x0
2443 
#define                   EMU_RUN  0x200      /* Emulation Behavior Select */
2444 
#define                  nEMU_RUN  0x0
2445 
#define                   ERR_TYP  0xc000     /* Error Type */
2446 
 
2447 
/* Bit masks for TIMER_ENABLE0 */
2448 
 
2449 
#define                    TIMEN0  0x1        /* Timer 0 Enable */
2450 
#define                   nTIMEN0  0x0
2451 
#define                    TIMEN1  0x2        /* Timer 1 Enable */
2452 
#define                   nTIMEN1  0x0
2453 
#define                    TIMEN2  0x4        /* Timer 2 Enable */
2454 
#define                   nTIMEN2  0x0
2455 
#define                    TIMEN3  0x8        /* Timer 3 Enable */
2456 
#define                   nTIMEN3  0x0
2457 
#define                    TIMEN4  0x10       /* Timer 4 Enable */
2458 
#define                   nTIMEN4  0x0
2459 
#define                    TIMEN5  0x20       /* Timer 5 Enable */
2460 
#define                   nTIMEN5  0x0
2461 
#define                    TIMEN6  0x40       /* Timer 6 Enable */
2462 
#define                   nTIMEN6  0x0
2463 
#define                    TIMEN7  0x80       /* Timer 7 Enable */
2464 
#define                   nTIMEN7  0x0
2465 
 
2466 
/* Bit masks for TIMER_DISABLE0 */
2467 
 
2468 
#define                   TIMDIS0  0x1        /* Timer 0 Disable */
2469 
#define                  nTIMDIS0  0x0
2470 
#define                   TIMDIS1  0x2        /* Timer 1 Disable */
2471 
#define                  nTIMDIS1  0x0
2472 
#define                   TIMDIS2  0x4        /* Timer 2 Disable */
2473 
#define                  nTIMDIS2  0x0
2474 
#define                   TIMDIS3  0x8        /* Timer 3 Disable */
2475 
#define                  nTIMDIS3  0x0
2476 
#define                   TIMDIS4  0x10       /* Timer 4 Disable */
2477 
#define                  nTIMDIS4  0x0
2478 
#define                   TIMDIS5  0x20       /* Timer 5 Disable */
2479 
#define                  nTIMDIS5  0x0
2480 
#define                   TIMDIS6  0x40       /* Timer 6 Disable */
2481 
#define                  nTIMDIS6  0x0
2482 
#define                   TIMDIS7  0x80       /* Timer 7 Disable */
2483 
#define                  nTIMDIS7  0x0
2484 
 
2485 
/* Bit masks for TIMER_STATUS0 */
2486 
 
2487 
#define                    TIMIL0  0x1        /* Timer 0 Interrupt */
2488 
#define                   nTIMIL0  0x0
2489 
#define                    TIMIL1  0x2        /* Timer 1 Interrupt */
2490 
#define                   nTIMIL1  0x0
2491 
#define                    TIMIL2  0x4        /* Timer 2 Interrupt */
2492 
#define                   nTIMIL2  0x0
2493 
#define                    TIMIL3  0x8        /* Timer 3 Interrupt */
2494 
#define                   nTIMIL3  0x0
2495 
#define                 TOVF_ERR0  0x10       /* Timer 0 Counter Overflow */
2496 
#define                nTOVF_ERR0  0x0
2497 
#define                 TOVF_ERR1  0x20       /* Timer 1 Counter Overflow */
2498 
#define                nTOVF_ERR1  0x0
2499 
#define                 TOVF_ERR2  0x40       /* Timer 2 Counter Overflow */
2500 
#define                nTOVF_ERR2  0x0
2501 
#define                 TOVF_ERR3  0x80       /* Timer 3 Counter Overflow */
2502 
#define                nTOVF_ERR3  0x0
2503 
#define                     TRUN0  0x1000     /* Timer 0 Slave Enable Status */
2504 
#define                    nTRUN0  0x0
2505 
#define                     TRUN1  0x2000     /* Timer 1 Slave Enable Status */
2506 
#define                    nTRUN1  0x0
2507 
#define                     TRUN2  0x4000     /* Timer 2 Slave Enable Status */
2508 
#define                    nTRUN2  0x0
2509 
#define                     TRUN3  0x8000     /* Timer 3 Slave Enable Status */
2510 
#define                    nTRUN3  0x0
2511 
#define                    TIMIL4  0x10000    /* Timer 4 Interrupt */
2512 
#define                   nTIMIL4  0x0
2513 
#define                    TIMIL5  0x20000    /* Timer 5 Interrupt */
2514 
#define                   nTIMIL5  0x0
2515 
#define                    TIMIL6  0x40000    /* Timer 6 Interrupt */
2516 
#define                   nTIMIL6  0x0
2517 
#define                    TIMIL7  0x80000    /* Timer 7 Interrupt */
2518 
#define                   nTIMIL7  0x0
2519 
#define                 TOVF_ERR4  0x100000   /* Timer 4 Counter Overflow */
2520 
#define                nTOVF_ERR4  0x0
2521 
#define                 TOVF_ERR5  0x200000   /* Timer 5 Counter Overflow */
2522 
#define                nTOVF_ERR5  0x0
2523 
#define                 TOVF_ERR6  0x400000   /* Timer 6 Counter Overflow */
2524 
#define                nTOVF_ERR6  0x0
2525 
#define                 TOVF_ERR7  0x800000   /* Timer 7 Counter Overflow */
2526 
#define                nTOVF_ERR7  0x0
2527 
#define                     TRUN4  0x10000000 /* Timer 4 Slave Enable Status */
2528 
#define                    nTRUN4  0x0
2529 
#define                     TRUN5  0x20000000 /* Timer 5 Slave Enable Status */
2530 
#define                    nTRUN5  0x0
2531 
#define                     TRUN6  0x40000000 /* Timer 6 Slave Enable Status */
2532 
#define                    nTRUN6  0x0
2533 
#define                     TRUN7  0x80000000 /* Timer 7 Slave Enable Status */
2534 
#define                    nTRUN7  0x0
2535 
 
2536 
/* Bit masks for WDOG_CTL */
2537 
 
2538 
#define                      WDEV  0x6        /* Watchdog Event */
2539 
#define                      WDEN  0xff0      /* Watchdog Enable */
2540 
#define                      WDRO  0x8000     /* Watchdog Rolled Over */
2541 
#define                     nWDRO  0x0
2542 
 
2543 
/* Bit masks for CNT_CONFIG */
2544 
 
2545 
#define                      CNTE  0x1        /* Counter Enable */
2546 
#define                     nCNTE  0x0
2547 
#define                      DEBE  0x2        /* Debounce Enable */
2548 
#define                     nDEBE  0x0
2549 
#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
2550 
#define                   nCDGINV  0x0
2551 
#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
2552 
#define                   nCUDINV  0x0
2553 
#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
2554 
#define                   nCZMINV  0x0
2555 
#define                   CNTMODE  0x700      /* Counter Operating Mode */
2556 
#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
2557 
#define                     nZMZC  0x0
2558 
#define                   BNDMODE  0x3000     /* Boundary register Mode */
2559 
#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
2560 
#define                   nINPDIS  0x0
2561 
 
2562 
/* Bit masks for CNT_IMASK */
2563 
 
2564 
#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
2565 
#define                     nICIE  0x0
2566 
#define                      UCIE  0x2        /* Up count Interrupt Enable */
2567 
#define                     nUCIE  0x0
2568 
#define                      DCIE  0x4        /* Down count Interrupt Enable */
2569 
#define                     nDCIE  0x0
2570 
#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
2571 
#define                   nMINCIE  0x0
2572 
#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
2573 
#define                   nMAXCIE  0x0
2574 
#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
2575 
#define                  nCOV31IE  0x0
2576 
#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
2577 
#define                  nCOV15IE  0x0
2578 
#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
2579 
#define                  nCZEROIE  0x0
2580 
#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
2581 
#define                    nCZMIE  0x0
2582 
#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
2583 
#define                   nCZMEIE  0x0
2584 
#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
2585 
#define                   nCZMZIE  0x0
2586 
 
2587 
/* Bit masks for CNT_STATUS */
2588 
 
2589 
#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
2590 
#define                     nICII  0x0
2591 
#define                      UCII  0x2        /* Up count Interrupt Identifier */
2592 
#define                     nUCII  0x0
2593 
#define                      DCII  0x4        /* Down count Interrupt Identifier */
2594 
#define                     nDCII  0x0
2595 
#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
2596 
#define                   nMINCII  0x0
2597 
#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
2598 
#define                   nMAXCII  0x0
2599 
#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
2600 
#define                  nCOV31II  0x0
2601 
#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
2602 
#define                  nCOV15II  0x0
2603 
#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
2604 
#define                  nCZEROII  0x0
2605 
#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
2606 
#define                    nCZMII  0x0
2607 
#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
2608 
#define                   nCZMEII  0x0
2609 
#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
2610 
#define                   nCZMZII  0x0
2611 
 
2612 
/* Bit masks for CNT_COMMAND */
2613 
 
2614 
#define                    W1LCNT  0xf        /* Load Counter Register */
2615 
#define                    W1LMIN  0xf0       /* Load Min Register */
2616 
#define                    W1LMAX  0xf00      /* Load Max Register */
2617 
#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
2618 
#define                 nW1ZMONCE  0x0
2619 
 
2620 
/* Bit masks for CNT_DEBOUNCE */
2621 
 
2622 
#define                 DPRESCALE  0xf        /* Load Counter Register */
2623 
 
2624 
/* Bit masks for RTC_STAT */
2625 
 
2626 
#define                   SECONDS  0x3f       /* Seconds */
2627 
#define                   MINUTES  0xfc0      /* Minutes */
2628 
#define                     HOURS  0x1f000    /* Hours */
2629 
#define               DAY_COUNTER  0xfffe0000 /* Day Counter */
2630 
 
2631 
/* Bit masks for RTC_ICTL */
2632 
 
2633 
#define STOPWATCH_INTERRUPT_ENABLE  0x1        /* Stopwatch Interrupt Enable */
2634 
#define nSTOPWATCH_INTERRUPT_ENABLE  0x0
2635 
#define    ALARM_INTERRUPT_ENABLE  0x2        /* Alarm Interrupt Enable */
2636 
#define   nALARM_INTERRUPT_ENABLE  0x0
2637 
#define  SECONDS_INTERRUPT_ENABLE  0x4        /* Seconds Interrupt Enable */
2638 
#define nSECONDS_INTERRUPT_ENABLE  0x0
2639 
#define  MINUTES_INTERRUPT_ENABLE  0x8        /* Minutes Interrupt Enable */
2640 
#define nMINUTES_INTERRUPT_ENABLE  0x0
2641 
#define    HOURS_INTERRUPT_ENABLE  0x10       /* Hours Interrupt Enable */
2642 
#define   nHOURS_INTERRUPT_ENABLE  0x0
2643 
#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x20       /* 24 Hours Interrupt Enable */
2644 
#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x0
2645 
#define DAY_ALARM_INTERRUPT_ENABLE  0x40       /* Day Alarm Interrupt Enable */
2646 
#define nDAY_ALARM_INTERRUPT_ENABLE  0x0
2647 
#define WRITE_COMPLETE_INTERRUPT_ENABLE  0x8000     /* Write Complete Interrupt Enable */
2648 
#define nWRITE_COMPLETE_INTERRUPT_ENABLE  0x0
2649 
 
2650 
/* Bit masks for RTC_ISTAT */
2651 
 
2652 
#define      STOPWATCH_EVENT_FLAG  0x1        /* Stopwatch Event Flag */
2653 
#define     nSTOPWATCH_EVENT_FLAG  0x0
2654 
#define          ALARM_EVENT_FLAG  0x2        /* Alarm Event Flag */
2655 
#define         nALARM_EVENT_FLAG  0x0
2656 
#define        SECONDS_EVENT_FLAG  0x4        /* Seconds Event Flag */
2657 
#define       nSECONDS_EVENT_FLAG  0x0
2658 
#define        MINUTES_EVENT_FLAG  0x8        /* Minutes Event Flag */
2659 
#define       nMINUTES_EVENT_FLAG  0x0
2660 
#define          HOURS_EVENT_FLAG  0x10       /* Hours Event Flag */
2661 
#define         nHOURS_EVENT_FLAG  0x0
2662 
#define TWENTY_FOUR_HOURS_EVENT_FLAG  0x20       /* 24 Hours Event Flag */
2663 
#define nTWENTY_FOUR_HOURS_EVENT_FLAG  0x0
2664 
#define      DAY_ALARM_EVENT_FLAG  0x40       /* Day Alarm Event Flag */
2665 
#define     nDAY_ALARM_EVENT_FLAG  0x0
2666 
#define     WRITE_PENDING_STATUS  0x4000     /* Write Pending Status */
2667 
#define    nWRITE_PENDING_STATUS  0x0
2668 
#define            WRITE_COMPLETE  0x8000     /* Write Complete */
2669 
#define           nWRITE_COMPLETE  0x0
2670 
 
2671 
/* Bit masks for RTC_SWCNT */
2672 
 
2673 
#define           STOPWATCH_COUNT  0xffff     /* Stopwatch Count */
2674 
 
2675 
/* Bit masks for RTC_ALARM */
2676 
 
2677 
#define                   SECONDS  0x3f       /* Seconds */
2678 
#define                   MINUTES  0xfc0      /* Minutes */
2679 
#define                     HOURS  0x1f000    /* Hours */
2680 
#define                       DAY  0xfffe0000 /* Day */
2681 
 
2682 
/* Bit masks for RTC_PREN */
2683 
 
2684 
#define                      PREN  0x1        /* Prescaler Enable */
2685 
#define                     nPREN  0x0
2686 
 
2687 
/* Bit masks for SECURE_SYSSWT */
2688 
 
2689 
#define                   EMUDABL  0x1        /* Emulation Disable. */
2690 
#define                  nEMUDABL  0x0
2691 
#define                   RSTDABL  0x2        /* Reset Disable */
2692 
#define                  nRSTDABL  0x0
2693 
#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
2694 
#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
2695 
#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
2696 
#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
2697 
#define                  nDMA0OVR  0x0
2698 
#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
2699 
#define                  nDMA1OVR  0x0
2700 
#define                    EMUOVR  0x4000     /* Emulation Override */
2701 
#define                   nEMUOVR  0x0
2702 
#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
2703 
#define                   nOTPSEN  0x0
2704 
#define                    L2DABL  0x70000    /* L2 Memory Disable. */
2705 
 
2706 
/* Bit masks for SECURE_CONTROL */
2707 
 
2708 
#define                   SECURE0  0x1        /* SECURE 0 */
2709 
#define                  nSECURE0  0x0
2710 
#define                   SECURE1  0x2        /* SECURE 1 */
2711 
#define                  nSECURE1  0x0
2712 
#define                   SECURE2  0x4        /* SECURE 2 */
2713 
#define                  nSECURE2  0x0
2714 
#define                   SECURE3  0x8        /* SECURE 3 */
2715 
#define                  nSECURE3  0x0
2716 
 
2717 
/* Bit masks for SECURE_STATUS */
2718 
 
2719 
#define                   SECMODE  0x3        /* Secured Mode Control State */
2720 
#define                       NMI  0x4        /* Non Maskable Interrupt */
2721 
#define                      nNMI  0x0
2722 
#define                   AFVALID  0x8        /* Authentication Firmware Valid */
2723 
#define                  nAFVALID  0x0
2724 
#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
2725 
#define                   nAFEXIT  0x0
2726 
#define                   SECSTAT  0xe0       /* Secure Status */
2727 
 
2728 
/* Bit masks for PLL_DIV */
2729 
 
2730 
#define                      CSEL  0x30       /* Core Select */
2731 
#define                      SSEL  0xf        /* System Select */
2732 
 
2733 
/* PLL_DIV Masks (CSEL) */
2734 
#define CSEL_DIV1               0x0000              /* CCLK = VCO / 1 */
2735 
#define CSEL_DIV2               0x0010              /* CCLK = VCO / 2 */
2736 
#define CSEL_DIV4               0x0020              /* CCLK = VCO / 4 */
2737 
#define CSEL_DIV8               0x0030              /* CCLK = VCO / 8 */
2738 
 
2739 
/* PLL_DIV Macros */
2740 
#ifdef _MISRA_RULES
2741 
#define SET_SSEL(x)             ((x)&0xFu)           /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
2742 
#else
2743 
#define SET_SSEL(x)             ((x)&0xF)           /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
2744 
#endif /* _MISRA_RULES */
2745 
 
2746 
/* Bit masks for PLL_CTL */
2747 
 
2748 
#define                      MSEL  0x7e00     /* Multiplier Select */
2749 
#define                    BYPASS  0x100      /* PLL Bypass Enable */
2750 
#define                   nBYPASS  0x0
2751 
#define              OUTPUT_DELAY  0x80       /* External Memory Output Delay Enable */
2752 
#define             nOUTPUT_DELAY  0x0
2753 
#define               INPUT_DELAY  0x40       /* External Memory Input Delay Enable */
2754 
#define              nINPUT_DELAY  0x0
2755 
#define                      PDWN  0x20       /* Power Down */
2756 
#define                     nPDWN  0x0
2757 
#define                    STOPCK  0x8        /* Stop Clock */
2758 
#define                   nSTOPCK  0x0
2759 
#define                   PLL_OFF  0x2        /* Disable PLL */
2760 
#define                  nPLL_OFF  0x0
2761 
#define                        DF  0x1        /* Divide Frequency */
2762 
#define                       nDF  0x0
2763 
 
2764 
/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
2765 
#ifdef _MISRA_RULES
2766 
#define SET_MSEL(x)             (((x)&0x3Fu) << 9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
2767 
#else
2768 
#define SET_MSEL(x)             (((x)&0x3F) << 9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
2769 
#endif /* _MISRA_RULES */
2770 
 
2771 
/* Bit masks for PLL_STAT */
2772 
 
2773 
#define                PLL_LOCKED  0x20       /* PLL Locked Status */
2774 
#define               nPLL_LOCKED  0x0
2775 
#define        ACTIVE_PLLDISABLED  0x4        /* Active Mode With PLL Disabled */
2776 
#define       nACTIVE_PLLDISABLED  0x0
2777 
#define                   FULL_ON  0x2        /* Full-On Mode */
2778 
#define                  nFULL_ON  0x0
2779 
#define         ACTIVE_PLLENABLED  0x1        /* Active Mode With PLL Enabled */
2780 
#define        nACTIVE_PLLENABLED  0x0
2781 
#define                     RTCWS  0x400      /* RTC/Reset Wake-Up Status */
2782 
#define                    nRTCWS  0x0
2783 
#define                     CANWS  0x800      /* CAN Wake-Up Status */
2784 
#define                    nCANWS  0x0
2785 
#define                     USBWS  0x2000     /* USB Wake-Up Status */
2786 
#define                    nUSBWS  0x0
2787 
#define                    KPADWS  0x4000     /* Keypad Wake-Up Status */
2788 
#define                   nKPADWS  0x0
2789 
#define                     ROTWS  0x8000     /* Rotary Wake-Up Status */
2790 
#define                    nROTWS  0x0
2791 
#define                      GPWS  0x1000     /* General-Purpose Wake-Up Status */
2792 
#define                     nGPWS  0x0
2793 
 
2794 
/* Bit masks for VR_CTL */
2795 
 
2796 
#define                      FREQ  0x3        /* Regulator Switching Frequency */
2797 
#define                      GAIN  0xc        /* Voltage Output Level Gain */
2798 
#define                      VLEV  0xf0       /* Internal Voltage Level */
2799 
#define                   SCKELOW  0x8000     /* Drive SCKE Low During Reset Enable */
2800 
#define                  nSCKELOW  0x0
2801 
#define                      WAKE  0x100      /* RTC/Reset Wake-Up Enable */
2802 
#define                     nWAKE  0x0
2803 
#define                     CANWE  0x200      /* CAN0/1 Wake-Up Enable */
2804 
#define                    nCANWE  0x0
2805 
#define                      GPWE  0x400      /* General-Purpose Wake-Up Enable */
2806 
#define                     nGPWE  0x0
2807 
#define                     USBWE  0x800      /* USB Wake-Up Enable */
2808 
#define                    nUSBWE  0x0
2809 
#define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
2810 
#define                   nKPADWE  0x0
2811 
#define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
2812 
#define                    nROTWE  0x0
2813 
#define                  CLKBUFOE  0x4000     /* CLKIN Buffer Output Enable */
2814 
#define                 nCLKBUFOE  0x0
2815 
 
2816 
/* VR_CTL Masks (FREQ) */
2817 
#define HIBERNATE               0x0000              /* Powerdown/Bypass On-Board Regulation */
2818 
#define FREQ_333                0x0001              /* Switching Frequency Is 333 kHz */
2819 
#define FREQ_667                0x0002              /* Switching Frequency Is 667 kHz */
2820 
#define FREQ_1000               0x0003              /* Switching Frequency Is 1 MHz */
2821 
 
2822 
/* VR_CTL Masks (GAIN) */
2823 
 
2824 
#define GAIN_5                  0x0000              /* GAIN = 5 */
2825 
#define GAIN_10                 0x0004              /* GAIN = 10 */
2826 
#define GAIN_20                 0x0008              /* GAIN = 20 */
2827 
#define GAIN_50                 0x000C              /* GAIN = 50 */
2828 
 
2829 
/* VR_CTL Masks (VLEV) */
2830 
 
2831 
#define VLEV_085                0x0060              /* VLEV = 0.85 V (-5% - +10% Accuracy) */
2832 
#define VLEV_090                0x0070              /* VLEV = 0.90 V (-5% - +10% Accuracy) */
2833 
#define VLEV_095                0x0080              /* VLEV = 0.95 V (-5% - +10% Accuracy) */
2834 
#define VLEV_100                0x0090              /* VLEV = 1.00 V (-5% - +10% Accuracy) */
2835 
#define VLEV_105                0x00A0              /* VLEV = 1.05 V (-5% - +10% Accuracy) */
2836 
#define VLEV_110                0x00B0              /* VLEV = 1.10 V (-5% - +10% Accuracy) */
2837 
#define VLEV_115                0x00C0              /* VLEV = 1.15 V (-5% - +10% Accuracy) */
2838 
#define VLEV_120                0x00D0              /* VLEV = 1.20 V (-5% - +10% Accuracy) */
2839 
#define VLEV_125                0x00E0              /* VLEV = 1.25 V (-5% - +10% Accuracy) */
2840 
#define VLEV_130                0x00F0              /* VLEV = 1.30 V (-5% - +10% Accuracy) */
2841 
 
2842 
/* Bit masks for NFC_CTL */
2843 
 
2844 
#define                    WR_DLY  0xf        /* Write Strobe Delay */
2845 
#define                    RD_DLY  0xf0       /* Read Strobe Delay */
2846 
#define                    NWIDTH  0x100      /* NAND Data Width */
2847 
#define                   nNWIDTH  0x0
2848 
#define                   PG_SIZE  0x200      /* Page Size */
2849 
#define                  nPG_SIZE  0x0
2850 
 
2851 
/* Bit masks for NFC_STAT */
2852 
 
2853 
#define                     NBUSY  0x1        /* Not Busy */
2854 
#define                    nNBUSY  0x0
2855 
#define                   WB_FULL  0x2        /* Write Buffer Full */
2856 
#define                  nWB_FULL  0x0
2857 
#define                PG_WR_STAT  0x4        /* Page Write Pending */
2858 
#define               nPG_WR_STAT  0x0
2859 
#define                PG_RD_STAT  0x8        /* Page Read Pending */
2860 
#define               nPG_RD_STAT  0x0
2861 
#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
2862 
#define                 nWB_EMPTY  0x0
2863 
 
2864 
/* Bit masks for NFC_IRQSTAT */
2865 
 
2866 
#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
2867 
#define                 nNBUSYIRQ  0x0
2868 
#define                    WB_OVF  0x2        /* Write Buffer Overflow */
2869 
#define                   nWB_OVF  0x0
2870 
#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
2871 
#define                  nWB_EDGE  0x0
2872 
#define                    RD_RDY  0x8        /* Read Data Ready */
2873 
#define                   nRD_RDY  0x0
2874 
#define                   WR_DONE  0x10       /* Page Write Done */
2875 
#define                  nWR_DONE  0x0
2876 
 
2877 
/* Bit masks for NFC_IRQMASK */
2878 
 
2879 
#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
2880 
#define             nMASK_BUSYIRQ  0x0
2881 
#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
2882 
#define               nMASK_WBOVF  0x0
2883 
#define               MASK_WBEDGE  0x4        /* Mask Write Buffer Edge Detect */
2884 
#define              nMASK_WBEDGE  0x0
2885 
#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
2886 
#define               nMASK_RDRDY  0x0
2887 
#define               MASK_WRDONE  0x10       /* Mask Write Done */
2888 
#define              nMASK_WRDONE  0x0
2889 
 
2890 
/* Bit masks for NFC_RST */
2891 
 
2892 
#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
2893 
#define                  nECC_RST  0x0
2894 
 
2895 
/* Bit masks for NFC_PGCTL */
2896 
 
2897 
#define               PG_RD_START  0x1        /* Page Read Start */
2898 
#define              nPG_RD_START  0x0
2899 
#define               PG_WR_START  0x2        /* Page Write Start */
2900 
#define              nPG_WR_START  0x0
2901 
 
2902 
/* Bit masks for NFC_ECC0 */
2903 
 
2904 
#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
2905 
 
2906 
/* Bit masks for NFC_ECC1 */
2907 
 
2908 
#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
2909 
 
2910 
/* Bit masks for NFC_ECC2 */
2911 
 
2912 
#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
2913 
 
2914 
/* Bit masks for NFC_ECC3 */
2915 
 
2916 
#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
2917 
 
2918 
/* Bit masks for NFC_COUNT */
2919 
 
2920 
#define                    ECCCNT  0x3ff      /* Transfer Count */
2921 
 
2922 
/* Bit masks for CAN0_CONTROL */
2923 
 
2924 
#define                       SRS  0x1        /* Software Reset */
2925 
#define                      nSRS  0x0
2926 
#define                       DNM  0x2        /* DeviceNet Mode */
2927 
#define                      nDNM  0x0
2928 
#define                       ABO  0x4        /* Auto Bus On */
2929 
#define                      nABO  0x0
2930 
#define                       WBA  0x10       /* Wakeup On CAN Bus Activity */
2931 
#define                      nWBA  0x0
2932 
#define                       SMR  0x20       /* Sleep Mode Request */
2933 
#define                      nSMR  0x0
2934 
#define                       CSR  0x40       /* CAN Suspend Mode Request */
2935 
#define                      nCSR  0x0
2936 
#define                       CCR  0x80       /* CAN Configuration Mode Request */
2937 
#define                      nCCR  0x0
2938 
 
2939 
/* Bit masks for CAN0_STATUS */
2940 
 
2941 
#define                        WT  0x1        /* CAN Transmit Warning Flag */
2942 
#define                       nWT  0x0
2943 
#define                        WR  0x2        /* CAN Receive Warning Flag */
2944 
#define                       nWR  0x0
2945 
#define                        EP  0x4        /* CAN Error Passive Mode */
2946 
#define                       nEP  0x0
2947 
#define                       EBO  0x8        /* CAN Error Bus Off Mode */
2948 
#define                      nEBO  0x0
2949 
#define                       CSA  0x40       /* CAN Suspend Mode Acknowledge */
2950 
#define                      nCSA  0x0
2951 
#define                       CCA  0x80       /* CAN Configuration Mode Acknowledge */
2952 
#define                      nCCA  0x0
2953 
#define                     MBPTR  0x1f00     /* Mailbox Pointer */
2954 
#define                       TRM  0x4000     /* Transmit Mode Status */
2955 
#define                      nTRM  0x0
2956 
#define                       REC  0x8000     /* Receive Mode Status */
2957 
#define                      nREC  0x0
2958 
 
2959 
/* Bit masks for CAN0_DEBUG */
2960 
 
2961 
#define                       DEC  0x1        /* Disable Transmit/Receive Error Counters */
2962 
#define                      nDEC  0x0
2963 
#define                       DRI  0x2        /* Disable CANRX Input Pin */
2964 
#define                      nDRI  0x0
2965 
#define                       DTO  0x4        /* Disable CANTX Output Pin */
2966 
#define                      nDTO  0x0
2967 
#define                       DIL  0x8        /* Disable Internal Loop */
2968 
#define                      nDIL  0x0
2969 
#define                       MAA  0x10       /* Mode Auto-Acknowledge */
2970 
#define                      nMAA  0x0
2971 
#define                       MRB  0x20       /* Mode Read Back */
2972 
#define                      nMRB  0x0
2973 
#define                       CDE  0x8000     /* CAN Debug Mode Enable */
2974 
#define                      nCDE  0x0
2975 
 
2976 
/* Bit masks for CAN0_CLOCK */
2977 
 
2978 
#define                       BRP  0x3ff      /* CAN Bit Rate Prescaler */
2979 
 
2980 
/* Bit masks for CAN0_TIMING */
2981 
 
2982 
#define                       SJW  0x300      /* Synchronization Jump Width */
2983 
#define                       SAM  0x80       /* Sampling */
2984 
#define                      nSAM  0x0
2985 
#define                     TSEG2  0x70       /* Time Segment 2 */
2986 
#define                     TSEG1  0xf        /* Time Segment 1 */
2987 
 
2988 
/* Bit masks for CAN0_INTR */
2989 
 
2990 
#define                     CANRX  0x80       /* Serial Input From Transceiver */
2991 
#define                    nCANRX  0x0
2992 
#define                     CANTX  0x40       /* Serial Output To Transceiver */
2993 
#define                    nCANTX  0x0
2994 
#define                     SMACK  0x8        /* Sleep Mode Acknowledge */
2995 
#define                    nSMACK  0x0
2996 
#define                      GIRQ  0x4        /* Global Interrupt Request Status */
2997 
#define                     nGIRQ  0x0
2998 
#define                    MBTIRQ  0x2        /* Mailbox Transmit Interrupt Request */
2999 
#define                   nMBTIRQ  0x0
3000 
#define                    MBRIRQ  0x1        /* Mailbox Receive Interrupt Request */
3001 
#define                   nMBRIRQ  0x0
3002 
 
3003 
/* Bit masks for CAN0_GIM */
3004 
 
3005 
#define                     EWTIM  0x1        /* Error Warning Transmit Interrupt Mask */
3006 
#define                    nEWTIM  0x0
3007 
#define                     EWRIM  0x2        /* Error Warning Receive Interrupt Mask */
3008 
#define                    nEWRIM  0x0
3009 
#define                      EPIM  0x4        /* Error Passive Interrupt Mask */
3010 
#define                     nEPIM  0x0
3011 
#define                      BOIM  0x8        /* Bus Off Interrupt Mask */
3012 
#define                     nBOIM  0x0
3013 
#define                      WUIM  0x10       /* Wakeup Interrupt Mask */
3014 
#define                     nWUIM  0x0
3015 
#define                     UIAIM  0x20       /* Unimplemented Address Interrupt Mask */
3016 
#define                    nUIAIM  0x0
3017 
#define                      AAIM  0x40       /* Abort Acknowledge Interrupt Mask */
3018 
#define                     nAAIM  0x0
3019 
#define                     RMLIM  0x80       /* Receive Message Lost Interrupt Mask */
3020 
#define                    nRMLIM  0x0
3021 
#define                     UCEIM  0x100      /* Universal Counter Exceeded Interrupt Mask */
3022 
#define                    nUCEIM  0x0
3023 
#define                      ADIM  0x400      /* Access Denied Interrupt Mask */
3024 
#define                     nADIM  0x0
3025 
 
3026 
/* Bit masks for CAN0_GIS */
3027 
 
3028 
#define                     EWTIS  0x1        /* Error Warning Transmit Interrupt Status */
3029 
#define                    nEWTIS  0x0
3030 
#define                     EWRIS  0x2        /* Error Warning Receive Interrupt Status */
3031 
#define                    nEWRIS  0x0
3032 
#define                      EPIS  0x4        /* Error Passive Interrupt Status */
3033 
#define                     nEPIS  0x0
3034 
#define                      BOIS  0x8        /* Bus Off Interrupt Status */
3035 
#define                     nBOIS  0x0
3036 
#define                      WUIS  0x10       /* Wakeup Interrupt Status */
3037 
#define                     nWUIS  0x0
3038 
#define                     UIAIS  0x20       /* Unimplemented Address Interrupt Status */
3039 
#define                    nUIAIS  0x0
3040 
#define                      AAIS  0x40       /* Abort Acknowledge Interrupt Status */
3041 
#define                     nAAIS  0x0
3042 
#define                     RMLIS  0x80       /* Receive Message Lost Interrupt Status */
3043 
#define                    nRMLIS  0x0
3044 
#define                     UCEIS  0x100      /* Universal Counter Exceeded Interrupt Status */
3045 
#define                    nUCEIS  0x0
3046 
#define                      ADIS  0x400      /* Access Denied Interrupt Status */
3047 
#define                     nADIS  0x0
3048 
 
3049 
/* Bit masks for CAN0_GIF */
3050 
 
3051 
#define                     EWTIF  0x1        /* Error Warning Transmit Interrupt Flag */
3052 
#define                    nEWTIF  0x0
3053 
#define                     EWRIF  0x2        /* Error Warning Receive Interrupt Flag */
3054 
#define                    nEWRIF  0x0
3055 
#define                      EPIF  0x4        /* Error Passive Interrupt Flag */
3056 
#define                     nEPIF  0x0
3057 
#define                      BOIF  0x8        /* Bus Off Interrupt Flag */
3058 
#define                     nBOIF  0x0
3059 
#define                      WUIF  0x10       /* Wakeup Interrupt Flag */
3060 
#define                     nWUIF  0x0
3061 
#define                     UIAIF  0x20       /* Unimplemented Address Interrupt Flag */
3062 
#define                    nUIAIF  0x0
3063 
#define                      AAIF  0x40       /* Abort Acknowledge Interrupt Flag */
3064 
#define                     nAAIF  0x0
3065 
#define                     RMLIF  0x80       /* Receive Message Lost Interrupt Flag */
3066 
#define                    nRMLIF  0x0
3067 
#define                     UCEIF  0x100      /* Universal Counter Exceeded Interrupt Flag */
3068 
#define                    nUCEIF  0x0
3069 
#define                      ADIF  0x400      /* Access Denied Interrupt Flag */
3070 
#define                     nADIF  0x0
3071 
 
3072 
/* Bit masks for CAN0_MBTD */
3073 
 
3074 
#define                       TDR  0x80       /* Temporary Disable Request */
3075 
#define                      nTDR  0x0
3076 
#define                       TDA  0x40       /* Temporary Disable Acknowledge */
3077 
#define                      nTDA  0x0
3078 
#define                     TDPTR  0x1f       /* Temporary Disable Pointer */
3079 
 
3080 
/* Bit masks for CAN0_UCCNF */
3081 
 
3082 
#define                     UCCNF  0xf        /* Universal Counter Configuration */
3083 
#define                      UCRC  0x20       /* Universal Counter Reload/Clear */
3084 
#define                     nUCRC  0x0
3085 
#define                      UCCT  0x40       /* Universal Counter CAN Trigger */
3086 
#define                     nUCCT  0x0
3087 
#define                       UCE  0x80       /* Universal Counter Enable */
3088 
#define                      nUCE  0x0
3089 
 
3090 
/* Bit masks for CAN0_UCCNT */
3091 
 
3092 
#define                     UCCNT  0xffff     /* Universal Counter Count Value */
3093 
 
3094 
/* Bit masks for CAN0_UCRC */
3095 
 
3096 
#define                     UCVAL  0xffff     /* Universal Counter Reload/Capture Value */
3097 
 
3098 
/* Bit masks for CAN0_CEC */
3099 
 
3100 
#define                    RXECNT  0xff       /* Receive Error Counter */
3101 
#define                    TXECNT  0xff00     /* Transmit Error Counter */
3102 
 
3103 
/* Bit masks for CAN0_ESR */
3104 
 
3105 
#define                       FER  0x80       /* Form Error */
3106 
#define                      nFER  0x0
3107 
#define                       BEF  0x40       /* Bit Error Flag */
3108 
#define                      nBEF  0x0
3109 
#define                       SA0  0x20       /* Stuck At Dominant */
3110 
#define                      nSA0  0x0
3111 
#define                      CRCE  0x10       /* CRC Error */
3112 
#define                     nCRCE  0x0
3113 
#define                       SER  0x8        /* Stuff Bit Error */
3114 
#define                      nSER  0x0
3115 
#define                      ACKE  0x4        /* Acknowledge Error */
3116 
#define                     nACKE  0x0
3117 
 
3118 
/* Bit masks for CAN0_EWR */
3119 
 
3120 
#define                    EWLTEC  0xff00     /* Transmit Error Warning Limit */
3121 
#define                    EWLREC  0xff       /* Receive Error Warning Limit */
3122 
 
3123 
/* Bit masks for CAN0_AMxx_H */
3124 
 
3125 
#define                       FDF  0x8000     /* Filter On Data Field */
3126 
#define                      nFDF  0x0
3127 
#define                       FMD  0x4000     /* Full Mask Data */
3128 
#define                      nFMD  0x0
3129 
#define                     AMIDE  0x2000     /* Acceptance Mask Identifier Extension */
3130 
#define                    nAMIDE  0x0
3131 
#define                    BASEID  0x1ffc     /* Base Identifier */
3132 
#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
3133 
 
3134 
/* Bit masks for CAN0_AMxx_L */
3135 
 
3136 
#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
3137 
#define                       DFM  0xffff     /* Data Field Mask */
3138 
 
3139 
/* Bit masks for CAN0_MBxx_ID1 */
3140 
 
3141 
#define                       AME  0x8000     /* Acceptance Mask Enable */
3142 
#define                      nAME  0x0
3143 
#define                       RTR  0x4000     /* Remote Transmission Request */
3144 
#define                      nRTR  0x0
3145 
#define                       IDE  0x2000     /* Identifier Extension */
3146 
#define                      nIDE  0x0
3147 
#define                    BASEID  0x1ffc     /* Base Identifier */
3148 
#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
3149 
 
3150 
/* Bit masks for CAN0_MBxx_ID0 */
3151 
 
3152 
#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
3153 
#define                       DFM  0xffff     /* Data Field Mask */
3154 
 
3155 
/* Bit masks for CAN0_MBxx_TIMESTAMP */
3156 
 
3157 
#define                       TSV  0xffff     /* Time Stamp Value */
3158 
 
3159 
/* Bit masks for CAN0_MBxx_LENGTH */
3160 
 
3161 
#define                       DLC  0xf        /* Data Length Code */
3162 
 
3163 
/* Bit masks for CAN0_MBxx_DATA3 */
3164 
 
3165 
#define                 CAN_BYTE0  0xff00     /* Data Field Byte 0 */
3166 
#define                 CAN_BYTE1  0xff       /* Data Field Byte 1 */
3167 
 
3168 
/* Bit masks for CAN0_MBxx_DATA2 */
3169 
 
3170 
#define                 CAN_BYTE2  0xff00     /* Data Field Byte 2 */
3171 
#define                 CAN_BYTE3  0xff       /* Data Field Byte 3 */
3172 
 
3173 
/* Bit masks for CAN0_MBxx_DATA1 */
3174 
 
3175 
#define                 CAN_BYTE4  0xff00     /* Data Field Byte 4 */
3176 
#define                 CAN_BYTE5  0xff       /* Data Field Byte 5 */
3177 
 
3178 
/* Bit masks for CAN0_MBxx_DATA0 */
3179 
 
3180 
#define                 CAN_BYTE6  0xff00     /* Data Field Byte 6 */
3181 
#define                 CAN_BYTE7  0xff       /* Data Field Byte 7 */
3182 
 
3183 
/* Bit masks for CAN0_MC1 */
3184 
 
3185 
#define                       MC0  0x1        /* Mailbox 0 Enable */
3186 
#define                      nMC0  0x0
3187 
#define                       MC1  0x2        /* Mailbox 1 Enable */
3188 
#define                      nMC1  0x0
3189 
#define                       MC2  0x4        /* Mailbox 2 Enable */
3190 
#define                      nMC2  0x0
3191 
#define                       MC3  0x8        /* Mailbox 3 Enable */
3192 
#define                      nMC3  0x0
3193 
#define                       MC4  0x10       /* Mailbox 4 Enable */
3194 
#define                      nMC4  0x0
3195 
#define                       MC5  0x20       /* Mailbox 5 Enable */
3196 
#define                      nMC5  0x0
3197 
#define                       MC6  0x40       /* Mailbox 6 Enable */
3198 
#define                      nMC6  0x0
3199 
#define                       MC7  0x80       /* Mailbox 7 Enable */
3200 
#define                      nMC7  0x0
3201 
#define                       MC8  0x100      /* Mailbox 8 Enable */
3202 
#define                      nMC8  0x0
3203 
#define                       MC9  0x200      /* Mailbox 9 Enable */
3204 
#define                      nMC9  0x0
3205 
#define                      MC10  0x400      /* Mailbox 10 Enable */
3206 
#define                     nMC10  0x0
3207 
#define                      MC11  0x800      /* Mailbox 11 Enable */
3208 
#define                     nMC11  0x0
3209 
#define                      MC12  0x1000     /* Mailbox 12 Enable */
3210 
#define                     nMC12  0x0
3211 
#define                      MC13  0x2000     /* Mailbox 13 Enable */
3212 
#define                     nMC13  0x0
3213 
#define                      MC14  0x4000     /* Mailbox 14 Enable */
3214 
#define                     nMC14  0x0
3215 
#define                      MC15  0x8000     /* Mailbox 15 Enable */
3216 
#define                     nMC15  0x0
3217 
 
3218 
/* Bit masks for CAN0_MC2 */
3219 
 
3220 
#define                      MC16  0x1        /* Mailbox 16 Enable */
3221 
#define                     nMC16  0x0
3222 
#define                      MC17  0x2        /* Mailbox 17 Enable */
3223 
#define                     nMC17  0x0
3224 
#define                      MC18  0x4        /* Mailbox 18 Enable */
3225 
#define                     nMC18  0x0
3226 
#define                      MC19  0x8        /* Mailbox 19 Enable */
3227 
#define                     nMC19  0x0
3228 
#define                      MC20  0x10       /* Mailbox 20 Enable */
3229 
#define                     nMC20  0x0
3230 
#define                      MC21  0x20       /* Mailbox 21 Enable */
3231 
#define                     nMC21  0x0
3232 
#define                      MC22  0x40       /* Mailbox 22 Enable */
3233 
#define                     nMC22  0x0
3234 
#define                      MC23  0x80       /* Mailbox 23 Enable */
3235 
#define                     nMC23  0x0
3236 
#define                      MC24  0x100      /* Mailbox 24 Enable */
3237 
#define                     nMC24  0x0
3238 
#define                      MC25  0x200      /* Mailbox 25 Enable */
3239 
#define                     nMC25  0x0
3240 
#define                      MC26  0x400      /* Mailbox 26 Enable */
3241 
#define                     nMC26  0x0
3242 
#define                      MC27  0x800      /* Mailbox 27 Enable */
3243 
#define                     nMC27  0x0
3244 
#define                      MC28  0x1000     /* Mailbox 28 Enable */
3245 
#define                     nMC28  0x0
3246 
#define                      MC29  0x2000     /* Mailbox 29 Enable */
3247 
#define                     nMC29  0x0
3248 
#define                      MC30  0x4000     /* Mailbox 30 Enable */
3249 
#define                     nMC30  0x0
3250 
#define                      MC31  0x8000     /* Mailbox 31 Enable */
3251 
#define                     nMC31  0x0
3252 
 
3253 
/* Bit masks for CAN0_MD1 */
3254 
 
3255 
#define                       MD0  0x1        /* Mailbox 0 Receive Enable */
3256 
#define                      nMD0  0x0
3257 
#define                       MD1  0x2        /* Mailbox 1 Receive Enable */
3258 
#define                      nMD1  0x0
3259 
#define                       MD2  0x4        /* Mailbox 2 Receive Enable */
3260 
#define                      nMD2  0x0
3261 
#define                       MD3  0x8        /* Mailbox 3 Receive Enable */
3262 
#define                      nMD3  0x0
3263 
#define                       MD4  0x10       /* Mailbox 4 Receive Enable */
3264 
#define                      nMD4  0x0
3265 
#define                       MD5  0x20       /* Mailbox 5 Receive Enable */
3266 
#define                      nMD5  0x0
3267 
#define                       MD6  0x40       /* Mailbox 6 Receive Enable */
3268 
#define                      nMD6  0x0
3269 
#define                       MD7  0x80       /* Mailbox 7 Receive Enable */
3270 
#define                      nMD7  0x0
3271 
#define                       MD8  0x100      /* Mailbox 8 Receive Enable */
3272 
#define                      nMD8  0x0
3273 
#define                       MD9  0x200      /* Mailbox 9 Receive Enable */
3274 
#define                      nMD9  0x0
3275 
#define                      MD10  0x400      /* Mailbox 10 Receive Enable */
3276 
#define                     nMD10  0x0
3277 
#define                      MD11  0x800      /* Mailbox 11 Receive Enable */
3278 
#define                     nMD11  0x0
3279 
#define                      MD12  0x1000     /* Mailbox 12 Receive Enable */
3280 
#define                     nMD12  0x0
3281 
#define                      MD13  0x2000     /* Mailbox 13 Receive Enable */
3282 
#define                     nMD13  0x0
3283 
#define                      MD14  0x4000     /* Mailbox 14 Receive Enable */
3284 
#define                     nMD14  0x0
3285 
#define                      MD15  0x8000     /* Mailbox 15 Receive Enable */
3286 
#define                     nMD15  0x0
3287 
 
3288 
/* Bit masks for CAN0_MD2 */
3289 
 
3290 
#define                      MD16  0x1        /* Mailbox 16 Receive Enable */
3291 
#define                     nMD16  0x0
3292 
#define                      MD17  0x2        /* Mailbox 17 Receive Enable */
3293 
#define                     nMD17  0x0
3294 
#define                      MD18  0x4        /* Mailbox 18 Receive Enable */
3295 
#define                     nMD18  0x0
3296 
#define                      MD19  0x8        /* Mailbox 19 Receive Enable */
3297 
#define                     nMD19  0x0
3298 
#define                      MD20  0x10       /* Mailbox 20 Receive Enable */
3299 
#define                     nMD20  0x0
3300 
#define                      MD21  0x20       /* Mailbox 21 Receive Enable */
3301 
#define                     nMD21  0x0
3302 
#define                      MD22  0x40       /* Mailbox 22 Receive Enable */
3303 
#define                     nMD22  0x0
3304 
#define                      MD23  0x80       /* Mailbox 23 Receive Enable */
3305 
#define                     nMD23  0x0
3306 
#define                      MD24  0x100      /* Mailbox 24 Receive Enable */
3307 
#define                     nMD24  0x0
3308 
#define                      MD25  0x200      /* Mailbox 25 Receive Enable */
3309 
#define                     nMD25  0x0
3310 
#define                      MD26  0x400      /* Mailbox 26 Receive Enable */
3311 
#define                     nMD26  0x0
3312 
#define                      MD27  0x800      /* Mailbox 27 Receive Enable */
3313 
#define                     nMD27  0x0
3314 
#define                      MD28  0x1000     /* Mailbox 28 Receive Enable */
3315 
#define                     nMD28  0x0
3316 
#define                      MD29  0x2000     /* Mailbox 29 Receive Enable */
3317 
#define                     nMD29  0x0
3318 
#define                      MD30  0x4000     /* Mailbox 30 Receive Enable */
3319 
#define                     nMD30  0x0
3320 
#define                      MD31  0x8000     /* Mailbox 31 Receive Enable */
3321 
#define                     nMD31  0x0
3322 
 
3323 
/* Bit masks for CAN0_RMP1 */
3324 
 
3325 
#define                      RMP0  0x1        /* Mailbox 0 Receive Message Pending */
3326 
#define                     nRMP0  0x0
3327 
#define                      RMP1  0x2        /* Mailbox 1 Receive Message Pending */
3328 
#define                     nRMP1  0x0
3329 
#define                      RMP2  0x4        /* Mailbox 2 Receive Message Pending */
3330 
#define                     nRMP2  0x0
3331 
#define                      RMP3  0x8        /* Mailbox 3 Receive Message Pending */
3332 
#define                     nRMP3  0x0
3333 
#define                      RMP4  0x10       /* Mailbox 4 Receive Message Pending */
3334 
#define                     nRMP4  0x0
3335 
#define                      RMP5  0x20       /* Mailbox 5 Receive Message Pending */
3336 
#define                     nRMP5  0x0
3337 
#define                      RMP6  0x40       /* Mailbox 6 Receive Message Pending */
3338 
#define                     nRMP6  0x0
3339 
#define                      RMP7  0x80       /* Mailbox 7 Receive Message Pending */
3340 
#define                     nRMP7  0x0
3341 
#define                      RMP8  0x100      /* Mailbox 8 Receive Message Pending */
3342 
#define                     nRMP8  0x0
3343 
#define                      RMP9  0x200      /* Mailbox 9 Receive Message Pending */
3344 
#define                     nRMP9  0x0
3345 
#define                     RMP10  0x400      /* Mailbox 10 Receive Message Pending */
3346 
#define                    nRMP10  0x0
3347 
#define                     RMP11  0x800      /* Mailbox 11 Receive Message Pending */
3348 
#define                    nRMP11  0x0
3349 
#define                     RMP12  0x1000     /* Mailbox 12 Receive Message Pending */
3350 
#define                    nRMP12  0x0
3351 
#define                     RMP13  0x2000     /* Mailbox 13 Receive Message Pending */
3352 
#define                    nRMP13  0x0
3353 
#define                     RMP14  0x4000     /* Mailbox 14 Receive Message Pending */
3354 
#define                    nRMP14  0x0
3355 
#define                     RMP15  0x8000     /* Mailbox 15 Receive Message Pending */
3356 
#define                    nRMP15  0x0
3357 
 
3358 
/* Bit masks for CAN0_RMP2 */
3359 
 
3360 
#define                     RMP16  0x1        /* Mailbox 16 Receive Message Pending */
3361 
#define                    nRMP16  0x0
3362 
#define                     RMP17  0x2        /* Mailbox 17 Receive Message Pending */
3363 
#define                    nRMP17  0x0
3364 
#define                     RMP18  0x4        /* Mailbox 18 Receive Message Pending */
3365 
#define                    nRMP18  0x0
3366 
#define                     RMP19  0x8        /* Mailbox 19 Receive Message Pending */
3367 
#define                    nRMP19  0x0
3368 
#define                     RMP20  0x10       /* Mailbox 20 Receive Message Pending */
3369 
#define                    nRMP20  0x0
3370 
#define                     RMP21  0x20       /* Mailbox 21 Receive Message Pending */
3371 
#define                    nRMP21  0x0
3372 
#define                     RMP22  0x40       /* Mailbox 22 Receive Message Pending */
3373 
#define                    nRMP22  0x0
3374 
#define                     RMP23  0x80       /* Mailbox 23 Receive Message Pending */
3375 
#define                    nRMP23  0x0
3376 
#define                     RMP24  0x100      /* Mailbox 24 Receive Message Pending */
3377 
#define                    nRMP24  0x0
3378 
#define                     RMP25  0x200      /* Mailbox 25 Receive Message Pending */
3379 
#define                    nRMP25  0x0
3380 
#define                     RMP26  0x400      /* Mailbox 26 Receive Message Pending */
3381 
#define                    nRMP26  0x0
3382 
#define                     RMP27  0x800      /* Mailbox 27 Receive Message Pending */
3383 
#define                    nRMP27  0x0
3384 
#define                     RMP28  0x1000     /* Mailbox 28 Receive Message Pending */
3385 
#define                    nRMP28  0x0
3386 
#define                     RMP29  0x2000     /* Mailbox 29 Receive Message Pending */
3387 
#define                    nRMP29  0x0
3388 
#define                     RMP30  0x4000     /* Mailbox 30 Receive Message Pending */
3389 
#define                    nRMP30  0x0
3390 
#define                     RMP31  0x8000     /* Mailbox 31 Receive Message Pending */
3391 
#define                    nRMP31  0x0
3392 
 
3393 
/* Bit masks for CAN0_RML1 */
3394 
 
3395 
#define                      RML0  0x1        /* Mailbox 0 Receive Message Lost */
3396 
#define                     nRML0  0x0
3397 
#define                      RML1  0x2        /* Mailbox 1 Receive Message Lost */
3398 
#define                     nRML1  0x0
3399 
#define                      RML2  0x4        /* Mailbox 2 Receive Message Lost */
3400 
#define                     nRML2  0x0
3401 
#define                      RML3  0x8        /* Mailbox 3 Receive Message Lost */
3402 
#define                     nRML3  0x0
3403 
#define                      RML4  0x10       /* Mailbox 4 Receive Message Lost */
3404 
#define                     nRML4  0x0
3405 
#define                      RML5  0x20       /* Mailbox 5 Receive Message Lost */
3406 
#define                     nRML5  0x0
3407 
#define                      RML6  0x40       /* Mailbox 6 Receive Message Lost */
3408 
#define                     nRML6  0x0
3409 
#define                      RML7  0x80       /* Mailbox 7 Receive Message Lost */
3410 
#define                     nRML7  0x0
3411 
#define                      RML8  0x100      /* Mailbox 8 Receive Message Lost */
3412 
#define                     nRML8  0x0
3413 
#define                      RML9  0x200      /* Mailbox 9 Receive Message Lost */
3414 
#define                     nRML9  0x0
3415 
#define                     RML10  0x400      /* Mailbox 10 Receive Message Lost */
3416 
#define                    nRML10  0x0
3417 
#define                     RML11  0x800      /* Mailbox 11 Receive Message Lost */
3418 
#define                    nRML11  0x0
3419 
#define                     RML12  0x1000     /* Mailbox 12 Receive Message Lost */
3420 
#define                    nRML12  0x0
3421 
#define                     RML13  0x2000     /* Mailbox 13 Receive Message Lost */
3422 
#define                    nRML13  0x0
3423 
#define                     RML14  0x4000     /* Mailbox 14 Receive Message Lost */
3424 
#define                    nRML14  0x0
3425 
#define                     RML15  0x8000     /* Mailbox 15 Receive Message Lost */
3426 
#define                    nRML15  0x0
3427 
 
3428 
/* Bit masks for CAN0_RML2 */
3429 
 
3430 
#define                     RML16  0x1        /* Mailbox 16 Receive Message Lost */
3431 
#define                    nRML16  0x0
3432 
#define                     RML17  0x2        /* Mailbox 17 Receive Message Lost */
3433 
#define                    nRML17  0x0
3434 
#define                     RML18  0x4        /* Mailbox 18 Receive Message Lost */
3435 
#define                    nRML18  0x0
3436 
#define                     RML19  0x8        /* Mailbox 19 Receive Message Lost */
3437 
#define                    nRML19  0x0
3438 
#define                     RML20  0x10       /* Mailbox 20 Receive Message Lost */
3439 
#define                    nRML20  0x0
3440 
#define                     RML21  0x20       /* Mailbox 21 Receive Message Lost */
3441 
#define                    nRML21  0x0
3442 
#define                     RML22  0x40       /* Mailbox 22 Receive Message Lost */
3443 
#define                    nRML22  0x0
3444 
#define                     RML23  0x80       /* Mailbox 23 Receive Message Lost */
3445 
#define                    nRML23  0x0
3446 
#define                     RML24  0x100      /* Mailbox 24 Receive Message Lost */
3447 
#define                    nRML24  0x0
3448 
#define                     RML25  0x200      /* Mailbox 25 Receive Message Lost */
3449 
#define                    nRML25  0x0
3450 
#define                     RML26  0x400      /* Mailbox 26 Receive Message Lost */
3451 
#define                    nRML26  0x0
3452 
#define                     RML27  0x800      /* Mailbox 27 Receive Message Lost */
3453 
#define                    nRML27  0x0
3454 
#define                     RML28  0x1000     /* Mailbox 28 Receive Message Lost */
3455 
#define                    nRML28  0x0
3456 
#define                     RML29  0x2000     /* Mailbox 29 Receive Message Lost */
3457 
#define                    nRML29  0x0
3458 
#define                     RML30  0x4000     /* Mailbox 30 Receive Message Lost */
3459 
#define                    nRML30  0x0
3460 
#define                     RML31  0x8000     /* Mailbox 31 Receive Message Lost */
3461 
#define                    nRML31  0x0
3462 
 
3463 
/* Bit masks for CAN0_OPSS1 */
3464 
 
3465 
#define                     OPSS0  0x1        /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
3466 
#define                    nOPSS0  0x0
3467 
#define                     OPSS1  0x2        /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
3468 
#define                    nOPSS1  0x0
3469 
#define                     OPSS2  0x4        /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
3470 
#define                    nOPSS2  0x0
3471 
#define                     OPSS3  0x8        /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
3472 
#define                    nOPSS3  0x0
3473 
#define                     OPSS4  0x10       /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
3474 
#define                    nOPSS4  0x0
3475 
#define                     OPSS5  0x20       /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
3476 
#define                    nOPSS5  0x0
3477 
#define                     OPSS6  0x40       /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
3478 
#define                    nOPSS6  0x0
3479 
#define                     OPSS7  0x80       /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
3480 
#define                    nOPSS7  0x0
3481 
#define                     OPSS8  0x100      /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
3482 
#define                    nOPSS8  0x0
3483 
#define                     OPSS9  0x200      /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
3484 
#define                    nOPSS9  0x0
3485 
#define                    OPSS10  0x400      /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
3486 
#define                   nOPSS10  0x0
3487 
#define                    OPSS11  0x800      /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
3488 
#define                   nOPSS11  0x0
3489 
#define                    OPSS12  0x1000     /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
3490 
#define                   nOPSS12  0x0
3491 
#define                    OPSS13  0x2000     /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
3492 
#define                   nOPSS13  0x0
3493 
#define                    OPSS14  0x4000     /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
3494 
#define                   nOPSS14  0x0
3495 
#define                    OPSS15  0x8000     /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
3496 
#define                   nOPSS15  0x0
3497 
 
3498 
/* Bit masks for CAN0_OPSS2 */
3499 
 
3500 
#define                    OPSS16  0x1        /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
3501 
#define                   nOPSS16  0x0
3502 
#define                    OPSS17  0x2        /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
3503 
#define                   nOPSS17  0x0
3504 
#define                    OPSS18  0x4        /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
3505 
#define                   nOPSS18  0x0
3506 
#define                    OPSS19  0x8        /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
3507 
#define                   nOPSS19  0x0
3508 
#define                    OPSS20  0x10       /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
3509 
#define                   nOPSS20  0x0
3510 
#define                    OPSS21  0x20       /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
3511 
#define                   nOPSS21  0x0
3512 
#define                    OPSS22  0x40       /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
3513 
#define                   nOPSS22  0x0
3514 
#define                    OPSS23  0x80       /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
3515 
#define                   nOPSS23  0x0
3516 
#define                    OPSS24  0x100      /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
3517 
#define                   nOPSS24  0x0
3518 
#define                    OPSS25  0x200      /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
3519 
#define                   nOPSS25  0x0
3520 
#define                    OPSS26  0x400      /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
3521 
#define                   nOPSS26  0x0
3522 
#define                    OPSS27  0x800      /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
3523 
#define                   nOPSS27  0x0
3524 
#define                    OPSS28  0x1000     /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
3525 
#define                   nOPSS28  0x0
3526 
#define                    OPSS29  0x2000     /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
3527 
#define                   nOPSS29  0x0
3528 
#define                    OPSS30  0x4000     /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
3529 
#define                   nOPSS30  0x0
3530 
#define                    OPSS31  0x8000     /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
3531 
#define                   nOPSS31  0x0
3532 
 
3533 
/* Bit masks for CAN0_TRS1 */
3534 
 
3535 
#define                      TRS0  0x1        /* Mailbox 0 Transmit Request Set */
3536 
#define                     nTRS0  0x0
3537 
#define                      TRS1  0x2        /* Mailbox 1 Transmit Request Set */
3538 
#define                     nTRS1  0x0
3539 
#define                      TRS2  0x4        /* Mailbox 2 Transmit Request Set */
3540 
#define                     nTRS2  0x0
3541 
#define                      TRS3  0x8        /* Mailbox 3 Transmit Request Set */
3542 
#define                     nTRS3  0x0
3543 
#define                      TRS4  0x10       /* Mailbox 4 Transmit Request Set */
3544 
#define                     nTRS4  0x0
3545 
#define                      TRS5  0x20       /* Mailbox 5 Transmit Request Set */
3546 
#define                     nTRS5  0x0
3547 
#define                      TRS6  0x40       /* Mailbox 6 Transmit Request Set */
3548 
#define                     nTRS6  0x0
3549 
#define                      TRS7  0x80       /* Mailbox 7 Transmit Request Set */
3550 
#define                     nTRS7  0x0
3551 
#define                      TRS8  0x100      /* Mailbox 8 Transmit Request Set */
3552 
#define                     nTRS8  0x0
3553 
#define                      TRS9  0x200      /* Mailbox 9 Transmit Request Set */
3554 
#define                     nTRS9  0x0
3555 
#define                     TRS10  0x400      /* Mailbox 10 Transmit Request Set */
3556 
#define                    nTRS10  0x0
3557 
#define                     TRS11  0x800      /* Mailbox 11 Transmit Request Set */
3558 
#define                    nTRS11  0x0
3559 
#define                     TRS12  0x1000     /* Mailbox 12 Transmit Request Set */
3560 
#define                    nTRS12  0x0
3561 
#define                     TRS13  0x2000     /* Mailbox 13 Transmit Request Set */
3562 
#define                    nTRS13  0x0
3563 
#define                     TRS14  0x4000     /* Mailbox 14 Transmit Request Set */
3564 
#define                    nTRS14  0x0
3565 
#define                     TRS15  0x8000     /* Mailbox 15 Transmit Request Set */
3566 
#define                    nTRS15  0x0
3567 
 
3568 
/* Bit masks for CAN0_TRS2 */
3569 
 
3570 
#define                     TRS16  0x1        /* Mailbox 16 Transmit Request Set */
3571 
#define                    nTRS16  0x0
3572 
#define                     TRS17  0x2        /* Mailbox 17 Transmit Request Set */
3573 
#define                    nTRS17  0x0
3574 
#define                     TRS18  0x4        /* Mailbox 18 Transmit Request Set */
3575 
#define                    nTRS18  0x0
3576 
#define                     TRS19  0x8        /* Mailbox 19 Transmit Request Set */
3577 
#define                    nTRS19  0x0
3578 
#define                     TRS20  0x10       /* Mailbox 20 Transmit Request Set */
3579 
#define                    nTRS20  0x0
3580 
#define                     TRS21  0x20       /* Mailbox 21 Transmit Request Set */
3581 
#define                    nTRS21  0x0
3582 
#define                     TRS22  0x40       /* Mailbox 22 Transmit Request Set */
3583 
#define                    nTRS22  0x0
3584 
#define                     TRS23  0x80       /* Mailbox 23 Transmit Request Set */
3585 
#define                    nTRS23  0x0
3586 
#define                     TRS24  0x100      /* Mailbox 24 Transmit Request Set */
3587 
#define                    nTRS24  0x0
3588 
#define                     TRS25  0x200      /* Mailbox 25 Transmit Request Set */
3589 
#define                    nTRS25  0x0
3590 
#define                     TRS26  0x400      /* Mailbox 26 Transmit Request Set */
3591 
#define                    nTRS26  0x0
3592 
#define                     TRS27  0x800      /* Mailbox 27 Transmit Request Set */
3593 
#define                    nTRS27  0x0
3594 
#define                     TRS28  0x1000     /* Mailbox 28 Transmit Request Set */
3595 
#define                    nTRS28  0x0
3596 
#define                     TRS29  0x2000     /* Mailbox 29 Transmit Request Set */
3597 
#define                    nTRS29  0x0
3598 
#define                     TRS30  0x4000     /* Mailbox 30 Transmit Request Set */
3599 
#define                    nTRS30  0x0
3600 
#define                     TRS31  0x8000     /* Mailbox 31 Transmit Request Set */
3601 
#define                    nTRS31  0x0
3602 
 
3603 
/* Bit masks for CAN0_TRR1 */
3604 
 
3605 
#define                      TRR0  0x1        /* Mailbox 0 Transmit Request Reset */
3606 
#define                     nTRR0  0x0
3607 
#define                      TRR1  0x2        /* Mailbox 1 Transmit Request Reset */
3608 
#define                     nTRR1  0x0
3609 
#define                      TRR2  0x4        /* Mailbox 2 Transmit Request Reset */
3610 
#define                     nTRR2  0x0
3611 
#define                      TRR3  0x8        /* Mailbox 3 Transmit Request Reset */
3612 
#define                     nTRR3  0x0
3613 
#define                      TRR4  0x10       /* Mailbox 4 Transmit Request Reset */
3614 
#define                     nTRR4  0x0
3615 
#define                      TRR5  0x20       /* Mailbox 5 Transmit Request Reset */
3616 
#define                     nTRR5  0x0
3617 
#define                      TRR6  0x40       /* Mailbox 6 Transmit Request Reset */
3618 
#define                     nTRR6  0x0
3619 
#define                      TRR7  0x80       /* Mailbox 7 Transmit Request Reset */
3620 
#define                     nTRR7  0x0
3621 
#define                      TRR8  0x100      /* Mailbox 8 Transmit Request Reset */
3622 
#define                     nTRR8  0x0
3623 
#define                      TRR9  0x200      /* Mailbox 9 Transmit Request Reset */
3624 
#define                     nTRR9  0x0
3625 
#define                     TRR10  0x400      /* Mailbox 10 Transmit Request Reset */
3626 
#define                    nTRR10  0x0
3627 
#define                     TRR11  0x800      /* Mailbox 11 Transmit Request Reset */
3628 
#define                    nTRR11  0x0
3629 
#define                     TRR12  0x1000     /* Mailbox 12 Transmit Request Reset */
3630 
#define                    nTRR12  0x0
3631 
#define                     TRR13  0x2000     /* Mailbox 13 Transmit Request Reset */
3632 
#define                    nTRR13  0x0
3633 
#define                     TRR14  0x4000     /* Mailbox 14 Transmit Request Reset */
3634 
#define                    nTRR14  0x0
3635 
#define                     TRR15  0x8000     /* Mailbox 15 Transmit Request Reset */
3636 
#define                    nTRR15  0x0
3637 
 
3638 
/* Bit masks for CAN0_TRR2 */
3639 
 
3640 
#define                     TRR16  0x1        /* Mailbox 16 Transmit Request Reset */
3641 
#define                    nTRR16  0x0
3642 
#define                     TRR17  0x2        /* Mailbox 17 Transmit Request Reset */
3643 
#define                    nTRR17  0x0
3644 
#define                     TRR18  0x4        /* Mailbox 18 Transmit Request Reset */
3645 
#define                    nTRR18  0x0
3646 
#define                     TRR19  0x8        /* Mailbox 19 Transmit Request Reset */
3647 
#define                    nTRR19  0x0
3648 
#define                     TRR20  0x10       /* Mailbox 20 Transmit Request Reset */
3649 
#define                    nTRR20  0x0
3650 
#define                     TRR21  0x20       /* Mailbox 21 Transmit Request Reset */
3651 
#define                    nTRR21  0x0
3652 
#define                     TRR22  0x40       /* Mailbox 22 Transmit Request Reset */
3653 
#define                    nTRR22  0x0
3654 
#define                     TRR23  0x80       /* Mailbox 23 Transmit Request Reset */
3655 
#define                    nTRR23  0x0
3656 
#define                     TRR24  0x100      /* Mailbox 24 Transmit Request Reset */
3657 
#define                    nTRR24  0x0
3658 
#define                     TRR25  0x200      /* Mailbox 25 Transmit Request Reset */
3659 
#define                    nTRR25  0x0
3660 
#define                     TRR26  0x400      /* Mailbox 26 Transmit Request Reset */
3661 
#define                    nTRR26  0x0
3662 
#define                     TRR27  0x800      /* Mailbox 27 Transmit Request Reset */
3663 
#define                    nTRR27  0x0
3664 
#define                     TRR28  0x1000     /* Mailbox 28 Transmit Request Reset */
3665 
#define                    nTRR28  0x0
3666 
#define                     TRR29  0x2000     /* Mailbox 29 Transmit Request Reset */
3667 
#define                    nTRR29  0x0
3668 
#define                     TRR30  0x4000     /* Mailbox 30 Transmit Request Reset */
3669 
#define                    nTRR30  0x0
3670 
#define                     TRR31  0x8000     /* Mailbox 31 Transmit Request Reset */
3671 
#define                    nTRR31  0x0
3672 
 
3673 
/* Bit masks for CAN0_AA1 */
3674 
 
3675 
#define                       AA0  0x1        /* Mailbox 0 Abort Acknowledge */
3676 
#define                      nAA0  0x0
3677 
#define                       AA1  0x2        /* Mailbox 1 Abort Acknowledge */
3678 
#define                      nAA1  0x0
3679 
#define                       AA2  0x4        /* Mailbox 2 Abort Acknowledge */
3680 
#define                      nAA2  0x0
3681 
#define                       AA3  0x8        /* Mailbox 3 Abort Acknowledge */
3682 
#define                      nAA3  0x0
3683 
#define                       AA4  0x10       /* Mailbox 4 Abort Acknowledge */
3684 
#define                      nAA4  0x0
3685 
#define                       AA5  0x20       /* Mailbox 5 Abort Acknowledge */
3686 
#define                      nAA5  0x0
3687 
#define                       AA6  0x40       /* Mailbox 6 Abort Acknowledge */
3688 
#define                      nAA6  0x0
3689 
#define                       AA7  0x80       /* Mailbox 7 Abort Acknowledge */
3690 
#define                      nAA7  0x0
3691 
#define                       AA8  0x100      /* Mailbox 8 Abort Acknowledge */
3692 
#define                      nAA8  0x0
3693 
#define                       AA9  0x200      /* Mailbox 9 Abort Acknowledge */
3694 
#define                      nAA9  0x0
3695 
#define                      AA10  0x400      /* Mailbox 10 Abort Acknowledge */
3696 
#define                     nAA10  0x0
3697 
#define                      AA11  0x800      /* Mailbox 11 Abort Acknowledge */
3698 
#define                     nAA11  0x0
3699 
#define                      AA12  0x1000     /* Mailbox 12 Abort Acknowledge */
3700 
#define                     nAA12  0x0
3701 
#define                      AA13  0x2000     /* Mailbox 13 Abort Acknowledge */
3702 
#define                     nAA13  0x0
3703 
#define                      AA14  0x4000     /* Mailbox 14 Abort Acknowledge */
3704 
#define                     nAA14  0x0
3705 
#define                      AA15  0x8000     /* Mailbox 15 Abort Acknowledge */
3706 
#define                     nAA15  0x0
3707 
 
3708 
/* Bit masks for CAN0_AA2 */
3709 
 
3710 
#define                      AA16  0x1        /* Mailbox 16 Abort Acknowledge */
3711 
#define                     nAA16  0x0
3712 
#define                      AA17  0x2        /* Mailbox 17 Abort Acknowledge */
3713 
#define                     nAA17  0x0
3714 
#define                      AA18  0x4        /* Mailbox 18 Abort Acknowledge */
3715 
#define                     nAA18  0x0
3716 
#define                      AA19  0x8        /* Mailbox 19 Abort Acknowledge */
3717 
#define                     nAA19  0x0
3718 
#define                      AA20  0x10       /* Mailbox 20 Abort Acknowledge */
3719 
#define                     nAA20  0x0
3720 
#define                      AA21  0x20       /* Mailbox 21 Abort Acknowledge */
3721 
#define                     nAA21  0x0
3722 
#define                      AA22  0x40       /* Mailbox 22 Abort Acknowledge */
3723 
#define                     nAA22  0x0
3724 
#define                      AA23  0x80       /* Mailbox 23 Abort Acknowledge */
3725 
#define                     nAA23  0x0
3726 
#define                      AA24  0x100      /* Mailbox 24 Abort Acknowledge */
3727 
#define                     nAA24  0x0
3728 
#define                      AA25  0x200      /* Mailbox 25 Abort Acknowledge */
3729 
#define                     nAA25  0x0
3730 
#define                      AA26  0x400      /* Mailbox 26 Abort Acknowledge */
3731 
#define                     nAA26  0x0
3732 
#define                      AA27  0x800      /* Mailbox 27 Abort Acknowledge */
3733 
#define                     nAA27  0x0
3734 
#define                      AA28  0x1000     /* Mailbox 28 Abort Acknowledge */
3735 
#define                     nAA28  0x0
3736 
#define                      AA29  0x2000     /* Mailbox 29 Abort Acknowledge */
3737 
#define                     nAA29  0x0
3738 
#define                      AA30  0x4000     /* Mailbox 30 Abort Acknowledge */
3739 
#define                     nAA30  0x0
3740 
#define                      AA31  0x8000     /* Mailbox 31 Abort Acknowledge */
3741 
#define                     nAA31  0x0
3742 
 
3743 
/* Bit masks for CAN0_TA1 */
3744 
 
3745 
#define                       TA0  0x1        /* Mailbox 0 Transmit Acknowledge */
3746 
#define                      nTA0  0x0
3747 
#define                       TA1  0x2        /* Mailbox 1 Transmit Acknowledge */
3748 
#define                      nTA1  0x0
3749 
#define                       TA2  0x4        /* Mailbox 2 Transmit Acknowledge */
3750 
#define                      nTA2  0x0
3751 
#define                       TA3  0x8        /* Mailbox 3 Transmit Acknowledge */
3752 
#define                      nTA3  0x0
3753 
#define                       TA4  0x10       /* Mailbox 4 Transmit Acknowledge */
3754 
#define                      nTA4  0x0
3755 
#define                       TA5  0x20       /* Mailbox 5 Transmit Acknowledge */
3756 
#define                      nTA5  0x0
3757 
#define                       TA6  0x40       /* Mailbox 6 Transmit Acknowledge */
3758 
#define                      nTA6  0x0
3759 
#define                       TA7  0x80       /* Mailbox 7 Transmit Acknowledge */
3760 
#define                      nTA7  0x0
3761 
#define                       TA8  0x100      /* Mailbox 8 Transmit Acknowledge */
3762 
#define                      nTA8  0x0
3763 
#define                       TA9  0x200      /* Mailbox 9 Transmit Acknowledge */
3764 
#define                      nTA9  0x0
3765 
#define                      TA10  0x400      /* Mailbox 10 Transmit Acknowledge */
3766 
#define                     nTA10  0x0
3767 
#define                      TA11  0x800      /* Mailbox 11 Transmit Acknowledge */
3768 
#define                     nTA11  0x0
3769 
#define                      TA12  0x1000     /* Mailbox 12 Transmit Acknowledge */
3770 
#define                     nTA12  0x0
3771 
#define                      TA13  0x2000     /* Mailbox 13 Transmit Acknowledge */
3772 
#define                     nTA13  0x0
3773 
#define                      TA14  0x4000     /* Mailbox 14 Transmit Acknowledge */
3774 
#define                     nTA14  0x0
3775 
#define                      TA15  0x8000     /* Mailbox 15 Transmit Acknowledge */
3776 
#define                     nTA15  0x0
3777 
 
3778 
/* Bit masks for CAN0_TA2 */
3779 
 
3780 
#define                      TA16  0x1        /* Mailbox 16 Transmit Acknowledge */
3781 
#define                     nTA16  0x0
3782 
#define                      TA17  0x2        /* Mailbox 17 Transmit Acknowledge */
3783 
#define                     nTA17  0x0
3784 
#define                      TA18  0x4        /* Mailbox 18 Transmit Acknowledge */
3785 
#define                     nTA18  0x0
3786 
#define                      TA19  0x8        /* Mailbox 19 Transmit Acknowledge */
3787 
#define                     nTA19  0x0
3788 
#define                      TA20  0x10       /* Mailbox 20 Transmit Acknowledge */
3789 
#define                     nTA20  0x0
3790 
#define                      TA21  0x20       /* Mailbox 21 Transmit Acknowledge */
3791 
#define                     nTA21  0x0
3792 
#define                      TA22  0x40       /* Mailbox 22 Transmit Acknowledge */
3793 
#define                     nTA22  0x0
3794 
#define                      TA23  0x80       /* Mailbox 23 Transmit Acknowledge */
3795 
#define                     nTA23  0x0
3796 
#define                      TA24  0x100      /* Mailbox 24 Transmit Acknowledge */
3797 
#define                     nTA24  0x0
3798 
#define                      TA25  0x200      /* Mailbox 25 Transmit Acknowledge */
3799 
#define                     nTA25  0x0
3800 
#define                      TA26  0x400      /* Mailbox 26 Transmit Acknowledge */
3801 
#define                     nTA26  0x0
3802 
#define                      TA27  0x800      /* Mailbox 27 Transmit Acknowledge */
3803 
#define                     nTA27  0x0
3804 
#define                      TA28  0x1000     /* Mailbox 28 Transmit Acknowledge */
3805 
#define                     nTA28  0x0
3806 
#define                      TA29  0x2000     /* Mailbox 29 Transmit Acknowledge */
3807 
#define                     nTA29  0x0
3808 
#define                      TA30  0x4000     /* Mailbox 30 Transmit Acknowledge */
3809 
#define                     nTA30  0x0
3810 
#define                      TA31  0x8000     /* Mailbox 31 Transmit Acknowledge */
3811 
#define                     nTA31  0x0
3812 
 
3813 
/* Bit masks for CAN0_RFH1 */
3814 
 
3815 
#define                      RFH0  0x1        /* Mailbox 0 Remote Frame Handling Enable */
3816 
#define                     nRFH0  0x0
3817 
#define                      RFH1  0x2        /* Mailbox 1 Remote Frame Handling Enable */
3818 
#define                     nRFH1  0x0
3819 
#define                      RFH2  0x4        /* Mailbox 2 Remote Frame Handling Enable */
3820 
#define                     nRFH2  0x0
3821 
#define                      RFH3  0x8        /* Mailbox 3 Remote Frame Handling Enable */
3822 
#define                     nRFH3  0x0
3823 
#define                      RFH4  0x10       /* Mailbox 4 Remote Frame Handling Enable */
3824 
#define                     nRFH4  0x0
3825 
#define                      RFH5  0x20       /* Mailbox 5 Remote Frame Handling Enable */
3826 
#define                     nRFH5  0x0
3827 
#define                      RFH6  0x40       /* Mailbox 6 Remote Frame Handling Enable */
3828 
#define                     nRFH6  0x0
3829 
#define                      RFH7  0x80       /* Mailbox 7 Remote Frame Handling Enable */
3830 
#define                     nRFH7  0x0
3831 
#define                      RFH8  0x100      /* Mailbox 8 Remote Frame Handling Enable */
3832 
#define                     nRFH8  0x0
3833 
#define                      RFH9  0x200      /* Mailbox 9 Remote Frame Handling Enable */
3834 
#define                     nRFH9  0x0
3835 
#define                     RFH10  0x400      /* Mailbox 10 Remote Frame Handling Enable */
3836 
#define                    nRFH10  0x0
3837 
#define                     RFH11  0x800      /* Mailbox 11 Remote Frame Handling Enable */
3838 
#define                    nRFH11  0x0
3839 
#define                     RFH12  0x1000     /* Mailbox 12 Remote Frame Handling Enable */
3840 
#define                    nRFH12  0x0
3841 
#define                     RFH13  0x2000     /* Mailbox 13 Remote Frame Handling Enable */
3842 
#define                    nRFH13  0x0
3843 
#define                     RFH14  0x4000     /* Mailbox 14 Remote Frame Handling Enable */
3844 
#define                    nRFH14  0x0
3845 
#define                     RFH15  0x8000     /* Mailbox 15 Remote Frame Handling Enable */
3846 
#define                    nRFH15  0x0
3847 
 
3848 
/* Bit masks for CAN0_RFH2 */
3849 
 
3850 
#define                     RFH16  0x1        /* Mailbox 16 Remote Frame Handling Enable */
3851 
#define                    nRFH16  0x0
3852 
#define                     RFH17  0x2        /* Mailbox 17 Remote Frame Handling Enable */
3853 
#define                    nRFH17  0x0
3854 
#define                     RFH18  0x4        /* Mailbox 18 Remote Frame Handling Enable */
3855 
#define                    nRFH18  0x0
3856 
#define                     RFH19  0x8        /* Mailbox 19 Remote Frame Handling Enable */
3857 
#define                    nRFH19  0x0
3858 
#define                     RFH20  0x10       /* Mailbox 20 Remote Frame Handling Enable */
3859 
#define                    nRFH20  0x0
3860 
#define                     RFH21  0x20       /* Mailbox 21 Remote Frame Handling Enable */
3861 
#define                    nRFH21  0x0
3862 
#define                     RFH22  0x40       /* Mailbox 22 Remote Frame Handling Enable */
3863 
#define                    nRFH22  0x0
3864 
#define                     RFH23  0x80       /* Mailbox 23 Remote Frame Handling Enable */
3865 
#define                    nRFH23  0x0
3866 
#define                     RFH24  0x100      /* Mailbox 24 Remote Frame Handling Enable */
3867 
#define                    nRFH24  0x0
3868 
#define                     RFH25  0x200      /* Mailbox 25 Remote Frame Handling Enable */
3869 
#define                    nRFH25  0x0
3870 
#define                     RFH26  0x400      /* Mailbox 26 Remote Frame Handling Enable */
3871 
#define                    nRFH26  0x0
3872 
#define                     RFH27  0x800      /* Mailbox 27 Remote Frame Handling Enable */
3873 
#define                    nRFH27  0x0
3874 
#define                     RFH28  0x1000     /* Mailbox 28 Remote Frame Handling Enable */
3875 
#define                    nRFH28  0x0
3876 
#define                     RFH29  0x2000     /* Mailbox 29 Remote Frame Handling Enable */
3877 
#define                    nRFH29  0x0
3878 
#define                     RFH30  0x4000     /* Mailbox 30 Remote Frame Handling Enable */
3879 
#define                    nRFH30  0x0
3880 
#define                     RFH31  0x8000     /* Mailbox 31 Remote Frame Handling Enable */
3881 
#define                    nRFH31  0x0
3882 
 
3883 
/* Bit masks for CAN0_MBIM1 */
3884 
 
3885 
#define                     MBIM0  0x1        /* Mailbox 0 Mailbox Interrupt Mask */
3886 
#define                    nMBIM0  0x0
3887 
#define                     MBIM1  0x2        /* Mailbox 1 Mailbox Interrupt Mask */
3888 
#define                    nMBIM1  0x0
3889 
#define                     MBIM2  0x4        /* Mailbox 2 Mailbox Interrupt Mask */
3890 
#define                    nMBIM2  0x0
3891 
#define                     MBIM3  0x8        /* Mailbox 3 Mailbox Interrupt Mask */
3892 
#define                    nMBIM3  0x0
3893 
#define                     MBIM4  0x10       /* Mailbox 4 Mailbox Interrupt Mask */
3894 
#define                    nMBIM4  0x0
3895 
#define                     MBIM5  0x20       /* Mailbox 5 Mailbox Interrupt Mask */
3896 
#define                    nMBIM5  0x0
3897 
#define                     MBIM6  0x40       /* Mailbox 6 Mailbox Interrupt Mask */
3898 
#define                    nMBIM6  0x0
3899 
#define                     MBIM7  0x80       /* Mailbox 7 Mailbox Interrupt Mask */
3900 
#define                    nMBIM7  0x0
3901 
#define                     MBIM8  0x100      /* Mailbox 8 Mailbox Interrupt Mask */
3902 
#define                    nMBIM8  0x0
3903 
#define                     MBIM9  0x200      /* Mailbox 9 Mailbox Interrupt Mask */
3904 
#define                    nMBIM9  0x0
3905 
#define                    MBIM10  0x400      /* Mailbox 10 Mailbox Interrupt Mask */
3906 
#define                   nMBIM10  0x0
3907 
#define                    MBIM11  0x800      /* Mailbox 11 Mailbox Interrupt Mask */
3908 
#define                   nMBIM11  0x0
3909 
#define                    MBIM12  0x1000     /* Mailbox 12 Mailbox Interrupt Mask */
3910 
#define                   nMBIM12  0x0
3911 
#define                    MBIM13  0x2000     /* Mailbox 13 Mailbox Interrupt Mask */
3912 
#define                   nMBIM13  0x0
3913 
#define                    MBIM14  0x4000     /* Mailbox 14 Mailbox Interrupt Mask */
3914 
#define                   nMBIM14  0x0
3915 
#define                    MBIM15  0x8000     /* Mailbox 15 Mailbox Interrupt Mask */
3916 
#define                   nMBIM15  0x0
3917 
 
3918 
/* Bit masks for CAN0_MBIM2 */
3919 
 
3920 
#define                    MBIM16  0x1        /* Mailbox 16 Mailbox Interrupt Mask */
3921 
#define                   nMBIM16  0x0
3922 
#define                    MBIM17  0x2        /* Mailbox 17 Mailbox Interrupt Mask */
3923 
#define                   nMBIM17  0x0
3924 
#define                    MBIM18  0x4        /* Mailbox 18 Mailbox Interrupt Mask */
3925 
#define                   nMBIM18  0x0
3926 
#define                    MBIM19  0x8        /* Mailbox 19 Mailbox Interrupt Mask */
3927 
#define                   nMBIM19  0x0
3928 
#define                    MBIM20  0x10       /* Mailbox 20 Mailbox Interrupt Mask */
3929 
#define                   nMBIM20  0x0
3930 
#define                    MBIM21  0x20       /* Mailbox 21 Mailbox Interrupt Mask */
3931 
#define                   nMBIM21  0x0
3932 
#define                    MBIM22  0x40       /* Mailbox 22 Mailbox Interrupt Mask */
3933 
#define                   nMBIM22  0x0
3934 
#define                    MBIM23  0x80       /* Mailbox 23 Mailbox Interrupt Mask */
3935 
#define                   nMBIM23  0x0
3936 
#define                    MBIM24  0x100      /* Mailbox 24 Mailbox Interrupt Mask */
3937 
#define                   nMBIM24  0x0
3938 
#define                    MBIM25  0x200      /* Mailbox 25 Mailbox Interrupt Mask */
3939 
#define                   nMBIM25  0x0
3940 
#define                    MBIM26  0x400      /* Mailbox 26 Mailbox Interrupt Mask */
3941 
#define                   nMBIM26  0x0
3942 
#define                    MBIM27  0x800      /* Mailbox 27 Mailbox Interrupt Mask */
3943 
#define                   nMBIM27  0x0
3944 
#define                    MBIM28  0x1000     /* Mailbox 28 Mailbox Interrupt Mask */
3945 
#define                   nMBIM28  0x0
3946 
#define                    MBIM29  0x2000     /* Mailbox 29 Mailbox Interrupt Mask */
3947 
#define                   nMBIM29  0x0
3948 
#define                    MBIM30  0x4000     /* Mailbox 30 Mailbox Interrupt Mask */
3949 
#define                   nMBIM30  0x0
3950 
#define                    MBIM31  0x8000     /* Mailbox 31 Mailbox Interrupt Mask */
3951 
#define                   nMBIM31  0x0
3952 
 
3953 
/* Bit masks for CAN0_MBTIF1 */
3954 
 
3955 
#define                    MBTIF0  0x1        /* Mailbox 0 Mailbox Transmit Interrupt Flag */
3956 
#define                   nMBTIF0  0x0
3957 
#define                    MBTIF1  0x2        /* Mailbox 1 Mailbox Transmit Interrupt Flag */
3958 
#define                   nMBTIF1  0x0
3959 
#define                    MBTIF2  0x4        /* Mailbox 2 Mailbox Transmit Interrupt Flag */
3960 
#define                   nMBTIF2  0x0
3961 
#define                    MBTIF3  0x8        /* Mailbox 3 Mailbox Transmit Interrupt Flag */
3962 
#define                   nMBTIF3  0x0
3963 
#define                    MBTIF4  0x10       /* Mailbox 4 Mailbox Transmit Interrupt Flag */
3964 
#define                   nMBTIF4  0x0
3965 
#define                    MBTIF5  0x20       /* Mailbox 5 Mailbox Transmit Interrupt Flag */
3966 
#define                   nMBTIF5  0x0
3967 
#define                    MBTIF6  0x40       /* Mailbox 6 Mailbox Transmit Interrupt Flag */
3968 
#define                   nMBTIF6  0x0
3969 
#define                    MBTIF7  0x80       /* Mailbox 7 Mailbox Transmit Interrupt Flag */
3970 
#define                   nMBTIF7  0x0
3971 
#define                    MBTIF8  0x100      /* Mailbox 8 Mailbox Transmit Interrupt Flag */
3972 
#define                   nMBTIF8  0x0
3973 
#define                    MBTIF9  0x200      /* Mailbox 9 Mailbox Transmit Interrupt Flag */
3974 
#define                   nMBTIF9  0x0
3975 
#define                   MBTIF10  0x400      /* Mailbox 10 Mailbox Transmit Interrupt Flag */
3976 
#define                  nMBTIF10  0x0
3977 
#define                   MBTIF11  0x800      /* Mailbox 11 Mailbox Transmit Interrupt Flag */
3978 
#define                  nMBTIF11  0x0
3979 
#define                   MBTIF12  0x1000     /* Mailbox 12 Mailbox Transmit Interrupt Flag */
3980 
#define                  nMBTIF12  0x0
3981 
#define                   MBTIF13  0x2000     /* Mailbox 13 Mailbox Transmit Interrupt Flag */
3982 
#define                  nMBTIF13  0x0
3983 
#define                   MBTIF14  0x4000     /* Mailbox 14 Mailbox Transmit Interrupt Flag */
3984 
#define                  nMBTIF14  0x0
3985 
#define                   MBTIF15  0x8000     /* Mailbox 15 Mailbox Transmit Interrupt Flag */
3986 
#define                  nMBTIF15  0x0
3987 
 
3988 
/* Bit masks for CAN0_MBTIF2 */
3989 
 
3990 
#define                   MBTIF16  0x1        /* Mailbox 16 Mailbox Transmit Interrupt Flag */
3991 
#define                  nMBTIF16  0x0
3992 
#define                   MBTIF17  0x2        /* Mailbox 17 Mailbox Transmit Interrupt Flag */
3993 
#define                  nMBTIF17  0x0
3994 
#define                   MBTIF18  0x4        /* Mailbox 18 Mailbox Transmit Interrupt Flag */
3995 
#define                  nMBTIF18  0x0
3996 
#define                   MBTIF19  0x8        /* Mailbox 19 Mailbox Transmit Interrupt Flag */
3997 
#define                  nMBTIF19  0x0
3998 
#define                   MBTIF20  0x10       /* Mailbox 20 Mailbox Transmit Interrupt Flag */
3999 
#define                  nMBTIF20  0x0
4000 
#define                   MBTIF21  0x20       /* Mailbox 21 Mailbox Transmit Interrupt Flag */
4001 
#define                  nMBTIF21  0x0
4002 
#define                   MBTIF22  0x40       /* Mailbox 22 Mailbox Transmit Interrupt Flag */
4003 
#define                  nMBTIF22  0x0
4004 
#define                   MBTIF23  0x80       /* Mailbox 23 Mailbox Transmit Interrupt Flag */
4005 
#define                  nMBTIF23  0x0
4006 
#define                   MBTIF24  0x100      /* Mailbox 24 Mailbox Transmit Interrupt Flag */
4007 
#define                  nMBTIF24  0x0
4008 
#define                   MBTIF25  0x200      /* Mailbox 25 Mailbox Transmit Interrupt Flag */
4009 
#define                  nMBTIF25  0x0
4010 
#define                   MBTIF26  0x400      /* Mailbox 26 Mailbox Transmit Interrupt Flag */
4011 
#define                  nMBTIF26  0x0
4012 
#define                   MBTIF27  0x800      /* Mailbox 27 Mailbox Transmit Interrupt Flag */
4013 
#define                  nMBTIF27  0x0
4014 
#define                   MBTIF28  0x1000     /* Mailbox 28 Mailbox Transmit Interrupt Flag */
4015 
#define                  nMBTIF28  0x0
4016 
#define                   MBTIF29  0x2000     /* Mailbox 29 Mailbox Transmit Interrupt Flag */
4017 
#define                  nMBTIF29  0x0
4018 
#define                   MBTIF30  0x4000     /* Mailbox 30 Mailbox Transmit Interrupt Flag */
4019 
#define                  nMBTIF30  0x0
4020 
#define                   MBTIF31  0x8000     /* Mailbox 31 Mailbox Transmit Interrupt Flag */
4021 
#define                  nMBTIF31  0x0
4022 
 
4023 
/* Bit masks for CAN0_MBRIF1 */
4024 
 
4025 
#define                    MBRIF0  0x1        /* Mailbox 0 Mailbox Receive Interrupt Flag */
4026 
#define                   nMBRIF0  0x0
4027 
#define                    MBRIF1  0x2        /* Mailbox 1 Mailbox Receive Interrupt Flag */
4028 
#define                   nMBRIF1  0x0
4029 
#define                    MBRIF2  0x4        /* Mailbox 2 Mailbox Receive Interrupt Flag */
4030 
#define                   nMBRIF2  0x0
4031 
#define                    MBRIF3  0x8        /* Mailbox 3 Mailbox Receive Interrupt Flag */
4032 
#define                   nMBRIF3  0x0
4033 
#define                    MBRIF4  0x10       /* Mailbox 4 Mailbox Receive Interrupt Flag */
4034 
#define                   nMBRIF4  0x0
4035 
#define                    MBRIF5  0x20       /* Mailbox 5 Mailbox Receive Interrupt Flag */
4036 
#define                   nMBRIF5  0x0
4037 
#define                    MBRIF6  0x40       /* Mailbox 6 Mailbox Receive Interrupt Flag */
4038 
#define                   nMBRIF6  0x0
4039 
#define                    MBRIF7  0x80       /* Mailbox 7 Mailbox Receive Interrupt Flag */
4040 
#define                   nMBRIF7  0x0
4041 
#define                    MBRIF8  0x100      /* Mailbox 8 Mailbox Receive Interrupt Flag */
4042 
#define                   nMBRIF8  0x0
4043 
#define                    MBRIF9  0x200      /* Mailbox 9 Mailbox Receive Interrupt Flag */
4044 
#define                   nMBRIF9  0x0
4045 
#define                   MBRIF10  0x400      /* Mailbox 10 Mailbox Receive Interrupt Flag */
4046 
#define                  nMBRIF10  0x0
4047 
#define                   MBRIF11  0x800      /* Mailbox 11 Mailbox Receive Interrupt Flag */
4048 
#define                  nMBRIF11  0x0
4049 
#define                   MBRIF12  0x1000     /* Mailbox 12 Mailbox Receive Interrupt Flag */
4050 
#define                  nMBRIF12  0x0
4051 
#define                   MBRIF13  0x2000     /* Mailbox 13 Mailbox Receive Interrupt Flag */
4052 
#define                  nMBRIF13  0x0
4053 
#define                   MBRIF14  0x4000     /* Mailbox 14 Mailbox Receive Interrupt Flag */
4054 
#define                  nMBRIF14  0x0
4055 
#define                   MBRIF15  0x8000     /* Mailbox 15 Mailbox Receive Interrupt Flag */
4056 
#define                  nMBRIF15  0x0
4057 
 
4058 
/* Bit masks for CAN0_MBRIF2 */
4059 
 
4060 
#define                   MBRIF16  0x1        /* Mailbox 16 Mailbox Receive Interrupt Flag */
4061 
#define                  nMBRIF16  0x0
4062 
#define                   MBRIF17  0x2        /* Mailbox 17 Mailbox Receive Interrupt Flag */
4063 
#define                  nMBRIF17  0x0
4064 
#define                   MBRIF18  0x4        /* Mailbox 18 Mailbox Receive Interrupt Flag */
4065 
#define                  nMBRIF18  0x0
4066 
#define                   MBRIF19  0x8        /* Mailbox 19 Mailbox Receive Interrupt Flag */
4067 
#define                  nMBRIF19  0x0
4068 
#define                   MBRIF20  0x10       /* Mailbox 20 Mailbox Receive Interrupt Flag */
4069 
#define                  nMBRIF20  0x0
4070 
#define                   MBRIF21  0x20       /* Mailbox 21 Mailbox Receive Interrupt Flag */
4071 
#define                  nMBRIF21  0x0
4072 
#define                   MBRIF22  0x40       /* Mailbox 22 Mailbox Receive Interrupt Flag */
4073 
#define                  nMBRIF22  0x0
4074 
#define                   MBRIF23  0x80       /* Mailbox 23 Mailbox Receive Interrupt Flag */
4075 
#define                  nMBRIF23  0x0
4076 
#define                   MBRIF24  0x100      /* Mailbox 24 Mailbox Receive Interrupt Flag */
4077 
#define                  nMBRIF24  0x0
4078 
#define                   MBRIF25  0x200      /* Mailbox 25 Mailbox Receive Interrupt Flag */
4079 
#define                  nMBRIF25  0x0
4080 
#define                   MBRIF26  0x400      /* Mailbox 26 Mailbox Receive Interrupt Flag */
4081 
#define                  nMBRIF26  0x0
4082 
#define                   MBRIF27  0x800      /* Mailbox 27 Mailbox Receive Interrupt Flag */
4083 
#define                  nMBRIF27  0x0
4084 
#define                   MBRIF28  0x1000     /* Mailbox 28 Mailbox Receive Interrupt Flag */
4085 
#define                  nMBRIF28  0x0
4086 
#define                   MBRIF29  0x2000     /* Mailbox 29 Mailbox Receive Interrupt Flag */
4087 
#define                  nMBRIF29  0x0
4088 
#define                   MBRIF30  0x4000     /* Mailbox 30 Mailbox Receive Interrupt Flag */
4089 
#define                  nMBRIF30  0x0
4090 
#define                   MBRIF31  0x8000     /* Mailbox 31 Mailbox Receive Interrupt Flag */
4091 
#define                  nMBRIF31  0x0
4092 
 
4093 
/* Bit masks for EPPIx_STATUS */
4094 
 
4095 
#define                 CFIFO_ERR  0x1        /* Chroma FIFO Error */
4096 
#define                nCFIFO_ERR  0x0
4097 
#define                 YFIFO_ERR  0x2        /* Luma FIFO Error */
4098 
#define                nYFIFO_ERR  0x0
4099 
#define                 LTERR_OVR  0x4        /* Line Track Overflow */
4100 
#define                nLTERR_OVR  0x0
4101 
#define                LTERR_UNDR  0x8        /* Line Track Underflow */
4102 
#define               nLTERR_UNDR  0x0
4103 
#define                 FTERR_OVR  0x10       /* Frame Track Overflow */
4104 
#define                nFTERR_OVR  0x0
4105 
#define                FTERR_UNDR  0x20       /* Frame Track Underflow */
4106 
#define               nFTERR_UNDR  0x0
4107 
#define                  ERR_NCOR  0x40       /* Preamble Error Not Corrected */
4108 
#define                 nERR_NCOR  0x0
4109 
#define                   DMA1URQ  0x80       /* DMA1 Urgent Request */
4110 
#define                  nDMA1URQ  0x0
4111 
#define                   DMA0URQ  0x100      /* DMA0 Urgent Request */
4112 
#define                  nDMA0URQ  0x0
4113 
#define                   ERR_DET  0x4000     /* Preamble Error Detected */
4114 
#define                  nERR_DET  0x0
4115 
#define                       FLD  0x8000     /* Field */
4116 
#define                      nFLD  0x0
4117 
 
4118 
/* Bit masks for EPPIx_CONTROL */
4119 
 
4120 
#define                   EPPI_EN  0x1        /* Enable */
4121 
#define                  nEPPI_EN  0x0
4122 
#define                  EPPI_DIR  0x2        /* Direction */
4123 
#define                 nEPPI_DIR  0x0
4124 
#define                  XFR_TYPE  0xc        /* Operating Mode */
4125 
#define                    FS_CFG  0x30       /* Frame Sync Configuration */
4126 
#define                   FLD_SEL  0x40       /* Field Select/Trigger */
4127 
#define                  nFLD_SEL  0x0
4128 
#define                  ITU_TYPE  0x80       /* ITU Interlaced or Progressive */
4129 
#define                 nITU_TYPE  0x0
4130 
#define                  BLANKGEN  0x100      /* ITU Output Mode with Internal Blanking Generation */
4131 
#define                 nBLANKGEN  0x0
4132 
#define                   ICLKGEN  0x200      /* Internal Clock Generation */
4133 
#define                  nICLKGEN  0x0
4134 
#define                    IFSGEN  0x400      /* Internal Frame Sync Generation */
4135 
#define                   nIFSGEN  0x0
4136 
#define                      POLC  0x1800     /* Frame Sync and Data Driving/Sampling Edges */
4137 
#define                      POLS  0x6000     /* Frame Sync Polarity */
4138 
#define                      DLEN  0x38000    /* Data Length */
4139 
#define                   SKIP_EN  0x40000    /* Skip Enable */
4140 
#define                  nSKIP_EN  0x0
4141 
#define                   SKIP_EO  0x80000    /* Skip Even or Odd */
4142 
#define                  nSKIP_EO  0x0
4143 
#define                    PACKEN  0x100000   /* Packing/Unpacking Enable */
4144 
#define                   nPACKEN  0x0
4145 
#define                    SWAPEN  0x200000   /* Swap Enable */
4146 
#define                   nSWAPEN  0x0
4147 
#define                  SIGN_EXT  0x400000   /* Sign Extension or Zero-filled / Data Split Format */
4148 
#define                 nSIGN_EXT  0x0
4149 
#define             SPLT_EVEN_ODD  0x800000   /* Split Even and Odd Data Samples */
4150 
#define            nSPLT_EVEN_ODD  0x0
4151 
#define               SUBSPLT_ODD  0x1000000  /* Sub-split Odd Samples */
4152 
#define              nSUBSPLT_ODD  0x0
4153 
#define                    DMACFG  0x2000000  /* One or Two DMA Channels Mode */
4154 
#define                   nDMACFG  0x0
4155 
#define                RGB_FMT_EN  0x4000000  /* RGB Formatting Enable */
4156 
#define               nRGB_FMT_EN  0x0
4157 
#define                  FIFO_RWM  0x18000000 /* FIFO Regular Watermarks */
4158 
#define                  FIFO_UWM  0x60000000 /* FIFO Urgent Watermarks */
4159 
 
4160 
/* Bit masks for EPPIx_FS2W_LVB */
4161 
 
4162 
#define                   F1VB_BD  0xff       /* Vertical Blanking before Field 1 Active Data */
4163 
#define                   F1VB_AD  0xff00     /* Vertical Blanking after Field 1 Active Data */
4164 
#define                   F2VB_BD  0xff0000   /* Vertical Blanking before Field 2 Active Data */
4165 
#define                   F2VB_AD  0xff000000 /* Vertical Blanking after Field 2 Active Data */
4166 
 
4167 
/* Bit masks for EPPIx_FS2W_LAVF */
4168 
 
4169 
#define                    F1_ACT  0xffff     /* Number of Lines of Active Data in Field 1 */
4170 
#define                    F2_ACT  0xffff0000 /* Number of Lines of Active Data in Field 2 */
4171 
 
4172 
/* Bit masks for EPPIx_CLIP */
4173 
 
4174 
#define                   LOW_ODD  0xff       /* Lower Limit for Odd Bytes (Chroma) */
4175 
#define                  HIGH_ODD  0xff00     /* Upper Limit for Odd Bytes (Chroma) */
4176 
#define                  LOW_EVEN  0xff0000   /* Lower Limit for Even Bytes (Luma) */
4177 
#define                 HIGH_EVEN  0xff000000 /* Upper Limit for Even Bytes (Luma) */
4178 
 
4179 
/* Bit masks for SPIx_BAUD */
4180 
 
4181 
#define                  SPI_BAUD  0xffff     /* Baud Rate */
4182 
 
4183 
/* Bit masks for SPIx_CTL */
4184 
 
4185 
#define                       SPE  0x4000     /* SPI Enable */
4186 
#define                      nSPE  0x0
4187 
#define                       WOM  0x2000     /* Write Open Drain Master */
4188 
#define                      nWOM  0x0
4189 
#define                      MSTR  0x1000     /* Master Mode */
4190 
#define                     nMSTR  0x0
4191 
#define                      CPOL  0x800      /* Clock Polarity */
4192 
#define                     nCPOL  0x0
4193 
#define                      CPHA  0x400      /* Clock Phase */
4194 
#define                     nCPHA  0x0
4195 
#define                      LSBF  0x200      /* LSB First */
4196 
#define                     nLSBF  0x0
4197 
#define                      SIZE  0x100      /* Size of Words */
4198 
#define                     nSIZE  0x0
4199 
#define                     EMISO  0x20       /* Enable MISO Output */
4200 
#define                    nEMISO  0x0
4201 
#define                      PSSE  0x10       /* Slave-Select Enable */
4202 
#define                     nPSSE  0x0
4203 
#define                        GM  0x8        /* Get More Data */
4204 
#define                       nGM  0x0
4205 
#define                        SZ  0x4        /* Send Zero */
4206 
#define                       nSZ  0x0
4207 
#define                     TIMOD  0x3        /* Transfer Initiation Mode */
4208 
 
4209 
/* Bit masks for SPIx_FLG */
4210 
 
4211 
#define                      FLS1  0x2        /* Slave Select Enable 1 */
4212 
#define                     nFLS1  0x0
4213 
#define                      FLS2  0x4        /* Slave Select Enable 2 */
4214 
#define                     nFLS2  0x0
4215 
#define                      FLS3  0x8        /* Slave Select Enable 3 */
4216 
#define                     nFLS3  0x0
4217 
#define                      FLG1  0x200      /* Slave Select Value 1 */
4218 
#define                     nFLG1  0x0
4219 
#define                      FLG2  0x400      /* Slave Select Value 2 */
4220 
#define                     nFLG2  0x0
4221 
#define                      FLG3  0x800      /* Slave Select Value 3 */
4222 
#define                     nFLG3  0x0
4223 
 
4224 
/* Bit masks for SPIx_STAT */
4225 
 
4226 
#define                     TXCOL  0x40       /* Transmit Collision Error */
4227 
#define                    nTXCOL  0x0
4228 
#define                       RXS  0x20       /* RDBR Data Buffer Status */
4229 
#define                      nRXS  0x0
4230 
#define                      RBSY  0x10       /* Receive Error */
4231 
#define                     nRBSY  0x0
4232 
#define                       TXS  0x8        /* TDBR Data Buffer Status */
4233 
#define                      nTXS  0x0
4234 
#define                       TXE  0x4        /* Transmission Error */
4235 
#define                      nTXE  0x0
4236 
#define                      MODF  0x2        /* Mode Fault Error */
4237 
#define                     nMODF  0x0
4238 
#define                      SPIF  0x1        /* SPI Finished */
4239 
#define                     nSPIF  0x0
4240 
 
4241 
/* Bit masks for SPIx_TDBR */
4242 
 
4243 
#define                      TDBR  0xffff     /* Transmit Data Buffer */
4244 
 
4245 
/* Bit masks for SPIx_RDBR */
4246 
 
4247 
#define                      RDBR  0xffff     /* Receive Data Buffer */
4248 
 
4249 
/* Bit masks for SPIx_SHADOW */
4250 
 
4251 
#define                    SHADOW  0xffff     /* RDBR Shadow */
4252 
 
4253 
/* ************************************************ */
4254 
/* The TWI bit masks fields are from the ADSP-BF538 */
4255 
/* and they have not been verified as the final     */
4256 
/* ones for the Moab processors ... bz 1/19/2007    */
4257 
/* ************************************************ */
4258 
 
4259 
/* Bit masks for TWIx_CONTROL */
4260 
 
4261 
#define                  PRESCALE  0x7f       /* Prescale Value */
4262 
#define                   TWI_ENA  0x80       /* TWI Enable */
4263 
#define                  nTWI_ENA  0x0
4264 
#define                      SCCB  0x200      /* Serial Camera Control Bus */
4265 
#define                     nSCCB  0x0
4266 
 
4267 
/* Bit maskes for TWIx_CLKDIV */
4268 
 
4269 
#define                    CLKLOW  0xff       /* Clock Low */
4270 
#define                     CLKHI  0xff00     /* Clock High */
4271 
 
4272 
/* Bit maskes for TWIx_SLAVE_CTL */
4273 
 
4274 
#define                       SEN  0x1        /* Slave Enable */
4275 
#define                      nSEN  0x0
4276 
#define                    STDVAL  0x4        /* Slave Transmit Data Valid */
4277 
#define                   nSTDVAL  0x0
4278 
#define                       NAK  0x8        /* Not Acknowledge */
4279 
#define                      nNAK  0x0
4280 
#define                       GEN  0x10       /* General Call Enable */
4281 
#define                      nGEN  0x0
4282 
 
4283 
/* Bit maskes for TWIx_SLAVE_ADDR */
4284 
 
4285 
#define                     SADDR  0x7f       /* Slave Mode Address */
4286 
 
4287 
/* Bit maskes for TWIx_SLAVE_STAT */
4288 
 
4289 
#define                      SDIR  0x1        /* Slave Transfer Direction */
4290 
#define                     nSDIR  0x0
4291 
#define                     GCALL  0x2        /* General Call */
4292 
#define                    nGCALL  0x0
4293 
 
4294 
/* Bit maskes for TWIx_MASTER_CTL */
4295 
 
4296 
#define                       MEN  0x1        /* Master Mode Enable */
4297 
#define                      nMEN  0x0
4298 
#define                      MDIR  0x4        /* Master Transfer Direction */
4299 
#define                     nMDIR  0x0
4300 
#define                      FAST  0x8        /* Fast Mode */
4301 
#define                     nFAST  0x0
4302 
#define                      STOP  0x10       /* Issue Stop Condition */
4303 
#define                     nSTOP  0x0
4304 
#define                    RSTART  0x20       /* Repeat Start */
4305 
#define                   nRSTART  0x0
4306 
#define                      DCNT  0x3fc0     /* Data Transfer Count */
4307 
#define                    SDAOVR  0x4000     /* Serial Data Override */
4308 
#define                   nSDAOVR  0x0
4309 
#define                    SCLOVR  0x8000     /* Serial Clock Override */
4310 
#define                   nSCLOVR  0x0
4311 
 
4312 
/* Bit maskes for TWIx_MASTER_ADDR */
4313 
 
4314 
#define                     MADDR  0x7f       /* Master Mode Address */
4315 
 
4316 
/* Bit maskes for TWIx_MASTER_STAT */
4317 
 
4318 
#define                     MPROG  0x1        /* Master Transfer in Progress */
4319 
#define                    nMPROG  0x0
4320 
#define                   LOSTARB  0x2        /* Lost Arbitration */
4321 
#define                  nLOSTARB  0x0
4322 
#define                      ANAK  0x4        /* Address Not Acknowledged */
4323 
#define                     nANAK  0x0
4324 
#define                      DNAK  0x8        /* Data Not Acknowledged */
4325 
#define                     nDNAK  0x0
4326 
#define                  BUFRDERR  0x10       /* Buffer Read Error */
4327 
#define                 nBUFRDERR  0x0
4328 
#define                  BUFWRERR  0x20       /* Buffer Write Error */
4329 
#define                 nBUFWRERR  0x0
4330 
#define                    SDASEN  0x40       /* Serial Data Sense */
4331 
#define                   nSDASEN  0x0
4332 
#define                    SCLSEN  0x80       /* Serial Clock Sense */
4333 
#define                   nSCLSEN  0x0
4334 
#define                   BUSBUSY  0x100      /* Bus Busy */
4335 
#define                  nBUSBUSY  0x0
4336 
 
4337 
/* Bit maskes for TWIx_FIFO_CTL */
4338 
 
4339 
#define                  XMTFLUSH  0x1        /* Transmit Buffer Flush */
4340 
#define                 nXMTFLUSH  0x0
4341 
#define                  RCVFLUSH  0x2        /* Receive Buffer Flush */
4342 
#define                 nRCVFLUSH  0x0
4343 
#define                 XMTINTLEN  0x4        /* Transmit Buffer Interrupt Length */
4344 
#define                nXMTINTLEN  0x0
4345 
#define                 RCVINTLEN  0x8        /* Receive Buffer Interrupt Length */
4346 
#define                nRCVINTLEN  0x0
4347 
 
4348 
/* Bit maskes for TWIx_FIFO_STAT */
4349 
 
4350 
#define                   XMTSTAT  0x3        /* Transmit FIFO Status */
4351 
#define                   RCVSTAT  0xc        /* Receive FIFO Status */
4352 
 
4353 
/* Bit maskes for TWIx_INT_MASK */
4354 
 
4355 
#define                    SINITM  0x1        /* Slave Transfer Initiated Interrupt Mask */
4356 
#define                   nSINITM  0x0
4357 
#define                    SCOMPM  0x2        /* Slave Transfer Complete Interrupt Mask */
4358 
#define                   nSCOMPM  0x0
4359 
#define                     SERRM  0x4        /* Slave Transfer Error Interrupt Mask */
4360 
#define                    nSERRM  0x0
4361 
#define                     SOVFM  0x8        /* Slave Overflow Interrupt Mask */
4362 
#define                    nSOVFM  0x0
4363 
#define                    MCOMPM  0x10       /* Master Transfer Complete Interrupt Mask */
4364 
#define                   nMCOMPM  0x0
4365 
#define                     MERRM  0x20       /* Master Transfer Error Interrupt Mask */
4366 
#define                    nMERRM  0x0
4367 
#define                  XMTSERVM  0x40       /* Transmit FIFO Service Interrupt Mask */
4368 
#define                 nXMTSERVM  0x0
4369 
#define                  RCVSERVM  0x80       /* Receive FIFO Service Interrupt Mask */
4370 
#define                 nRCVSERVM  0x0
4371 
 
4372 
/* Bit maskes for TWIx_INT_STAT */
4373 
 
4374 
#define                     SINIT  0x1        /* Slave Transfer Initiated */
4375 
#define                    nSINIT  0x0
4376 
#define                     SCOMP  0x2        /* Slave Transfer Complete */
4377 
#define                    nSCOMP  0x0
4378 
#define                      SERR  0x4        /* Slave Transfer Error */
4379 
#define                     nSERR  0x0
4380 
#define                      SOVF  0x8        /* Slave Overflow */
4381 
#define                     nSOVF  0x0
4382 
#define                     MCOMP  0x10       /* Master Transfer Complete */
4383 
#define                    nMCOMP  0x0
4384 
#define                      MERR  0x20       /* Master Transfer Error */
4385 
#define                     nMERR  0x0
4386 
#define                   XMTSERV  0x40       /* Transmit FIFO Service */
4387 
#define                  nXMTSERV  0x0
4388 
#define                   RCVSERV  0x80       /* Receive FIFO Service */
4389 
#define                  nRCVSERV  0x0
4390 
 
4391 
/* Bit maskes for TWIx_XMT_DATA8 */
4392 
 
4393 
#define                  XMTDATA8  0xff       /* Transmit FIFO 8-Bit Data */
4394 
 
4395 
/* Bit maskes for TWIx_XMT_DATA16 */
4396 
 
4397 
#define                 XMTDATA16  0xffff     /* Transmit FIFO 16-Bit Data */
4398 
 
4399 
/* Bit maskes for TWIx_RCV_DATA8 */
4400 
 
4401 
#define                  RCVDATA8  0xff       /* Receive FIFO 8-Bit Data */
4402 
 
4403 
/* Bit maskes for TWIx_RCV_DATA16 */
4404 
 
4405 
#define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
4406 
 
4407 
/* Bit masks for SPORTx_TCR1 */
4408 
 
4409 
#define                     TCKFE  0x4000     /* Clock Falling Edge Select */
4410 
#define                    nTCKFE  0x0
4411 
#define                     LATFS  0x2000     /* Late Transmit Frame Sync */
4412 
#define                    nLATFS  0x0
4413 
#define                      LTFS  0x1000     /* Low Transmit Frame Sync Select */
4414 
#define                     nLTFS  0x0
4415 
#define                     DITFS  0x800      /* Data-Independent Transmit Frame Sync Select */
4416 
#define                    nDITFS  0x0
4417 
#define                      TFSR  0x400      /* Transmit Frame Sync Required Select */
4418 
#define                     nTFSR  0x0
4419 
#define                      ITFS  0x200      /* Internal Transmit Frame Sync Select */
4420 
#define                     nITFS  0x0
4421 
#define                    TLSBIT  0x10       /* Transmit Bit Order */
4422 
#define                   nTLSBIT  0x0
4423 
#define                    TDTYPE  0xc        /* Data Formatting Type Select */
4424 
#define                     ITCLK  0x2        /* Internal Transmit Clock Select */
4425 
#define                    nITCLK  0x0
4426 
#define                     TSPEN  0x1        /* Transmit Enable */
4427 
#define                    nTSPEN  0x0
4428 
 
4429 
/* Bit masks for SPORTx_TCR2 */
4430 
 
4431 
#define                     TRFST  0x400      /* Left/Right Order */
4432 
#define                    nTRFST  0x0
4433 
#define                     TSFSE  0x200      /* Transmit Stereo Frame Sync Enable */
4434 
#define                    nTSFSE  0x0
4435 
#define                      TXSE  0x100      /* TxSEC Enable */
4436 
#define                     nTXSE  0x0
4437 
#define                    SLEN_T  0x1f       /* SPORT Word Length */
4438 
 
4439 
/* Bit masks for SPORTx_RCR1 */
4440 
 
4441 
#define                     RCKFE  0x4000     /* Clock Falling Edge Select */
4442 
#define                    nRCKFE  0x0
4443 
#define                     LARFS  0x2000     /* Late Receive Frame Sync */
4444 
#define                    nLARFS  0x0
4445 
#define                      LRFS  0x1000     /* Low Receive Frame Sync Select */
4446 
#define                     nLRFS  0x0
4447 
#define                      RFSR  0x400      /* Receive Frame Sync Required Select */
4448 
#define                     nRFSR  0x0
4449 
#define                      IRFS  0x200      /* Internal Receive Frame Sync Select */
4450 
#define                     nIRFS  0x0
4451 
#define                    RLSBIT  0x10       /* Receive Bit Order */
4452 
#define                   nRLSBIT  0x0
4453 
#define                    RDTYPE  0xc        /* Data Formatting Type Select */
4454 
#define                     IRCLK  0x2        /* Internal Receive Clock Select */
4455 
#define                    nIRCLK  0x0
4456 
#define                     RSPEN  0x1        /* Receive Enable */
4457 
#define                    nRSPEN  0x0
4458 
 
4459 
/* Bit masks for SPORTx_RCR2 */
4460 
 
4461 
#define                     RRFST  0x400      /* Left/Right Order */
4462 
#define                    nRRFST  0x0
4463 
#define                     RSFSE  0x200      /* Receive Stereo Frame Sync Enable */
4464 
#define                    nRSFSE  0x0
4465 
#define                      RXSE  0x100      /* RxSEC Enable */
4466 
#define                     nRXSE  0x0
4467 
#define                    SLEN_R  0x1f       /* SPORT Word Length */
4468 
 
4469 
/* Bit masks for SPORTx_STAT */
4470 
 
4471 
#define                     TXHRE  0x40       /* Transmit Hold Register Empty */
4472 
#define                    nTXHRE  0x0
4473 
#define                      TOVF  0x20       /* Sticky Transmit Overflow Status */
4474 
#define                     nTOVF  0x0
4475 
#define                      TUVF  0x10       /* Sticky Transmit Underflow Status */
4476 
#define                     nTUVF  0x0
4477 
#define                       TXF  0x8        /* Transmit FIFO Full Status */
4478 
#define                      nTXF  0x0
4479 
#define                      ROVF  0x4        /* Sticky Receive Overflow Status */
4480 
#define                     nROVF  0x0
4481 
#define                      RUVF  0x2        /* Sticky Receive Underflow Status */
4482 
#define                     nRUVF  0x0
4483 
#define                      RXNE  0x1        /* Receive FIFO Not Empty Status */
4484 
#define                     nRXNE  0x0
4485 
 
4486 
/* Bit masks for SPORTx_MCMC1 */
4487 
 
4488 
#define                     WSIZE  0xf000     /* Window Size */
4489 
#define                      WOFF  0x3ff      /* Windows Offset */
4490 
 
4491 
/* Bit masks for SPORTx_MCMC2 */
4492 
 
4493 
#define                       MFD  0xf000     /* Multi channel Frame Delay */
4494 
#define                      FSDR  0x80       /* Frame Sync to Data Relationship */
4495 
#define                     nFSDR  0x0
4496 
#define                     MCMEN  0x10       /* Multi channel Frame Mode Enable */
4497 
#define                    nMCMEN  0x0
4498 
#define                   MCDRXPE  0x8        /* Multi channel DMA Receive Packing */
4499 
#define                  nMCDRXPE  0x0
4500 
#define                   MCDTXPE  0x4        /* Multi channel DMA Transmit Packing */
4501 
#define                  nMCDTXPE  0x0
4502 
#define                     MCCRM  0x3        /* 2X Clock Recovery Mode */
4503 
 
4504 
/* Bit masks for SPORTx_CHNL */
4505 
 
4506 
#define                  CUR_CHNL  0x3ff      /* Current Channel Indicator */
4507 
 
4508 
/* Bit masks for UARTx_LCR */
4509 
 
4510 
#if 0
4511 
/* conflicts with legacy one in last section */
4512 
#define                       WLS  0x3        /* Word Length Select */
4513 
#endif
4514 
#define                       STB  0x4        /* Stop Bits */
4515 
#define                      nSTB  0x0
4516 
#define                       PEN  0x8        /* Parity Enable */
4517 
#define                      nPEN  0x0
4518 
#define                       EPS  0x10       /* Even Parity Select */
4519 
#define                      nEPS  0x0
4520 
#define                       STP  0x20       /* Sticky Parity */
4521 
#define                      nSTP  0x0
4522 
#define                        SB  0x40       /* Set Break */
4523 
#define                       nSB  0x0
4524 
 
4525 
/* Bit masks for UARTx_MCR */
4526 
 
4527 
#define                      XOFF  0x1        /* Transmitter Off */
4528 
#define                     nXOFF  0x0
4529 
#define                      MRTS  0x2        /* Manual Request To Send */
4530 
#define                     nMRTS  0x0
4531 
#define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
4532 
#define                     nRFIT  0x0
4533 
#define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
4534 
#define                     nRFRT  0x0
4535 
#define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
4536 
#define                 nLOOP_ENA  0x0
4537 
#define                     FCPOL  0x20       /* Flow Control Pin Polarity */
4538 
#define                    nFCPOL  0x0
4539 
#define                      ARTS  0x40       /* Automatic Request To Send */
4540 
#define                     nARTS  0x0
4541 
#define                      ACTS  0x80       /* Automatic Clear To Send */
4542 
#define                     nACTS  0x0
4543 
 
4544 
/* Bit masks for UARTx_LSR */
4545 
 
4546 
#define                        DR  0x1        /* Data Ready */
4547 
#define                       nDR  0x0
4548 
#define                        OE  0x2        /* Overrun Error */
4549 
#define                       nOE  0x0
4550 
#define                        PE  0x4        /* Parity Error */
4551 
#define                       nPE  0x0
4552 
#define                        FE  0x8        /* Framing Error */
4553 
#define                       nFE  0x0
4554 
#define                        BI  0x10       /* Break Interrupt */
4555 
#define                       nBI  0x0
4556 
#define                      THRE  0x20       /* THR Empty */
4557 
#define                     nTHRE  0x0
4558 
#define                      TEMT  0x40       /* Transmitter Empty */
4559 
#define                     nTEMT  0x0
4560 
#define                       TFI  0x80       /* Transmission Finished Indicator */
4561 
#define                      nTFI  0x0
4562 
 
4563 
/* Bit masks for UARTx_MSR */
4564 
 
4565 
#define                      SCTS  0x1        /* Sticky CTS */
4566 
#define                     nSCTS  0x0
4567 
#define                       CTS  0x10       /* Clear To Send */
4568 
#define                      nCTS  0x0
4569 
#define                      RFCS  0x20       /* Receive FIFO Count Status */
4570 
#define                     nRFCS  0x0
4571 
 
4572 
/* Bit masks for UARTx_IER_SET and UARTx_IER_CLEAR */
4573 
 
4574 
#define                     ERBFI  0x1        /* Enable Receive Buffer Full Interrupt */
4575 
#define                    nERBFI  0x0
4576 
#define                     ETBEI  0x2        /* Enable Transmit Buffer Empty Interrupt */
4577 
#define                    nETBEI  0x0
4578 
#define                      ELSI  0x4        /* Enable Receive Status Interrupt */
4579 
#define                     nELSI  0x0
4580 
#define                     EDSSI  0x8        /* Enable Modem Status Interrupt */
4581 
#define                    nEDSSI  0x0
4582 
#define                    EDTPTI  0x10       /* Enable DMA Transmit PIRQ Interrupt */
4583 
#define                   nEDTPTI  0x0
4584 
#define                      ETFI  0x20       /* Enable Transmission Finished Interrupt */
4585 
#define                     nETFI  0x0
4586 
#define                     ERFCI  0x40       /* Enable Receive FIFO Count Interrupt */
4587 
#define                    nERFCI  0x0
4588 
 
4589 
 
4590 
/* Bit masks for UARTx_GCTL */
4591 
 
4592 
#define                      UCEN  0x1        /* UART Enable */
4593 
#define                     nUCEN  0x0
4594 
#define                      IREN  0x2        /* IrDA Mode Enable */
4595 
#define                     nIREN  0x0
4596 
#define                     TPOLC  0x4        /* IrDA TX Polarity Change */
4597 
#define                    nTPOLC  0x0
4598 
#define                     RPOLC  0x8        /* IrDA RX Polarity Change */
4599 
#define                    nRPOLC  0x0
4600 
#define                       FPE  0x10       /* Force Parity Error */
4601 
#define                      nFPE  0x0
4602 
#define                       FFE  0x20       /* Force Framing Error */
4603 
#define                      nFFE  0x0
4604 
#define                      EDBO  0x40       /* Enable Divide-by-One */
4605 
#define                     nEDBO  0x0
4606 
#define                     EGLSI  0x80       /* Enable Global LS Interrupt */
4607 
#define                    nEGLSI  0x0
4608 
 
4609 
/* Bit masks for HMDMAx_CONTROL */
4610 
 
4611 
#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
4612 
#define                  nHMDMAEN  0x0
4613 
#define                       REP  0x2        /* Handshake MDMA Request Polarity */
4614 
#define                      nREP  0x0
4615 
#define                       UTE  0x8        /* Urgency Threshold Enable */
4616 
#define                      nUTE  0x0
4617 
#define                       OIE  0x10       /* Overflow Interrupt Enable */
4618 
#define                      nOIE  0x0
4619 
#define                      BDIE  0x20       /* Block Done Interrupt Enable */
4620 
#define                     nBDIE  0x0
4621 
#define                      MBDI  0x40       /* Mask Block Done Interrupt */
4622 
#define                     nMBDI  0x0
4623 
#define                       SND  0x80       /* Source/Not Destination */
4624 
#define                      nSND  0x0
4625 
#define                       DRQ  0x300      /* Handshake MDMA Request Type */
4626 
#define                       RBC  0x1000     /* Force Reload of BCOUNT */
4627 
#define                      nRBC  0x0
4628 
#define                        PS  0x2000     /* Pin Status */
4629 
#define                       nPS  0x0
4630 
#define                        OI  0x4000     /* Overflow Interrupt Generated */
4631 
#define                       nOI  0x0
4632 
#define                       BDI  0x8000     /* Block Done Interrupt Generated */
4633 
#define                      nBDI  0x0
4634 
 
4635 
/* ******************************************* */
4636 
/*     MULTI BIT MACRO ENUMERATIONS            */
4637 
/* ******************************************* */
4638 
 
4639 
/* SYSCR Masks */
4640 
 
4641 
#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
4642 
#define NOBOOT 0x0030 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
4643 
 
4644 
 
4645 
#define BCODE 0x00F0
4646 
#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
4647 
#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
4648 
#define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */
4649 
#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
4650 
#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
4651 
 
4652 
#define CDMAPRIO 0x0100 /* DMA1 gets higher priority than DMA0 to L1 memory */
4653 
#define L2DMAPRIO 0x0200 /* DMA1 gets higher priority than DMA0 to L2 memory */
4654 
 
4655 
#define WURESET 0x1000 /* wakeup event since last hardware reset */
4656 
#define DFRESET 0x2000 /* recent reset was due to a double fault event */
4657 
#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
4658 
#define SWRESET 0x8000 /* recent reset was issued by software */
4659 
 
4660 
/* CNT_COMMAND bit field options */
4661 
 
4662 
#define W1LCNT_ZERO   0x0001   /* write 1 to load CNT_COUNTER with zero */
4663 
#define W1LCNT_MIN    0x0004   /* write 1 to load CNT_COUNTER from CNT_MIN */
4664 
#define W1LCNT_MAX    0x0008   /* write 1 to load CNT_COUNTER from CNT_MAX */
4665 
 
4666 
#define W1LMIN_ZERO   0x0010   /* write 1 to load CNT_MIN with zero */
4667 
#define W1LMIN_CNT    0x0020   /* write 1 to load CNT_MIN from CNT_COUNTER */
4668 
#define W1LMIN_MAX    0x0080   /* write 1 to load CNT_MIN from CNT_MAX */
4669 
 
4670 
#define W1LMAX_ZERO   0x0100   /* write 1 to load CNT_MAX with zero */
4671 
#define W1LMAX_CNT    0x0200   /* write 1 to load CNT_MAX from CNT_COUNTER */
4672 
#define W1LMAX_MIN    0x0400   /* write 1 to load CNT_MAX from CNT_MIN */
4673 
 
4674 
/* CNT_CONFIG bit field options */
4675 
 
4676 
#define CNTMODE_QUADENC  0x0000  /* quadrature encoder mode */
4677 
#define CNTMODE_BINENC   0x0100  /* binary encoder mode */
4678 
#define CNTMODE_UDCNT    0x0200  /* up/down counter mode */
4679 
#define CNTMODE_DIRCNT   0x0400  /* direction counter mode */
4680 
#define CNTMODE_DIRTMR   0x0500  /* direction timer mode */
4681 
 
4682 
#define BNDMODE_COMP     0x0000  /* boundary compare mode */
4683 
#define BNDMODE_ZERO     0x1000  /* boundary compare and zero mode */
4684 
#define BNDMODE_CAPT     0x2000  /* boundary capture mode */
4685 
#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
4686 
 
4687 
/* TMODE in TIMERx_CONFIG bit field options */
4688 
 
4689 
#define PWM_OUT  0x0001
4690 
#define WDTH_CAP 0x0002
4691 
#define EXT_CLK  0x0003
4692 
 
4693 
/* UARTx_LCR bit field options */
4694 
 
4695 
#define WLS_5   0x0000    /* 5 data bits */
4696 
#define WLS_6   0x0001    /* 6 data bits */
4697 
#define WLS_7   0x0002    /* 7 data bits */
4698 
#define WLS_8   0x0003    /* 8 data bits */
4699 
 
4700 
/* PINTx Register Bit Definitions */
4701 
 
4702 
#define PIQ0 0x00000001
4703 
#define PIQ1 0x00000002
4704 
#define PIQ2 0x00000004
4705 
#define PIQ3 0x00000008
4706 
 
4707 
#define PIQ4 0x00000010
4708 
#define PIQ5 0x00000020
4709 
#define PIQ6 0x00000040
4710 
#define PIQ7 0x00000080
4711 
 
4712 
#define PIQ8 0x00000100
4713 
#define PIQ9 0x00000200
4714 
#define PIQ10 0x00000400
4715 
#define PIQ11 0x00000800
4716 
 
4717 
#define PIQ12 0x00001000
4718 
#define PIQ13 0x00002000
4719 
#define PIQ14 0x00004000
4720 
#define PIQ15 0x00008000
4721 
 
4722 
#define PIQ16 0x00010000
4723 
#define PIQ17 0x00020000
4724 
#define PIQ18 0x00040000
4725 
#define PIQ19 0x00080000
4726 
 
4727 
#define PIQ20 0x00100000
4728 
#define PIQ21 0x00200000
4729 
#define PIQ22 0x00400000
4730 
#define PIQ23 0x00800000
4731 
 
4732 
#define PIQ24 0x01000000
4733 
#define PIQ25 0x02000000
4734 
#define PIQ26 0x04000000
4735 
#define PIQ27 0x08000000
4736 
 
4737 
#define PIQ28 0x10000000
4738 
#define PIQ29 0x20000000
4739 
#define PIQ30 0x40000000
4740 
#define PIQ31 0x80000000
4741 
 
4742 
/* PORT A Bit Definitions for the registers
4743 
PORTA, PORTA_SET, PORTA_CLEAR,
4744 
PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
4745 
PORTA_FER registers
4746 
*/
4747 
 
4748 
#define PA0 0x0001
4749 
#define PA1 0x0002
4750 
#define PA2 0x0004
4751 
#define PA3 0x0008
4752 
#define PA4 0x0010
4753 
#define PA5 0x0020
4754 
#define PA6 0x0040
4755 
#define PA7 0x0080
4756 
#define PA8 0x0100
4757 
#define PA9 0x0200
4758 
#define PA10 0x0400
4759 
#define PA11 0x0800
4760 
#define PA12 0x1000
4761 
#define PA13 0x2000
4762 
#define PA14 0x4000
4763 
#define PA15 0x8000
4764 
 
4765 
/* PORT B Bit Definitions for the registers
4766 
PORTB, PORTB_SET, PORTB_CLEAR,
4767 
PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
4768 
PORTB_FER registers
4769 
*/
4770 
 
4771 
#define PB0 0x0001
4772 
#define PB1 0x0002
4773 
#define PB2 0x0004
4774 
#define PB3 0x0008
4775 
#define PB4 0x0010
4776 
#define PB5 0x0020
4777 
#define PB6 0x0040
4778 
#define PB7 0x0080
4779 
#define PB8 0x0100
4780 
#define PB9 0x0200
4781 
#define PB10 0x0400
4782 
#define PB11 0x0800
4783 
#define PB12 0x1000
4784 
#define PB13 0x2000
4785 
#define PB14 0x4000
4786 
 
4787 
 
4788 
/* PORT C Bit Definitions for the registers
4789 
PORTC, PORTC_SET, PORTC_CLEAR,
4790 
PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
4791 
PORTC_FER registers
4792 
*/
4793 
 
4794 
 
4795 
#define PC0 0x0001
4796 
#define PC1 0x0002
4797 
#define PC2 0x0004
4798 
#define PC3 0x0008
4799 
#define PC4 0x0010
4800 
#define PC5 0x0020
4801 
#define PC6 0x0040
4802 
#define PC7 0x0080
4803 
#define PC8 0x0100
4804 
#define PC9 0x0200
4805 
#define PC10 0x0400
4806 
#define PC11 0x0800
4807 
#define PC12 0x1000
4808 
#define PC13 0x2000
4809 
 
4810 
 
4811 
/* PORT D Bit Definitions for the registers
4812 
PORTD, PORTD_SET, PORTD_CLEAR,
4813 
PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
4814 
PORTD_FER registers
4815 
*/
4816 
 
4817 
#define PD0 0x0001
4818 
#define PD1 0x0002
4819 
#define PD2 0x0004
4820 
#define PD3 0x0008
4821 
#define PD4 0x0010
4822 
#define PD5 0x0020
4823 
#define PD6 0x0040
4824 
#define PD7 0x0080
4825 
#define PD8 0x0100
4826 
#define PD9 0x0200
4827 
#define PD10 0x0400
4828 
#define PD11 0x0800
4829 
#define PD12 0x1000
4830 
#define PD13 0x2000
4831 
#define PD14 0x4000
4832 
#define PD15 0x8000
4833 
 
4834 
/* PORT E Bit Definitions for the registers
4835 
PORTE, PORTE_SET, PORTE_CLEAR,
4836 
PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
4837 
PORTE_FER registers
4838 
*/
4839 
 
4840 
 
4841 
#define PE0 0x0001
4842 
#define PE1 0x0002
4843 
#define PE2 0x0004
4844 
#define PE3 0x0008
4845 
#define PE4 0x0010
4846 
#define PE5 0x0020
4847 
#define PE6 0x0040
4848 
#define PE7 0x0080
4849 
#define PE8 0x0100
4850 
#define PE9 0x0200
4851 
#define PE10 0x0400
4852 
#define PE11 0x0800
4853 
#define PE12 0x1000
4854 
#define PE13 0x2000
4855 
#define PE14 0x4000
4856 
#define PE15 0x8000
4857 
 
4858 
/* PORT F Bit Definitions for the registers
4859 
PORTF, PORTF_SET, PORTF_CLEAR,
4860 
PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
4861 
PORTF_FER registers
4862 
*/
4863 
 
4864 
 
4865 
#define PF0 0x0001
4866 
#define PF1 0x0002
4867 
#define PF2 0x0004
4868 
#define PF3 0x0008
4869 
#define PF4 0x0010
4870 
#define PF5 0x0020
4871 
#define PF6 0x0040
4872 
#define PF7 0x0080
4873 
#define PF8 0x0100
4874 
#define PF9 0x0200
4875 
#define PF10 0x0400
4876 
#define PF11 0x0800
4877 
#define PF12 0x1000
4878 
#define PF13 0x2000
4879 
#define PF14 0x4000
4880 
#define PF15 0x8000
4881 
 
4882 
/* PORT G Bit Definitions for the registers
4883 
PORTG, PORTG_SET, PORTG_CLEAR,
4884 
PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
4885 
PORTG_FER registers
4886 
*/
4887 
 
4888 
 
4889 
#define PG0 0x0001
4890 
#define PG1 0x0002
4891 
#define PG2 0x0004
4892 
#define PG3 0x0008
4893 
#define PG4 0x0010
4894 
#define PG5 0x0020
4895 
#define PG6 0x0040
4896 
#define PG7 0x0080
4897 
#define PG8 0x0100
4898 
#define PG9 0x0200
4899 
#define PG10 0x0400
4900 
#define PG11 0x0800
4901 
#define PG12 0x1000
4902 
#define PG13 0x2000
4903 
#define PG14 0x4000
4904 
#define PG15 0x8000
4905 
 
4906 
/* PORT H Bit Definitions for the registers
4907 
PORTH, PORTH_SET, PORTH_CLEAR,
4908 
PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
4909 
PORTH_FER registers
4910 
*/
4911 
 
4912 
 
4913 
#define PH0 0x0001
4914 
#define PH1 0x0002
4915 
#define PH2 0x0004
4916 
#define PH3 0x0008
4917 
#define PH4 0x0010
4918 
#define PH5 0x0020
4919 
#define PH6 0x0040
4920 
#define PH7 0x0080
4921 
#define PH8 0x0100
4922 
#define PH9 0x0200
4923 
#define PH10 0x0400
4924 
#define PH11 0x0800
4925 
#define PH12 0x1000
4926 
#define PH13 0x2000
4927 
 
4928 
 
4929 
/* PORT I Bit Definitions for the registers
4930 
PORTI, PORTI_SET, PORTI_CLEAR,
4931 
PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
4932 
PORTI_FER registers
4933 
*/
4934 
 
4935 
 
4936 
#define PI0 0x0001
4937 
#define PI1 0x0002
4938 
#define PI2 0x0004
4939 
#define PI3 0x0008
4940 
#define PI4 0x0010
4941 
#define PI5 0x0020
4942 
#define PI6 0x0040
4943 
#define PI7 0x0080
4944 
#define PI8 0x0100
4945 
#define PI9 0x0200
4946 
#define PI10 0x0400
4947 
#define PI11 0x0800
4948 
#define PI12 0x1000
4949 
#define PI13 0x2000
4950 
#define PI14 0x4000
4951 
#define PI15 0x8000
4952 
 
4953 
/* PORT J Bit Definitions for the registers
4954 
PORTJ, PORTJ_SET, PORTJ_CLEAR,
4955 
PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
4956 
PORTJ_FER registers
4957 
*/
4958 
 
4959 
 
4960 
#define PJ0 0x0001
4961 
#define PJ1 0x0002
4962 
#define PJ2 0x0004
4963 
#define PJ3 0x0008
4964 
#define PJ4 0x0010
4965 
#define PJ5 0x0020
4966 
#define PJ6 0x0040
4967 
#define PJ7 0x0080
4968 
#define PJ8 0x0100
4969 
#define PJ9 0x0200
4970 
#define PJ10 0x0400
4971 
#define PJ11 0x0800
4972 
#define PJ12 0x1000
4973 
#define PJ13 0x2000
4974 
 
4975 
 
4976 
/* Port Muxing Bit Fields for PORTx_MUX Registers */
4977 
 
4978 
#define MUX0 0x00000003
4979 
#define MUX0_0 0x00000000
4980 
#define MUX0_1 0x00000001
4981 
#define MUX0_2 0x00000002
4982 
#define MUX0_3 0x00000003
4983 
 
4984 
#define MUX1 0x0000000C
4985 
#define MUX1_0 0x00000000
4986 
#define MUX1_1 0x00000004
4987 
#define MUX1_2 0x00000008
4988 
#define MUX1_3 0x0000000C
4989 
 
4990 
#define MUX2 0x00000030
4991 
#define MUX2_0 0x00000000
4992 
#define MUX2_1 0x00000010
4993 
#define MUX2_2 0x00000020
4994 
#define MUX2_3 0x00000030
4995 
 
4996 
#define MUX3 0x000000C0
4997 
#define MUX3_0 0x00000000
4998 
#define MUX3_1 0x00000040
4999 
#define MUX3_2 0x00000080
5000 
#define MUX3_3 0x000000C0
5001 
 
5002 
#define MUX4 0x00000300
5003 
#define MUX4_0 0x00000000
5004 
#define MUX4_1 0x00000100
5005 
#define MUX4_2 0x00000200
5006 
#define MUX4_3 0x00000300
5007 
 
5008 
#define MUX5 0x00000C00
5009 
#define MUX5_0 0x00000000
5010 
#define MUX5_1 0x00000400
5011 
#define MUX5_2 0x00000800
5012 
#define MUX5_3 0x00000C00
5013 
 
5014 
#define MUX6 0x00003000
5015 
#define MUX6_0 0x00000000
5016 
#define MUX6_1 0x00001000
5017 
#define MUX6_2 0x00002000
5018 
#define MUX6_3 0x00003000
5019 
 
5020 
#define MUX7 0x0000C000
5021 
#define MUX7_0 0x00000000
5022 
#define MUX7_1 0x00004000
5023 
#define MUX7_2 0x00008000
5024 
#define MUX7_3 0x0000C000
5025 
 
5026 
#define MUX8 0x00030000
5027 
#define MUX8_0 0x00000000
5028 
#define MUX8_1 0x00010000
5029 
#define MUX8_2 0x00020000
5030 
#define MUX8_3 0x00030000
5031 
 
5032 
#define MUX9 0x000C0000
5033 
#define MUX9_0 0x00000000
5034 
#define MUX9_1 0x00040000
5035 
#define MUX9_2 0x00080000
5036 
#define MUX9_3 0x000C0000
5037 
 
5038 
#define MUX10 0x00300000
5039 
#define MUX10_0 0x00000000
5040 
#define MUX10_1 0x00100000
5041 
#define MUX10_2 0x00200000
5042 
#define MUX10_3 0x00300000
5043 
 
5044 
#define MUX11 0x00C00000
5045 
#define MUX11_0 0x00000000
5046 
#define MUX11_1 0x00400000
5047 
#define MUX11_2 0x00800000
5048 
#define MUX11_3 0x00C00000
5049 
 
5050 
#define MUX12 0x03000000
5051 
#define MUX12_0 0x00000000
5052 
#define MUX12_1 0x01000000
5053 
#define MUX12_2 0x02000000
5054 
#define MUX12_3 0x03000000
5055 
 
5056 
#define MUX13 0x0C000000
5057 
#define MUX13_0 0x00000000
5058 
#define MUX13_1 0x04000000
5059 
#define MUX13_2 0x08000000
5060 
#define MUX13_3 0x0C000000
5061 
 
5062 
#define MUX14 0x30000000
5063 
#define MUX14_0 0x00000000
5064 
#define MUX14_1 0x10000000
5065 
#define MUX14_2 0x20000000
5066 
#define MUX14_3 0x30000000
5067 
 
5068 
#define MUX15 0xC0000000
5069 
#define MUX15_0 0x00000000
5070 
#define MUX15_1 0x40000000
5071 
#define MUX15_2 0x80000000
5072 
#define MUX15_3 0xC0000000
5073 
 
5074 
#ifdef _MISRA_RULES
5075 
#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
5076 
    ((((b15)&3u) << 30) | \
5077 
     (((b14)&3u) << 28) | \
5078 
     (((b13)&3u) << 26) | \
5079 
     (((b12)&3u) << 24) | \
5080 
     (((b11)&3u) << 22) | \
5081 
     (((b10)&3u) << 20) | \
5082 
     (((b9) &3u) << 18) | \
5083 
     (((b8) &3u) << 16) | \
5084 
     (((b7) &3u) << 14) | \
5085 
     (((b6) &3u) << 12) | \
5086 
     (((b5) &3u) << 10) | \
5087 
     (((b4) &3u) << 8)  | \
5088 
     (((b3) &3u) << 6)  | \
5089 
     (((b2) &3u) << 4)  | \
5090 
     (((b1) &3u) << 2)  | \
5091 
     (((b0) &3u)))
5092 
#else
5093 
#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
5094 
    ((((b15)&3) << 30) | \
5095 
     (((b14)&3) << 28) | \
5096 
     (((b13)&3) << 26) | \
5097 
     (((b12)&3) << 24) | \
5098 
     (((b11)&3) << 22) | \
5099 
     (((b10)&3) << 20) | \
5100 
     (((b9) &3) << 18) | \
5101 
     (((b8) &3) << 16) | \
5102 
     (((b7) &3) << 14) | \
5103 
     (((b6) &3) << 12) | \
5104 
     (((b5) &3) << 10) | \
5105 
     (((b4) &3) << 8)  | \
5106 
     (((b3) &3) << 6)  | \
5107 
     (((b2) &3) << 4)  | \
5108 
     (((b1) &3) << 2)  | \
5109 
     (((b0) &3)))
5110 
#endif /* _MISRA_RULES */
5111 
 
5112 
/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
5113 
 
5114 
#define B0MAP 0x000000FF     /* Byte 0 Lower Half Port Mapping */
5115 
#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
5116 
#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
5117 
#define B1MAP 0x0000FF00     /* Byte 1 Upper Half Port Mapping */
5118 
#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
5119 
#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
5120 
#define B2MAP 0x00FF0000     /* Byte 2 Lower Half Port Mapping */
5121 
#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
5122 
#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
5123 
#define B3MAP 0xFF000000     /* Byte 3 Upper Half Port Mapping */
5124 
#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
5125 
#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
5126 
 
5127 
/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
5128 
 
5129 
#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
5130 
#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
5131 
#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
5132 
#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
5133 
#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
5134 
#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
5135 
#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
5136 
#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
5137 
 
5138 
#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
5139 
#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
5140 
#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
5141 
#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
5142 
#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
5143 
#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
5144 
#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
5145 
#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
5146 
 
5147 
#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
5148 
#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
5149 
#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
5150 
#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
5151 
#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
5152 
#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
5153 
#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
5154 
#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
5155 
 
5156 
#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
5157 
#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
5158 
#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
5159 
#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
5160 
#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
5161 
#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
5162 
#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
5163 
#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
5164 
 
5165 
 
5166 
/* for legacy compatibility */
5167 
 
5168 
#ifdef _MISRA_RULES
5169 
#define WLS(x)  (((x)-5u) & 0x03u) /* Word Length Select */
5170 
#else
5171 
#define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
5172 
#endif /* _MISRA_RULES */
5173 
#define W1LMAX_MAX W1LMAX_MIN
5174 
#define EBIU_AMCBCTL0 EBIU_AMBCTL0
5175 
#define EBIU_AMCBCTL1 EBIU_AMBCTL1
5176 
#define PINT0_IRQ PINT0_REQUEST
5177 
#define PINT1_IRQ PINT1_REQUEST
5178 
#define PINT2_IRQ PINT2_REQUEST
5179 
#define PINT3_IRQ PINT3_REQUEST
5180 
 
5181 
 
5182 
/*********************************************************************************** */
5183 
/* System MMR Register Bits */
5184 
/******************************************************************************* */
5185 
 
5186 
/* **************************  DMA CONTROLLER MASKS  ********************************/
5187 
/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                */
5188 
#define WDSIZE_8        0x0000          /* Transfer Word Size = 8 */
5189 
#define WDSIZE_16       0x0004          /* Transfer Word Size = 16 */
5190 
#define WDSIZE_32       0x0008          /* Transfer Word Size = 32 */
5191 
#define NDSIZE_0        0x0000          /* Next Descriptor Size = 0 (Stop/Autobuffer) */
5192 
#define NDSIZE_1        0x0100          /* Next Descriptor Size = 1 */
5193 
#define NDSIZE_2        0x0200          /* Next Descriptor Size = 2 */
5194 
#define NDSIZE_3        0x0300          /* Next Descriptor Size = 3 */
5195 
#define NDSIZE_4        0x0400          /* Next Descriptor Size = 4 */
5196 
#define NDSIZE_5        0x0500          /* Next Descriptor Size = 5 */
5197 
#define NDSIZE_6        0x0600          /* Next Descriptor Size = 6 */
5198 
#define NDSIZE_7        0x0700          /* Next Descriptor Size = 7 */
5199 
#define NDSIZE_8        0x0800          /* Next Descriptor Size = 8 */
5200 
#define NDSIZE_9        0x0900          /* Next Descriptor Size = 9 */
5201 
 
5202 
#ifdef _MISRA_RULES
5203 
#define SET_NDSIZE(x)   (((x)&0xFu)<<8)
5204 
#else
5205 
#define SET_NDSIZE(x)   (((x)&0xF)<<8)
5206 
#endif
5207 
                                        /* NDSIZE[3:0] (Flex Descriptor Size)
5208 
                                            Size of next descriptor
5209 
                                            0000 - Required if in Stop or Autobuffer mode
5210 
                                            0001 - 1001 - Descriptor size
5211 
                                            1010 - 1111 - Reserved */
5212 
#define FLOW_STOP       0x0000          /* Stop Mode */
5213 
#define FLOW_AUTO       0x1000          /* Autobuffer Mode */
5214 
#define FLOW_ARRAY      0x4000          /* Descriptor Array Mode */
5215 
#define FLOW_SMALL      0x6000          /* Small Model Descriptor List Mode */
5216 
#define FLOW_LARGE      0x7000          /* Large Model Descriptor List Mode */
5217 
 
5218 
 
5219 
/* ********************* PLL AND RESET MASKS ************************ */
5220 
/* SWRST Mask */
5221 
#define SYSTEM_RESET    0x0007          /* Initiates A System Software Reset */
5222 
#define DOUBLE_FAULT    0x0008          /* Core Double Fault Causes Reset */
5223 
#define RESET_DOUBLE    0x2000          /* SW Reset Generated By Core Double-Fault */
5224 
#define RESET_WDOG      0x4000          /* SW Reset Generated By Watchdog Timer */
5225 
#define RESET_SOFTWARE  0x8000          /* SW Reset Occurred Since Last Read Of SWRST */
5226 
 
5227 
 
5228 
/* ******************************************* */
5229 
/*     MULTI BIT MACRO ENUMERATIONS            */
5230 
/* ******************************************* */
5231 
 
5232 
/* PORT A Bit Definitions for the registers
5233 
PORTA, PORTA_SET, PORTA_CLEAR, PORTA_DIR_SET,
5234 
PORTA_DIR_CLEAR, PORTA_INEN, PORTA_FER */
5235 
 
5236 
#define nPA0 0x0
5237 
#define nPA1 0x0
5238 
#define nPA2 0x0
5239 
#define nPA3 0x0
5240 
#define nPA4 0x0
5241 
#define nPA5 0x0
5242 
#define nPA6 0x0
5243 
#define nPA7 0x0
5244 
#define nPA8 0x0
5245 
#define nPA9 0x0
5246 
#define nPA10 0x0
5247 
#define nPA11 0x0
5248 
#define nPA12 0x0
5249 
#define nPA13 0x0
5250 
#define nPA14 0x0
5251 
#define nPA15 0x0
5252 
 
5253 
/* PORT B Bit Definitions for the registers
5254 
PORTB, PORTB_SET, PORTB_CLEAR, PORTB_DIR_SET,
5255 
PORTB_DIR_CLEAR, PORTB_INEN, PORTB_FER */
5256 
 
5257 
#define nPB0 0x0
5258 
#define nPB1 0x0
5259 
#define nPB2 0x0
5260 
#define nPB3 0x0
5261 
#define nPB4 0x0
5262 
#define nPB5 0x0
5263 
#define nPB6 0x0
5264 
#define nPB7 0x0
5265 
#define nPB8 0x0
5266 
#define nPB9 0x0
5267 
#define nPB10 0x0
5268 
#define nPB11 0x0
5269 
#define nPB12 0x0
5270 
#define nPB13 0x0
5271 
#define nPB14 0x0
5272 
#define nPB15 0x0
5273 
 
5274 
/* PORT D Bit Definitions for the registers
5275 
PORTD, PORTD_SET, PORTD_CLEAR, PORTD_DIR_SET,
5276 
PORTD_DIR_CLEAR, PORTD_INEN, PORTD_FER */
5277 
 
5278 
#define nPD0 0x0
5279 
#define nPD1 0x0
5280 
#define nPD2 0x0
5281 
#define nPD3 0x0
5282 
#define nPD4 0x0
5283 
#define nPD5 0x0
5284 
#define nPD6 0x0
5285 
#define nPD7 0x0
5286 
#define nPD8 0x0
5287 
#define nPD9 0x0
5288 
#define nPD10 0x0
5289 
#define nPD11 0x0
5290 
#define nPD12 0x0
5291 
#define nPD13 0x0
5292 
#define nPD14 0x0
5293 
#define nPD15 0x0
5294 
 
5295 
/* PORT E Bit Definitions for the registers
5296 
PORTE, PORTE_SET, PORTE_CLEAR, PORTE_DIR_SET,
5297 
PORTE_DIR_CLEAR, PORTE_INEN, PORTE_FER */
5298 
 
5299 
#define nPE0 0x0
5300 
#define nPE1 0x0
5301 
#define nPE2 0x0
5302 
#define nPE3 0x0
5303 
#define nPE4 0x0
5304 
#define nPE5 0x0
5305 
#define nPE6 0x0
5306 
#define nPE7 0x0
5307 
#define nPE8 0x0
5308 
#define nPE9 0x0
5309 
#define nPE10 0x0
5310 
#define nPE11 0x0
5311 
#define nPE12 0x0
5312 
#define nPE13 0x0
5313 
#define nPE14 0x0
5314 
#define nPE15 0x0
5315 
 
5316 
/* PORT F Bit Definitions for the registers
5317 
PORTF, PORTF_SET, PORTF_CLEAR, PORTF_DIR_SET,
5318 
PORTF_DIR_CLEAR, PORTF_INEN, PORTF_FER */
5319 
 
5320 
#define nPF0 0x0
5321 
#define nPF1 0x0
5322 
#define nPF2 0x0
5323 
#define nPF3 0x0
5324 
#define nPF4 0x0
5325 
#define nPF5 0x0
5326 
#define nPF6 0x0
5327 
#define nPF7 0x0
5328 
#define nPF8 0x0
5329 
#define nPF9 0x0
5330 
#define nPF10 0x0
5331 
#define nPF11 0x0
5332 
#define nPF12 0x0
5333 
#define nPF13 0x0
5334 
#define nPF14 0x0
5335 
#define nPF15 0x0
5336 
 
5337 
/* PORT G Bit Definitions for the registers
5338 
PORTG, PORTG_SET, PORTG_CLEAR, PORTG_DIR_SET,
5339 
PORTG_DIR_CLEAR, PORTG_INEN, PORTG_FER */
5340 
#define nPG0 0x0
5341 
#define nPG1 0x0
5342 
#define nPG2 0x0
5343 
#define nPG3 0x0
5344 
#define nPG4 0x0
5345 
#define nPG5 0x0
5346 
#define nPG6 0x0
5347 
#define nPG7 0x0
5348 
#define nPG8 0x0
5349 
#define nPG9 0x0
5350 
#define nPG10 0x0
5351 
#define nPG11 0x0
5352 
#define nPG12 0x0
5353 
#define nPG13 0x0
5354 
#define nPG14 0x0
5355 
#define nPG15 0x0
5356 
 
5357 
/* PORT H Bit Definitions for the registers
5358 
PORTH, PORTH_SET, PORTH_CLEAR, PORTH_DIR_SET,
5359 
PORTH_DIR_CLEAR, PORTH_INEN, PORTH_FER */
5360 
#define nPH0 0x0
5361 
#define nPH1 0x0
5362 
#define nPH2 0x0
5363 
#define nPH3 0x0
5364 
#define nPH4 0x0
5365 
#define nPH5 0x0
5366 
#define nPH6 0x0
5367 
#define nPH7 0x0
5368 
#define nPH8 0x0
5369 
#define nPH9 0x0
5370 
#define nPH10 0x0
5371 
#define nPH11 0x0
5372 
#define nPH12 0x0
5373 
#define nPH13 0x0
5374 
#define nPH14 0x0
5375 
#define nPH15 0x0
5376 
 
5377 
/* PORT I Bit Definitions for the registers
5378 
PORTI, PORTI_SET, PORTI_CLEAR, PORTI_DIR_SET,
5379 
PORTI_DIR_CLEAR, PORTI_INEN, PORTI_FER */
5380 
#define nPI0 0x0
5381 
#define nPI1 0x0
5382 
#define nPI2 0x0
5383 
#define nPI3 0x0
5384 
#define nPI4 0x0
5385 
#define nPI5 0x0
5386 
#define nPI6 0x0
5387 
#define nPI7 0x0
5388 
#define nPI8 0x0
5389 
#define nPI9 0x0
5390 
#define nPI10 0x0
5391 
#define nPI11 0x0
5392 
#define nPI12 0x0
5393 
#define nPI13 0x0
5394 
#define nPI14 0x0
5395 
#define nPI15 0x0
5396 
 
5397 
/* PORT J Bit Definitions for the registers
5398 
PORTJ, PORTJ_SET, PORTJ_CLEAR, PORTJ_DIR_SET,
5399 
PORTJ_DIR_CLEAR, PORTJ_INEN, PORTJ_FER */
5400 
#define nPJ0 0x0
5401 
#define nPJ1 0x0
5402 
#define nPJ2 0x0
5403 
#define nPJ3 0x0
5404 
#define nPJ4 0x0
5405 
#define nPJ5 0x0
5406 
#define nPJ6 0x0
5407 
#define nPJ7 0x0
5408 
#define nPJ8 0x0
5409 
#define nPJ9 0x0
5410 
#define nPJ10 0x0
5411 
#define nPJ11 0x0
5412 
#define nPJ12 0x0
5413 
#define nPJ13 0x0
5414 
#define nPJ14 0x0
5415 
#define nPJ15 0x0
5416 
 
5417 
 
5418 
#ifdef _MISRA_RULES
5419 
#define _MF15 0xFu
5420 
#define _MF7 7u
5421 
#else
5422 
#define _MF15 0xF
5423 
#define _MF7 7
5424 
#endif /* _MISRA_RULES */
5425 
 
5426 
/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
5427 
 
5428 
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                     */
5429 
 
5430 
/* SIC_IMASKx Masks */
5431 
/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
5432 
#define SIC_UNMASK_ALL  0x00000000  /* Unmask all peripheral interrupts */
5433 
#define SIC_MASK_ALL    0xFFFFFFFF  /* Mask all peripheral interrupts */
5434 
 
5435 
/* SIC_IMASKx Macros */
5436 
#ifdef _MISRA_RULES
5437 
#define SIC_MASK(x)     (1 << (x))  /* Mask Peripheral #x interrupt */
5438 
#define SIC_UNMASK(x)   (0xFFFFFFFFu ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
5439 
#else
5440 
#define SIC_MASK(x)     (1 << (x))  /* Mask Peripheral #x interrupt */
5441 
#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
5442 
#endif /* _MISRA_RULES */
5443 
 
5444 
/* SIC_IWR Masks */
5445 
#define IWR_DISABLE_ALL 0x00000000          /* Wakeup Disable all peripherals */
5446 
#define IWR_ENABLE_ALL  0xFFFFFFFF          /* Wakeup Enable all peripherals */
5447 
 
5448 
/* SIC_IWR Macros */
5449 
/* x = pos 0 to 31, for 32-63 use value-32 */
5450 
#ifdef _MISRA_RULES
5451 
#define IWR_ENABLE(x)   (1 << (x))          /* Wakeup Enable Peripheral #x */
5452 
#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
5453 
#else
5454 
#define IWR_ENABLE(x)   (1 << (x))          /* Wakeup Enable Peripheral #x */
5455 
#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
5456 
#endif /* _MISRA_RULES */
5457 
 
5458 
#define PIVG(PNr, IVGNr) ( (IVGNr) - 7) << ( ((PNr)%8) * 4) /* Peripheral #PNr assigned IVG #IVGNr  */
5459 
/* Rx.L = lo(PIVG(62,10)); */
5460 
/* Rx.H = hi(PIVG(62,10)); */
5461 
/* PNr = 0 to 95 */
5462 
/* IVGNr = 7 to 15 */
5463 
 
5464 
/* SIC_IAR0 Macros */
5465 
#define P0_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #0 assigned IVG #x    */
5466 
#define P1_IVG(x)       (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #1 assigned IVG #x    */
5467 
#define P2_IVG(x)       (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #2 assigned IVG #x    */
5468 
#define P3_IVG(x)       (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #3 assigned IVG #x    */
5469 
#define P4_IVG(x)       (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #4 assigned IVG #x    */
5470 
#define P5_IVG(x)       (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #5 assigned IVG #x    */
5471 
#define P6_IVG(x)       (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #6 assigned IVG #x    */
5472 
#define P7_IVG(x)       (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #7 assigned IVG #x    */
5473 
 
5474 
/* SIC_IAR1 Macros */
5475 
#define P8_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #8 assigned IVG #x    */
5476 
#define P9_IVG(x)       (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #9 assigned IVG #x    */
5477 
#define P10_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #10 assigned IVG #x   */
5478 
#define P11_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #11 assigned IVG #x   */
5479 
#define P12_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #12 assigned IVG #x   */
5480 
#define P13_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #13 assigned IVG #x   */
5481 
#define P14_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #14 assigned IVG #x   */
5482 
#define P15_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #15 assigned IVG #x   */
5483 
 
5484 
/* SIC_IAR2 Macros */
5485 
#define P16_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #16 assigned IVG #x   */
5486 
#define P17_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #17 assigned IVG #x   */
5487 
#define P18_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #18 assigned IVG #x   */
5488 
#define P19_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #19 assigned IVG #x   */
5489 
#define P20_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #20 assigned IVG #x   */
5490 
#define P21_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #21 assigned IVG #x   */
5491 
#define P22_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #22 assigned IVG #x   */
5492 
#define P23_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #23 assigned IVG #x   */
5493 
 
5494 
/* SIC_IAR3 Macros */
5495 
#define P24_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #24 assigned IVG #x   */
5496 
#define P25_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #25 assigned IVG #x   */
5497 
#define P26_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #26 assigned IVG #x   */
5498 
#define P27_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #27 assigned IVG #x   */
5499 
#define P28_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #28 assigned IVG #x   */
5500 
#define P29_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #29 assigned IVG #x   */
5501 
#define P30_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #30 assigned IVG #x   */
5502 
#define P31_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #31 assigned IVG #x   */
5503 
 
5504 
/* SIC_IAR4 Macros */
5505 
#define P32_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #32 assigned IVG #x   */
5506 
#define P33_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #33 assigned IVG #x   */
5507 
#define P34_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #34 assigned IVG #x   */
5508 
#define P35_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #35 assigned IVG #x   */
5509 
#define P36_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #36 assigned IVG #x   */
5510 
#define P37_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #37 assigned IVG #x   */
5511 
#define P38_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #38 assigned IVG #x   */
5512 
#define P39_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #39 assigned IVG #x   */
5513 
 
5514 
/* SIC_IAR4 Macros */
5515 
#define P40_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #40 assigned IVG #x   */
5516 
#define P41_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #41 assigned IVG #x   */
5517 
#define P42_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #42 assigned IVG #x   */
5518 
#define P43_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #43 assigned IVG #x   */
5519 
#define P44_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #44 assigned IVG #x   */
5520 
#define P45_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #45 assigned IVG #x   */
5521 
#define P46_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #46 assigned IVG #x   */
5522 
#define P47_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #47 assigned IVG #x   */
5523 
 
5524 
/* SIC_IAR5 Macros */
5525 
#define P48_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #48 assigned IVG #x   */
5526 
#define P49_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #49 assigned IVG #x   */
5527 
#define P50_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #50 assigned IVG #x   */
5528 
#define P51_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #51 assigned IVG #x   */
5529 
#define P52_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #52 assigned IVG #x   */
5530 
#define P53_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #53 assigned IVG #x   */
5531 
#define P54_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #54 assigned IVG #x   */
5532 
#define P55_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #55 assigned IVG #x   */
5533 
 
5534 
/* SIC_IAR5 Macros */
5535 
#define P56_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #56 assigned IVG #x   */
5536 
#define P57_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #57 assigned IVG #x   */
5537 
#define P58_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #58 assigned IVG #x   */
5538 
#define P59_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #59 assigned IVG #x   */
5539 
#define P60_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #60 assigned IVG #x   */
5540 
#define P61_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #61 assigned IVG #x   */
5541 
#define P62_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #62 assigned IVG #x   */
5542 
#define P63_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #63 assigned IVG #x   */
5543 
 
5544 
/* SIC_IAR6 Macros */
5545 
#define P64_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #64 assigned IVG #x   */
5546 
#define P65_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #65 assigned IVG #x   */
5547 
#define P66_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #66 assigned IVG #x   */
5548 
#define P67_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #67 assigned IVG #x   */
5549 
#define P68_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #68 assigned IVG #x   */
5550 
#define P69_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #69 assigned IVG #x   */
5551 
#define P70_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #70 assigned IVG #x   */
5552 
#define P71_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #71 assigned IVG #x   */
5553 
 
5554 
/* SIC_IAR7 Macros */
5555 
#define P72_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #72 assigned IVG #x   */
5556 
#define P73_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #73 assigned IVG #x   */
5557 
#define P74_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #74 assigned IVG #x   */
5558 
#define P75_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #75 assigned IVG #x   */
5559 
#define P76_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #76 assigned IVG #x   */
5560 
#define P77_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #77 assigned IVG #x   */
5561 
#define P78_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #78 assigned IVG #x   */
5562 
#define P79_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #79 assigned IVG #x   */
5563 
 
5564 
/* SIC_IAR8 Macros */
5565 
#define P80_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #80 assigned IVG #x   */
5566 
#define P81_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #81 assigned IVG #x   */
5567 
#define P82_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #82 assigned IVG #x   */
5568 
#define P83_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #83 assigned IVG #x   */
5569 
#define P84_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #84 assigned IVG #x   */
5570 
#define P85_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #85 assigned IVG #x   */
5571 
#define P86_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #86 assigned IVG #x   */
5572 
#define P87_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #87 assigned IVG #x   */
5573 
 
5574 
/* SIC_IAR9 Macros */
5575 
#define P88_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #88 assigned IVG #x   */
5576 
#define P89_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #89 assigned IVG #x   */
5577 
#define P90_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #90 assigned IVG #x   */
5578 
#define P91_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #91 assigned IVG #x   */
5579 
#define P92_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #92 assigned IVG #x   */
5580 
#define P93_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #93 assigned IVG #x   */
5581 
#define P94_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #94 assigned IVG #x   */
5582 
#define P95_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #95 assigned IVG #x   */
5583 
 
5584 
 
5585 
/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
5586 
 
5587 
/* Bit masks for SPIx_CTL */
5588 
#define RDBR_CORE   0x0         /* RDBR Read Initiates, IRQ when RDBR Full */
5589 
#define TDBR_CORE   0x1         /* TDBR Write Initiates, IRQ when TDBR Empty */
5590 
#define RDBR_DMA    0x2         /* DMA Read, DMA Until FIFO Empty */
5591 
#define TDBR_DMA    0x3         /* DMA Write, DMA Until FIFO Full */
5592 
 
5593 
 
5594 
/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
5595 
 
5596 
/* Bit macros for TWIx_CONTROL */
5597 
#define SET_TWI_PRESCALE(x)     ( (x) & PRESCALE )
5598 
#define SET_TWI_DCNT(x)         ( ((x) << 0x6) & DCNT )
5599 
 
5600 
/* Bit masks for TWIx_INT_MASK */
5601 
#define SCLIM       0x8000      /* Serial Clock Interrupt */
5602 
#define nSCLIM      0x0
5603 
#define SDAIM       0x4000      /* Serial Data Interrupt */
5604 
#define nSDAIM      0x0
5605 
 
5606 
/* Bit masks for TWIx_INT_STAT */
5607 
#define SCLI        0x8000      /* Serial Clock Interrupt */
5608 
#define nSCLI       0x0
5609 
#define SDAI        0x4000      /* Serial Data Interrupt */
5610 
#define nSDAI       0x0
5611 
 
5612 
/* Bit macros for TWIx_MASTER_ADDR */
5613 
#define SET_TWI_ADDR(x)         ( (x) & 0x7F )
5614 
 
5615 
/* ********* WATCHDOG TIMER MASKS ******************** */
5616 
 
5617 
/* Watchdog Timer WDOG_CTL Register Masks */
5618 
#ifdef _MISRA_RULES
5619 
#define SET_WDEV(x)     (((x)<<1) & 0x0006u)     /* event generated on roll over */
5620 
#else
5621 
#define SET_WDEV(x)     (((x)<<1) & 0x0006)     /* event generated on roll over */
5622 
#endif /* _MISRA_RULES */
5623 
#define WDEV_RESET      0x0000                  /* generate reset event on roll over */
5624 
#define nWDEV_RESET     0x0
5625 
#define WDEV_NMI        0x0002                  /* generate NMI event on roll over */
5626 
#define nWDEV_NMI       0x0
5627 
#define WDEV_GPI        0x0004                  /* generate GP IRQ on roll over */
5628 
#define nWDEV_GPI       0x0
5629 
#define WDEV_NONE       0x0006                  /* no event on roll over */
5630 
#define WDDIS           0x0AD0                  /* disable watchdog */
5631 
 
5632 
/* RTC_SWCNT (RTC stopwatch count) Macros */
5633 
#define SET_SWCNT(x)    (x)
5634 
 
5635 
/* RTC_PREN Register Masks */
5636 
#define ENABLE_PRESCALE             PREN        /* Enable prescaler so RTC runs at 1 Hz */
5637 
 
5638 
/* RTC_ALARM Macro: z=day, y=hr, x=min, w=sec */
5639 
#ifdef _MISRA_RULES
5640 
#define SET_ALARM(z,y,x,w)  ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
5641 
#else
5642 
#define SET_ALARM(z,y,x,w)  ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
5643 
#endif /* _MISRA_RULES */
5644 
 
5645 
/* ************** UART CONTROLLER MASKS *************************/
5646 
/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
5647 
#define UARTDLL      0x00FF   /* Divisor Latch Low Byte */
5648 
#define UARTDLH      0xFF00   /* Divisor Latch High Byte */
5649 
 
5650 
 
5651 
/* ******************************************* */
5652 
/*     MULTI BIT MACRO ENUMERATIONS            */
5653 
/* ******************************************* */
5654 
 
5655 
/* CNT_COMMAND bit field options */
5656 
#define nW1LCNT_ZERO    0x0
5657 
#define nW1LCNT_MIN     0x0
5658 
#define nW1LCNT_MAX     0x0
5659 
 
5660 
#define nW1LMIN_ZERO    0x0
5661 
#define nW1LMIN_CNT     0x0
5662 
#define nW1LMIN_MAX     0x0
5663 
 
5664 
#define nW1LMAX_ZERO    0x0
5665 
#define nW1LMAX_CNT     0x0
5666 
#define nW1LMAX_MIN     0x0
5667 
 
5668 
#define W1ZMONCE        0x1000          /* write on to enable single zero marker. clear CNT_COUNT action (W1A/R) */
5669 
#define nW1ZMONCE       0x0
5670 
 
5671 
/* Bit macros for CNT_DEBOUNCE */
5672 
#ifdef _MISRA_RULES
5673 
#define SET_DPRESCALE(x)   ((x)&0x7u)    /* 0000: 1x -> 0111: 128x, 1xxx Reserved */
5674 
#else
5675 
#define SET_DPRESCALE(x)   ((x)&0x7)    /* 0000: 1x -> 0111: 128x, 1xxx Reserved */
5676 
#endif /* _MISRA_RULES */
5677 
 
5678 
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
5679 
#define                     MCMEM  MCMEN
5680 
#define                    nMCMEM  0x0
5681 
 
5682 
#ifdef _MISRA_RULES
5683 
#pragma diag(pop)
5684 
#endif /* _MISRA_RULES */
5685 
 
5686 
#endif /* _DEF_BF54X_H */
5687 
 

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