OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [newlib-1.18.0/] [newlib-1.18.0-or32-1.0rc1/] [libgloss/] [bfin/] [include/] [sys/] [exception.h] - Blame information for rev 345

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/*
2
 * The authors hereby grant permission to use, copy, modify, distribute,
3
 * and license this software and its documentation for any purpose, provided
4
 * that existing copyright notices are retained in all copies and that this
5
 * notice is included verbatim in any distributions. No written agreement,
6
 * license, or royalty fee is required for any of the authorized uses.
7
 * Modifications to this software may be copyrighted by their authors
8
 * and need not follow the licensing terms described here, provided that
9
 * the new terms are clearly indicated on the first page of each file where
10
 * they apply.
11
 */
12
 
13
#pragma once
14
#ifndef __NO_BUILTIN
15
#pragma system_header /* exception.h */
16
#endif
17
/************************************************************************
18
 *
19
 * exception.h
20
 *
21
 * Copyright (C) 2008, 2009 Analog Devices, Inc.
22
 *
23
 ************************************************************************/
24
 
25
#ifndef _EXCEPTION_H
26
#define _EXCEPTION_H
27
 
28
#ifdef _MISRA_RULES
29
#pragma diag(push)
30
#pragma diag(suppress:misra_rule_5_6)
31
#pragma diag(suppress:misra_rule_5_7)
32
#pragma diag(suppress:misra_rule_6_3)
33
#pragma diag(suppress:misra_rule_19_4)
34
#pragma diag(suppress:misra_rule_19_7)
35
#pragma diag(suppress:misra_rule_19_10)
36
#pragma diag(suppress:misra_rule_19_13)
37
#endif /* _MISRA_RULES */
38
 
39
 
40
 
41
/*
42
** Definitions for user-friendly interrupt handling.
43
*/
44
 
45
/*
46
** Memory-Mapped Registers (MMRs) - these record what causes address
47
** exceptions.
48
*/
49
 
50
#define EX_DATA_FAULT_STATUS    0xFFE00008
51
#define EX_DATA_FAULT_ADDR      0xFFE0000C
52
#define EX_CODE_FAULT_STATUS    0xFFE01008
53
#define EX_CODE_FAULT_ADDR      0xFFE0100C
54
 
55
/*
56
** Event Vector Table
57
*/
58
 
59
#define EX_EVENT_VECTOR_TABLE   0xFFE02000
60
 
61
/*
62
** Meaning of the various bits in EXCAUSE field in SEQSTAT register.
63
*/
64
 
65
#define EX_BITS         0x3F    /* All EXCAUSE bits */
66
#define EX_TYPE         0x30    /* The bits which define the type */
67
#define EX_DEBUG        0x10    /* If set, is a debug exception type */
68
#define EX_SYS          0x20    /* If set, is a system exception type */
69
                                /* If neither set, is from EXCPT instr */
70
 
71
#define EX_IS_DEBUG_EXCEPTION(E)        (((E)&EX_TYPE)==EX_DEBUG)
72
#define EX_IS_SYSTEM_EXCEPTION(E)       (((E)&EX_TYPE)==EX_SYS)
73
#define EX_IS_USER_EXCEPTION(E)         (((E)&EX_TYPE)==0)
74
 
75
/*
76
** Service exceptions continue from the instruction after the one
77
** that raised the exception.
78
** Error exceptions restart the instruction that raised the exception.
79
*/
80
 
81
#define EX_IS_SERVICE_EXCEPTION(E)      (!EX_IS_SYSTEM_EXCEPTION(E))
82
#define EX_IS_ERROR_EXCEPTION(E)        (EX_IS_SYSTEM_EXCEPTION(E))
83
 
84
#define EX_DB_SINGLE_STEP 0x10  /* Processor is single-stepping */
85
#define EX_DB_EMTRCOVRFLW 0x11  /* Emulation Trace buffer overflowed */
86
 
87
#define EX_SYS_UNDEFINSTR 0x21  /* Undefined instruction */
88
#define EX_SYS_ILLINSTRC  0x22  /* Illegal instruction combination */
89
#define EX_SYS_DCPLBPROT  0x23  /* Data CPLB Protection violation */
90
#define EX_SYS_DALIGN     0x24  /* Data access misaligned address violation */
91
#define EX_SYS_UNRECEVT   0x25  /* Unrecoverable event */
92
#define EX_SYS_DCPLBMISS  0x26  /* Data access CPLB Miss */
93
#define EX_SYS_DCPLBMHIT  0x27  /* Data access CPLB Multiple Hits */
94
#define EX_SYS_EMWATCHPT  0x28  /* Emulation watch point match */
95
#define EX_SYS_CACCESSEX  0x29  /* Code fetch access exception */
96
#define EX_SYS_CALIGN     0x2A  /* Attempted misaligned instr cache fetch */
97
#define EX_SYS_CCPLBPROT  0x2B  /* Code fetch CPLB Protection */
98
#define EX_SYS_CCPLBMISS  0x2C  /* CPLB miss on an instruction fetch */
99
#define EX_SYS_CCPLBMHIT  0x2D  /* Code fetch CPLB Multiple Hits */
100
#define EX_SYS_ILLUSESUP  0x2E  /* Illegal use of Supervisor Resource */
101
 
102
/*
103
** Meaning of the various bits in HWERRCAUSE in SEQSTAT
104
*/
105
 
106
#define EX_HWBITS (0x1F<<14)    /* bits 18:14 */
107
 
108
#if !defined(__ADSPLPBLACKFIN__)
109
#define EX_HW_NOMEM1    (0x16<<14)
110
#define EX_HW_NOMEM2    (0x17<<14)
111
#else
112
#define EX_HW_SYSMMR    (0x02<<14)
113
#define EX_HW_EXTMEM    (0x03<<14)
114
#endif
115
#define EX_HW_DMAHIT    (0x01<<14)
116
#define EX_HW_PERFMON (0x12<<14)
117
#define EX_HW_RAISE     (0x18<<14)
118
 
119
/*
120
** Meaning of the bits in DATA_FAULT_STATUS and CODE_FAULT_STATUS
121
*/
122
 
123
#define EX_DATA_FAULT_ILLADDR   (1<<19) /* non-existent memory */
124
#define EX_DATA_FAULT_DAG       (1<<18) /* 0=>DAG0, 1=>DAG1 */
125
#define EX_DATA_FAULT_USERSUPV  (1<<17) /* 0=>user mode, 1=> supervisor */
126
#define EX_DATA_FAULT_READWRITE (1<<16) /* 0=>read, 1=>write */
127
#define EX_DATA_FAULT_CPLB       0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */
128
 
129
#define EX_CODE_FAULT_ILLADDR   (1<<19) /* non-existent memory */
130
#define EX_CODE_FAULT_USERSUPV  (1<<17) /* 0=>user mode, 1=> supervisor */
131
#define EX_CODE_FAULT_CPLB       0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */
132
 
133
/*
134
** The kinds of interrupt that can occur. These are also the
135
** indices into the Event Vector Table.
136
*/
137
 
138
#ifdef __cplusplus
139
extern "C" {
140
#endif
141
 
142
typedef enum {
143
  ik_err=-1,
144
  ik_emulation,
145
  ik_reset,
146
  ik_nmi,
147
  ik_exception,
148
  ik_global_int_enable,
149
  ik_hardware_err,
150
  ik_timer,
151
  ik_ivg7,
152
  ik_ivg8,
153
  ik_ivg9,
154
  ik_ivg10,
155
  ik_ivg11,
156
  ik_ivg12,
157
  ik_ivg13,
158
  ik_ivg14,
159
  ik_ivg15,
160
  num_interrupt_kind
161
} interrupt_kind;
162
 
163
/*
164
** Structure for recording details of an exception or interrupt
165
** that has occurred.
166
*/
167
 
168
typedef struct {
169
  interrupt_kind kind;          /* whether interrupt, exception, etc. */
170
  int value;                    /* interrupt number, exception type, etc. */
171
  void *pc;                     /* PC at point where exception occurred */
172
  void *addr;                   /* if an address faulted, which one. */
173
  unsigned status;              /* if an address faulted, why. */
174
} interrupt_info;
175
 
176
/*
177
** Macro for defining an interrupt routine
178
*/
179
 
180
typedef void (*ex_handler_fn)();
181
 
182
#define EX_HANDLER(KIND,NAME) \
183
_Pragma(#KIND) \
184
void NAME (void)
185
 
186
#define EX_HANDLER_PROTO(KIND, NAME) EX_HANDLER(KIND, NAME)
187
 
188
#define EX_INTERRUPT_HANDLER(NAME)      EX_HANDLER(interrupt,NAME)
189
#define EX_EXCEPTION_HANDLER(NAME)      EX_HANDLER(exception,NAME)
190
#define EX_NMI_HANDLER(NAME)            EX_HANDLER(nmi,NAME)
191
#define EX_REENTRANT_HANDLER(NAME) \
192
_Pragma("interrupt_reentrant") \
193
EX_HANDLER(interrupt,NAME)
194
 
195
/*
196
** A convenience function for setting up the interrupt_info contents.
197
** Must be called from immediately with the interrupt handler.
198
*/
199
 
200
void get_interrupt_info(interrupt_kind int_kind, interrupt_info *int_info);
201
 
202
/*
203
** Diagnostics function for reporting unexpected events.
204
*/
205
 
206
void _ex_report_event(interrupt_info *int_info);
207
 
208
/*
209
** Register an interrupt handler within the EVT.
210
** Return previous value if there was one.
211
*/
212
ex_handler_fn register_handler(interrupt_kind int_kind, ex_handler_fn handler);
213
 
214
/*
215
** Some magic values for registering default and null handlers.
216
*/
217
 
218
#define EX_INT_DEFAULT ((ex_handler_fn)-1)
219
#define EX_INT_IGNORE  ((ex_handler_fn)0)
220
 
221
/*
222
** Extended function to register an interrupt handler within the EVT.
223
** Returns the old handler.
224
**
225
** If enabled == EX_INT_ALWAYS_ENABLE, install fn (if fn != EX_INT_IGNORE
226
** and fn != EX_INT_DISABLE), and then enable the interrupt in IMASK then
227
** return
228
**
229
** If fn == EX_INT_IGNORE, disable the interrupt
230
** If fn == EX_INT_DEFAULT, delete the handler entry in the EVT and disable
231
**   the interrupt in IMASK
232
** Otherwise, install the new interrupt handler.  Then,
233
**  If enabled == EX_INT_DISABLE, disable the interrupt in IMASK
234
**  If enabled == EX_INT_ENABLE, enable the interrupt in IMASK
235
**  otherwise leave the interrupt status alone.
236
*/
237
ex_handler_fn register_handler_ex(interrupt_kind kind, ex_handler_fn fn,
238
                                  int enable);
239
 
240
/* Constants for the enabled parameter of register_handler_ex */
241
#define EX_INT_DISABLE 0
242
#define EX_INT_ENABLE 1
243
#define EX_INT_KEEP_IMASK -1
244
#define EX_INT_ALWAYS_ENABLE 2
245
 
246
/*
247
** Allow the user to raise exceptions from C.
248
*/
249
 
250
int raise_interrupt(interrupt_kind kind, int which,
251
   int cmd, int arg1, int arg2);
252
 
253
#ifdef __cplusplus
254
  } /* extern "C" */
255
#endif
256
 
257
#ifdef _MISRA_RULES
258
#pragma diag(pop)
259
#endif /* _MISRA_RULES */
260
 
261
#endif /* _EXCEPTION_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.