OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [newlib-1.18.0/] [newlib-1.18.0-or32-1.0rc1/] [libgloss/] [mep/] [simsdram-crt0.S] - Blame information for rev 345

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
# Copyright (c) 2003  Red Hat, Inc. All rights reserved.
2
#
3
# This copyrighted material is made available to anyone wishing to use, modify,
4
# copy, or redistribute it subject to the terms and conditions of the BSD
5
# License.   This program is distributed in the hope that it will be useful,
6
# but WITHOUT ANY WARRANTY expressed or implied, including the implied
7
# warranties of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  A copy
8
# of this license is available at http://www.opensource.org/licenses. Any
9
# Red Hat trademarks that are incorporated in the source code or documentation
10
# are not subject to the BSD License and may only be used or replicated with
11
# the express permission of Red Hat, Inc.
12
#
13
# Toshiba Media Processor startup file (simsdram-crt0.S)
14
#
15
# Designed for user programs which put interrupt/exception vectors in sdram.
16
#
17
 
18
#define UseSDRAM
19
#include "sim-crt0.S"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.