OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [gnu-src/] [newlib-1.18.0/] [newlib-1.18.0-or32-1.0rc1/] [libgloss/] [microblaze/] [crt4.S] - Blame information for rev 345

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 207 jeremybenn
/* Copyright (c) 2001, 2009 Xilinx, Inc.  All rights reserved.
2
 
3
   Redistribution and use in source and binary forms, with or without
4
   modification, are permitted provided that the following conditions are
5
   met:
6
 
7
   1.  Redistributions source code must retain the above copyright notice,
8
   this list of conditions and the following disclaimer.
9
 
10
   2.  Redistributions in binary form must reproduce the above copyright
11
   notice, this list of conditions and the following disclaimer in the
12
   documentation and/or other materials provided with the distribution.
13
 
14
   3.  Neither the name of Xilinx nor the names of its contributors may be
15
   used to endorse or promote products derived from this software without
16
   specific prior written permission.
17
 
18
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS
19
   IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20
   TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
21
   PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22
   HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23
   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24
   TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
25
   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
26
   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
27
   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28
   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29
 
30
 
31
        MicroBlaze Vector Map for Xilkernel ELF process images
32
 
33
         Address                Vector type                 Label
34
         -------                -----------                 ------
35
 
36
        # 0x00 #                (-- IMM --)
37
        # 0x04 #                Reset                       (-- Don't Care --)
38
 
39
        # 0x08 #                (-- IMM --)
40
        # 0x0c #                Software Exception          (-- Don't Care --)
41
 
42
        # 0x10 #                (-- IMM --)
43
        # 0x14 #                Hardware Interrupt          (-- Don't Care --)
44
 
45
        # 0x18 #                (-- IMM --)
46
        # 0x1C #                Breakpoint Exception        (-- Don't Care --)
47
 
48
        # 0x20 #                (-- IMM --)
49
        # 0x24 #                Hardware Exception          (-- Don't Care --)
50
 
51
*/
52
 
53
 
54
        .section .text
55
        .globl _start
56
        .align 2
57
        .ent _start
58
        .type _start, @function
59
_start:
60
        la      r13, r0, _SDA_BASE_         /* Set the Small Data Anchors and the stack pointer */
61
        la      r2, r0, _SDA2_BASE_
62
        la      r1, r0, _stack-16           /* 16 bytes (4 words are needed by crtinit for args and link reg */
63
 
64
        brlid   r15, _crtinit               /* Initialize BSS and run program */
65
        nop
66
 
67
        brlid   r15, exit                   /* Call exit with the return value of main */
68
        addik   r5, r3, 0
69
 
70
        /* Control does not reach here */
71
 
72
        .end _start
73
 
74
 
75
/*
76
        _exit
77
        Our simple _exit
78
*/
79
        .globl _exit
80
        .align 2
81
        .ent _exit
82
        .type _exit, @function
83
_exit:
84
        brlid   r15,elf_process_exit
85
        nop
86
        .end _exit

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.