URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [gnu-src/] [newlib-1.18.0/] [newlib-1.18.0-or32-1.0rc1/] [newlib/] [libc/] [machine/] [xscale/] [strcpy.c] - Blame information for rev 345

Line No.	Rev	Author	Line
1	207	jeremybenn	`#if defined __thumb__`
2
3			`#include "../../string/strcpy.c"`
4
5			`#else`
6
7			`#include <string.h>`
8			`#include "xscale.h"`
9
10			`char *`
11			`strcpy (char dest, const char src)`
12			`{`
13			`char *dest0 = dest;`
14
15			`asm (PRELOADSTR ("%0") : : "r" (src));`
16
17			`#ifndef __OPTIMIZE_SIZE__`
18			`if (((long)src & 3) == ((long)dest & 3))`
19			`{`
20			`/* Skip unaligned part. */`
21			`while ((long)src & 3)`
22			`{`
23			`if (! (dest++ = src++))`
24			`return dest0;`
25			`}`
26
27			`/* Load two constants:`
28			`R4 = 0xfefefeff [ == ~(0x80808080 << 1) ]`
29			`R5 = 0x80808080 */`
30
31			`asm ("mov r5, #0x80\n\`
32			`ldr r1, [%1, #0]\n\`
33			`add r5, r5, #0x8000\n\`
34			`add r5, r5, r5, lsl #16\n\`
35			`mvn r4, r5, lsl #1\n\`
36			`\n\`
37			`add r3, r1, r5\n\`
38			`bic r3, r3, r1\n\`
39			`ands r2, r3, r4\n\`
40			`bne 1f\n\`
41			`0:\n\`
42			`ldr r3, [%1, #0]\n\`
43			`ldr r1, [%1, #4]!\n\`
44			`" PRELOADSTR("%1") "\n\`
45			`str r3, [%0], #4\n\`
46			`add r2, r1, r4\n\`
47			`bic r2, r2, r1\n\`
48			`ands r3, r2, r5\n\`
49			`beq 0b\n\`
50			`1:"`
51			`: "=&r" (dest), "=&r" (src)`
52			`: "0" (dest), "1" (src)`
53			`: "r1", "r2", "r3", "r4", "r5", "memory", "cc");`
54			`}`
55			`#endif`
56
57			`while (dest++ = src++)`
58			`asm (PRELOADSTR ("%0") : : "r" (src));`
59			`return dest0;`
60			`}`
61
62			`#endif`