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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [build/] [doc/] [or1ksim.cps] - Blame information for rev 403

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Line No. Rev Author Line
1 19 jeremybenn
\initial {-}
2
\entry {\code {--cumulative}}{4}
3
\entry {\code {--debug-config}}{3}
4
\entry {\code {--enable-ethphy}}{2}
5
\entry {\code {--enable-mprofile}}{3}
6
\entry {\code {--enable-profile}}{3}
7
\entry {\code {--file}}{3}
8
\entry {\code {--filename}}{4}
9
\entry {\code {--generate}}{4}
10
\entry {\code {--group}}{4}
11
\entry {\code {--help}}{3}
12
\entry {\code {--help} (memory profiling utility)}{4}
13
\entry {\code {--help} (profiling utility)}{4}
14
\entry {\code {--interactive}}{3}
15
\entry {\code {--mode}}{4}
16
\entry {\code {--nosrv}}{3}
17
\entry {\code {--quiet}}{4}
18
\entry {\code {--srv}}{3}
19
\entry {\code {--version}}{3}
20
\entry {\code {--version} (memory profiling utility)}{4}
21
\entry {\code {--version} (profiling utility)}{4}
22
\entry {\code {-c}}{4}
23
\entry {\code {-d}}{3}
24
\entry {\code {-f}}{3, 4}
25
\entry {\code {-g}}{4}
26
\entry {\code {-h}}{3}
27
\entry {\code {-h} (memory profiling utility)}{4}
28
\entry {\code {-h} (profiling utility)}{4}
29
\entry {\code {-i}}{3}
30
\entry {\code {-m}}{4}
31
\entry {\code {-q}}{4}
32
\entry {\code {-v}}{3}
33
\entry {\code {-v} (memory profiling utility)}{4}
34
\entry {\code {-v} (profiling utility)}{4}
35
\initial {0}
36
\entry {0x00 UART VAPI sub-command (UART verification)}{30}
37
\entry {0x01 UART VAPI sub-command (UART verification)}{30}
38
\entry {0x02 UART VAPI sub-command (UART verification)}{30}
39
\entry {0x03 UART VAPI sub-command (UART verification)}{30}
40
\entry {0x04 UART VAPI sub-command (UART verification)}{30}
41
\initial {1}
42
\entry {\code {16550} (UART configuration)}{19}
43
\initial {A}
44
\entry {ATA/ATAPI configuration}{24}
45
\entry {ATA/ATAPI device configuration}{25}
46
\initial {B}
47
\entry {\code {base_vapi_id} (GPIO configuration - deprecated)}{22}
48
\entry {\code {baseaddr} (ATA/ATAPI configuration)}{24}
49
\entry {\code {baseaddr} (DMA configuration)}{20}
50
\entry {\code {baseaddr} (Ethernet configuration)}{20}
51
\entry {\code {baseaddr} (frame buffer configuration)}{23}
52
\entry {\code {baseaddr} (generic peripheral configuration)}{26}
53
\entry {\code {baseaddr} (GPIO configuration)}{21}
54
\entry {\code {baseaddr} (keyboard configuration)}{23}
55
\entry {\code {baseaddr} (memory configuration)}{13}
56
\entry {\code {baseaddr} (memory controller configuration)}{18}
57
\entry {\code {baseaddr} (UART configuration)}{18}
58
\entry {\code {baseaddr} (VGA configuration)}{22}
59
\entry {\code {blocksize} (cache configuration)}{15}
60
\entry {BPB configuration}{16}
61
\entry {branch prediction configuration}{16}
62
\entry {\code {break} (Interactive CLI)}{27}
63
\entry {breakpoint list (Interactive CLI)}{27}
64
\entry {breakpoint set/clear (Interactive CLI)}{27}
65
\entry {\code {breaks} (Interactive CLI)}{27}
66
\entry {\code {btic} (branch prediction configuration)}{16}
67
\entry {\code {byte_enabled} (generic peripheral configuration)}{26}
68
\initial {C}
69
\entry {cache configuration}{15}
70
\entry {\code {calling_convention} (CUC configuration)}{10}
71
\entry {\code {ce} (memory configuration)}{13}
72
\entry {\code {cfgr} (CPU configuration)}{11}
73
\entry {\code {channel} (UART configuration)}{18}
74
\entry {clear breakpoint (Interactive CLI)}{27}
75
\entry {\code {clkcycle} (simulator configuration)}{9}
76
\entry {\code {cm} (Interactive CLI)}{27}
77
\entry {command line for Or1ksim standalone use}{3}
78
\entry {\code {config}}{33}
79
\entry {\code {config.bpb}}{34}
80
\entry {\code {config.cpu}}{33}
81
\entry {\code {config.cuc}}{33}
82
\entry {\code {config.dc}}{33}
83
\entry {\code {config.debug}}{34}
84
\entry {\code {config.pic}}{34}
85
\entry {\code {config.pm}}{33}
86
\entry {\code {config.sim}}{33}
87
\entry {\code {config.vapi}}{33}
88
\entry {configuration dynamic structure}{34}
89
\entry {configuration file structure}{7}
90
\entry {configuration global structure}{33}
91
\entry {configuration info (Interactive CLI)}{28}
92
\entry {configuration of generic peripherals}{25}
93
\entry {configuration parameter setting (Interactive CLI)}{28}
94
\entry {configuring branch prediction}{16}
95
\entry {configuring data & instruction caches}{15}
96
\entry {configuring data & instruction MMUs}{14}
97
\entry {configuring DMA}{19}
98
\entry {configuring memory}{12}
99
\entry {configuring Or1ksim}{7}
100
\entry {configuring power management}{16}
101
\entry {configuring the ATA/ATAPI interfaces}{24}
102
\entry {configuring the behavior of Or1ksim}{8}
103
\entry {configuring the CPU}{11}
104
\entry {configuring the Custom Unit Compiler (CUC)}{10}
105
\entry {configuring the debug unit and interface to external debuggers}{17}
106
\entry {configuring the Ethernet interface}{20}
107
\entry {configuring the frame buffer}{22}
108
\entry {configuring the GPIO}{21}
109
\entry {configuring the interrupt controller}{15}
110
\entry {configuring the keyboard interface}{23}
111
\entry {configuring the memory controller}{17}
112
\entry {configuring the processor}{11}
113
\entry {configuring the PS2 interface}{23}
114
\entry {configuring the UART}{18}
115
\entry {configuring the Verification API (VAPI)}{9}
116
\entry {configuring the VGA interface}{22}
117
\entry {copying memory (Interactive CLI)}{27}
118
\entry {CPU configuration}{11}
119
\entry {CUC configuration}{10}
120
\entry {Custom Unit Compiler (Interactive CLI)}{29}
121
\entry {Custom Unit Compiler Configuration}{10}
122
\initial {D}
123
\entry {data cache configuration}{15}
124
\entry {data MMU configuration}{14}
125
\entry {DCGE (power management register)}{16}
126
\entry {\code {debug} (Interactive CLI)}{28, 29}
127
\entry {\code {debug} (simulator configuration)}{8}
128
\entry {debug channel toggle (Interactive CLI)}{28}
129
\entry {debug interface configuration}{17}
130
\entry {debug mode toggle (Interactive CLI)}{28}
131
\entry {debug unit configuration}{17}
132
\entry {Debug Unit verification (VAPI)}{30}
133
\entry {\code {delayr} (memory configuration)}{13}
134
\entry {\code {delayw} (memory configuration)}{14}
135
\entry {\code {dependstats} (CPU configuration)}{12}
136
\entry {\code {dev_id} (ATA/ATAPI configuration)}{24}
137
\entry {disassemble (Interactive CLI)}{27}
138
\entry {disc interface configuration}{24}
139
\entry {disc interface device configuration}{25}
140
\entry {display interface configuration}{22}
141
\entry {displaying memory (Interactive CLI)}{27}
142
\entry {displaying registers (Interactive CLI)}{27}
143
\entry {\code {dm} (Interactive CLI)}{27}
144
\entry {\code {dma} (Ethernet configuration)}{20}
145
\entry {DMA configuration}{19}
146
\entry {DMA verification (VAPI)}{30}
147
\entry {\code {dma_mode0_td} (ATA/ATAPI configuration)}{24}
148
\entry {\code {dma_mode0_teoc} (ATA/ATAPI configuration)}{24}
149
\entry {\code {dma_mode0_tm} (ATA/ATAPI configuration)}{24}
150
\entry {DME (power management register)}{16}
151
\entry {DMMU configuration}{14}
152
\entry {doze mode (power management register)}{16}
153
\entry {\code {dv} (Interactive CLI)}{28}
154
\entry {dynamic clock gating (power management register)}{16}
155
\entry {dynamic ports, use of}{10}
156
\initial {E}
157
\entry {\code {edge_trigger} (interrupt controller)}{16}
158
\entry {\code {enable_bursts} (CUC configuration)}{10}
159
\entry {\code {enabled} (ATA/ATAPI configuration)}{24}
160
\entry {\code {enabled} (branch prediction configuration)}{16}
161
\entry {\code {enabled} (cache configuration)}{15}
162
\entry {\code {enabled} (debug interface configuration)}{17}
163
\entry {\code {enabled} (DMA configuration)}{20}
164
\entry {\code {enabled} (Ethernet configuration)}{20}
165
\entry {\code {enabled} (frame buffer configuration)}{22}
166
\entry {\code {enabled} (generic peripheral configuration)}{26}
167
\entry {\code {enabled} (GPIO configuration)}{21}
168
\entry {\code {enabled} (interrupt controller)}{16}
169
\entry {\code {enabled} (keyboard configuration)}{23}
170
\entry {\code {enabled} (memory controller configuration)}{18}
171
\entry {\code {enabled} (MMU configuration)}{14}
172
\entry {\code {enabled} (power management configuration)}{16}
173
\entry {\code {enabled} (UART configuration)}{18}
174
\entry {\code {enabled} (verification API configuration)}{10}
175
\entry {\code {enabled} (VGA configuration)}{22}
176
\entry {enabling Ethernet via socket}{2}
177
\entry {\code {entrysize} (MMU configuration)}{14}
178
\entry {\code {ETH_VAPI_CTRL} (Ethernet verification)}{31}
179
\entry {\code {ETH_VAPI_DATA} (Ethernet verification)}{31}
180
\entry {Ethernet configuration}{20}
181
\entry {Ethernet verification (VAPI)}{30}
182
\entry {Ethernet via socket, enabling}{2}
183
\entry {\code {exe_log} (simulator configuration)}{9}
184
\entry {\code {exe_log_end} (simulator configuration)}{9}
185
\entry {\code {exe_log_file} (simulator configuration)}{9}
186
\entry {\code {exe_log_fn} (simulator configuration - deprecated)}{9}
187
\entry {\code {exe_log_marker} (simulator configuration)}{9}
188
\entry {\code {exe_log_start} (simulator configuration)}{9}
189
\entry {\code {exe_log_type} (simulator configuration)}{9}
190
\entry {\code {exe_log_type=default} (simulator configuration)}{9}
191
\entry {\code {exe_log_type=hardware} (simulator configuration)}{9}
192
\entry {\code {exe_log_type=simple} (simulator configuration)}{9}
193
\entry {\code {exe_log_type=software} (simulator configuration)}{9}
194
\entry {executing code (Interactive CLI)}{27}
195
\entry {execution history (Interactive CLI)}{27}
196
\initial {F}
197
\entry {\code {file} (ATA/ATAPI device configuration)}{25}
198
\entry {\code {file} (keyboard configuration)}{23}
199
\entry {\code {filename} (frame buffer configuration - deprecated)}{23}
200
\entry {\code {filename} (VGA configuration - deprecated)}{22}
201
\entry {\code {firmware} (ATA/ATAPI device configuration)}{25}
202
\entry {frame buffer configuration}{22}
203
\initial {G}
204
\entry {\code {gdb_enabled} (debug interface configuration)}{17}
205
\entry {generic peripheral configuration}{25}
206
\entry {GPIO configuration}{21}
207
\entry {GPIO verification (VAPI)}{31}
208
\entry {\code {GPIO_VAPI_AUX} (GPIO verification)}{31}
209
\entry {\code {GPIO_VAPI_CLOCK} (GPIO verification)}{31}
210
\entry {\code {GPIO_VAPI_CTRL} (GPIO verification)}{31}
211
\entry {\code {GPIO_VAPI_DATA} (GPIO verification)}{31}
212
\entry {\code {GPIO_VAPI_INTE} (GPIO verification)}{31}
213
\entry {\code {GPIO_VAPI_PTRIG} (GPIO verification)}{31}
214
\entry {\code {GPIO_VAPI_RGPIO} (GPIO verification)}{31}
215
\initial {H}
216
\entry {\code {hazards} (CPU configuration)}{12}
217
\entry {\code {heads} (ATA/ATAPI device configuration)}{25}
218
\entry {\code {help} (Interactive CLI)}{29}
219
\entry {hexadecimal memory dump (Interactive CLI)}{28}
220
\entry {\code {hide_device_id} (verification API configuration)}{10}
221
\entry {\code {hist} (Interactive CLI)}{27}
222
\entry {\code {history} (simulator configuration)}{8}
223
\entry {history of execution (Interactive CLI)}{27}
224
\entry {\code {hitdelay} (branch prediction configuration)}{16}
225
\entry {\code {hitdelay} (instruction cache configuration)}{15}
226
\entry {\code {hitdelay} (MMU configuration)}{14}
227
\entry {\code {hw_enabled} (generic peripheral configuration)}{26}
228
\initial {I}
229
\entry {IMMU configuration}{14}
230
\entry {\code {index} (memory controller configuration)}{18}
231
\entry {\code {info} (Interactive CLI)}{28}
232
\entry {installing Or1ksim}{2}
233
\entry {instruction cache configuration}{15}
234
\entry {instruction MMU configuration}{14}
235
\entry {instruction profiling for Or1ksim}{3}
236
\entry {instruction profiling utility (Interactive CLI)}{29}
237
\entry {internal debugging}{34}
238
\entry {interrupt controller configuration}{15}
239
\entry {\code {irq} (ATA/ATAPI configuration)}{24}
240
\entry {\code {irq} (DMA configuration)}{20}
241
\entry {\code {irq} (GPIO configuration)}{22}
242
\entry {\code {irq} (keyboard configuration)}{23}
243
\entry {\code {irq} (UART configuration)}{19}
244
\entry {\code {irq} (VGA configuration)}{22}
245
\initial {J}
246
\entry {\code {jitter} (UART configuration)}{19}
247
\initial {K}
248
\entry {keyboard configuration}{23}
249
\initial {L}
250
\entry {library version of Or1ksim}{5}
251
\entry {license for Or1ksim}{35}
252
\entry {list breakpoints (Interactive CLI)}{27}
253
\entry {\code {load_hitdelay} (data cache configuration)}{15}
254
\entry {\code {load_missdelay} (data cache configuration)}{15}
255
\entry {\code {log} (memory configuration)}{14}
256
\entry {\code {log_enabled} (verification API configuration)}{10}
257
\entry {\code {long}}{5}
258
\initial {M}
259
\entry {\code {mc} (memory configuration)}{13}
260
\entry {memory configuration}{12}
261
\entry {memory controller configuration}{17}
262
\entry {memory copying (Interactive CLI)}{27}
263
\entry {memory display (Interactive CLI)}{27}
264
\entry {memory dump, hexadecimal (Interactive CLI)}{28}
265
\entry {memory dump, Verilog (Interactive CLI)}{28}
266
\entry {memory patching (Interactive CLI)}{27}
267
\entry {memory profiling end address}{4}
268
\entry {memory profiling start address}{4}
269
\entry {memory profiling utility (Interactive CLI)}{29}
270
\entry {memory profiling version of Or1ksim}{4}
271
\entry {\code {memory_order} (CUC configuration)}{10}
272
\entry {\code {memory_order=exact} (CUC configuration)}{10}
273
\entry {\code {memory_order=none} (CUC configuration)}{10}
274
\entry {\code {memory_order=strong} (CUC configuration)}{10}
275
\entry {\code {memory_order=weak} (CUC configuration)}{10}
276
\entry {\code {missdelay} (branch prediction configuration)}{17}
277
\entry {\code {missdelay} (instruction cache configuration)}{15}
278
\entry {\code {missdelay} (MMU configuration)}{14}
279
\entry {MMU configuration}{14}
280
\entry {\code {mprof_file} (simulator configuration)}{8}
281
\entry {\code {mprof_fn} (simulator configuration - deprecated)}{8}
282
\entry {\code {mprofile} (Interactive CLI)}{29}
283
\entry {\code {mprofile} (simulator configuration)}{8}
284
\entry {\code {mwdma} (ATA/ATAPI device configuration)}{25}
285
\initial {N}
286
\entry {\code {name} (generic peripheral configuration)}{26}
287
\entry {\code {name} (memory configuration)}{13}
288
\entry {\code {no_multicycle} (CUC configuration)}{11}
289
\entry {\code {nsets} (cache configuration)}{15}
290
\entry {\code {nsets} (MMU configuration)}{14}
291
\entry {\code {nways} (cache configuration)}{15}
292
\entry {\code {nways} (MMU configuration)}{14}
293
\initial {O}
294
\entry {\code {or1ksim_get_time_period}}{5}
295
\entry {\code {or1ksim_init}}{5}
296
\entry {\code {or1ksim_interrupt}}{5}
297
\entry {\code {or1ksim_is_le}}{5}
298
\entry {\code {or1ksim_reset_duration}}{5}
299
\entry {\code {or1ksim_run}}{5}
300
\entry {\code {or1ksim_set_time_point}}{5}
301
\entry {output rediretion}{34}
302
\initial {P}
303
\entry {\code {packet} (ATA/ATAPI device configuration)}{25}
304
\entry {\code {pagesize} (MMU configuration)}{14}
305
\entry {patching memory (Interactive CLI)}{27}
306
\entry {patching registers (Interactive CLI)}{27}
307
\entry {patching the program counter (Interactive CLI)}{27}
308
\entry {\code {pattern} (memory configuration)}{13}
309
\entry {\code {pc} (Interactive CLI)}{27}
310
\entry {PIC configuration}{15}
311
\entry {\code {pio} (ATA/ATAPI device configuration)}{25}
312
\entry {\code {pio_mode0_t1} (ATA/ATAPI configuration)}{24}
313
\entry {\code {pio_mode0_t2} (ATA/ATAPI configuration)}{24}
314
\entry {\code {pio_mode0_t4} (ATA/ATAPI configuration)}{24}
315
\entry {\code {pio_mode0_teoc} (ATA/ATAPI configuration)}{24}
316
\entry {\code {pm} (Interactive CLI)}{27}
317
\entry {PMR - DGCE}{16}
318
\entry {PMR - DME}{16}
319
\entry {PMR - SDF}{16}
320
\entry {PMR - SME}{16}
321
\entry {PMR - SUME}{16}
322
\entry {PMU configuration}{16}
323
\entry {\code {poc} (memory controller configuration)}{18}
324
\entry {port range for TCP/IP}{10}
325
\entry {power management configuration}{16}
326
\entry {power management register, DGCE}{16}
327
\entry {power management register, DME}{16}
328
\entry {power management register, SDF}{16}
329
\entry {power management register, SME}{16}
330
\entry {power management register, SUME}{16}
331
\entry {\code {pr} (Interactive CLI)}{27}
332
\entry {private ports, use of}{10}
333
\entry {processor configuration}{11}
334
\entry {processor stall (Interactive CLI)}{27}
335
\entry {\code {prof_file} (simulator configuration)}{8}
336
\entry {\code {prof_fn} (simulator configuration - deprecated)}{8}
337
\entry {\code {profile} (simulator configuration)}{8}
338
\entry {profiling for Or1ksim}{3}
339
\entry {profiling utility (Interactive CLI)}{29}
340
\entry {program counter patching (Interactive CLI)}{27}
341
\entry {programmable interrupt controller configuration}{15}
342
\entry {PS2 configuration}{23}
343
\initial {Q}
344
\entry {\code {q} (Interactive CLI)}{27}
345
\entry {quitting (Interactive CLI)}{27}
346
\initial {R}
347
\entry {\code {r} (Interactive CLI)}{27}
348
\entry {\code {random_seed} (memory configuration)}{12}
349
\entry {\code {refresh_rate} (frame buffer configuration)}{23}
350
\entry {\code {refresh_rate} (VGA configuration)}{22}
351
\entry {\code {reg_sim_reset}}{34}
352
\entry {register display (Interactive CLI)}{27}
353
\entry {register patching (Interactive CLI)}{27}
354
\entry {\code {reset} (Interactive CLI)}{27}
355
\entry {reset hooks}{34}
356
\entry {reset the simulator (Interactive CLI)}{27}
357
\entry {\code {rev} (ATA/ATAPI configuration)}{24}
358
\entry {\code {rev} (CPU configuration)}{11}
359
\entry {\code {rtx_type} (Ethernet configuration)}{21}
360
\entry {\code {run} (Interactive CLI)}{27}
361
\entry {running code (Interactive CLI)}{27}
362
\entry {running Or1ksim}{3}
363
\entry {\code {runtime}}{34}
364
\entry {runtime global structure}{34}
365
\entry {\code {runtime.cpu}}{34}
366
\entry {\code {runtime.cpu.fout}}{34}
367
\entry {\code {runtime.cuc}}{34}
368
\entry {\code {runtime.vapi}}{34}
369
\entry {\code {rx_channel} (Ethernet configuration)}{21}
370
\entry {\code {rxfile} (Ethernet configuration)}{21}
371
\initial {S}
372
\entry {\code {sbp_bf_fwd} (branch prediction configuration)}{16}
373
\entry {\code {sbp_bnf_fwd} (branch prediction configuration)}{16}
374
\entry {\code {sbuf_len} (CPU configuration)}{12}
375
\entry {SDF (power management register)}{16}
376
\entry {\code {section ata}}{24}
377
\entry {\code {section bpb}}{16}
378
\entry {\code {section cpio}}{21}
379
\entry {\code {section cpu}}{11}
380
\entry {\code {section cuc}}{10}
381
\entry {\code {section dc}}{15}
382
\entry {\code {section debug}}{17}
383
\entry {\code {section dma}}{19}
384
\entry {\code {section dmmu}}{14}
385
\entry {\code {section ethernet}}{20}
386
\entry {\code {section fb}}{22}
387
\entry {\code {section generic}}{25}
388
\entry {\code {section ic}}{15}
389
\entry {\code {section immu}}{14}
390
\entry {\code {section kb}}{23}
391
\entry {\code {section mc}}{17}
392
\entry {\code {section memory}}{12}
393
\entry {\code {section pic}}{15}
394
\entry {\code {section pmu}}{16}
395
\entry {\code {section sim}}{8}
396
\entry {\code {section uart}}{18}
397
\entry {\code {section vapi}}{9}
398
\entry {\code {section vga}}{22}
399
\entry {\code {sections}}{34}
400
\entry {\code {sectors} (ATA/ATAPI device configuration)}{25}
401
\entry {\code {server_port} (debug interface configuration)}{17}
402
\entry {\code {server_port} (verification API configuration)}{10}
403
\entry {\code {set} (Interactive CLI)}{28}
404
\entry {set breakpoint (Interactive CLI)}{27}
405
\entry {\code {setdbch} (Interactive CLI)}{28}
406
\entry {simulator configuration}{8}
407
\entry {simulator configuration info (Interactive CLI)}{28}
408
\entry {simulator reset (Interactive CLI)}{27}
409
\entry {simulator statistics (Interactive CLI)}{28}
410
\entry {\code {size} (ATA/ATAPI device configuration)}{25}
411
\entry {\code {size} (generic peripheral configuration)}{26}
412
\entry {\code {size} (memory configuration)}{13}
413
\entry {sleep mode (power management register)}{16}
414
\entry {slow down factor (power management register)}{16}
415
\entry {SME (power management register)}{16}
416
\entry {\code {sockif} (Ethernet configuration)}{21}
417
\entry {\code {sr} (CPU configuration)}{11}
418
\entry {\code {stall} (Interactive CLI)}{27}
419
\entry {stall the processor (Interactive CLI)}{27}
420
\entry {statistics, simulation (Interactive CLI)}{28}
421
\entry {\code {stats} (Interactive CLI)}{28}
422
\entry {stepping code (Interactive CLI)}{27}
423
\entry {\code {store_hitdelay} (data cache configuration)}{15}
424
\entry {\code {store_missdelay} (data cache configuration)}{15}
425
\entry {SUME (power management register)}{16}
426
\entry {\code {superscalar} (CPU configuration)}{11}
427
\entry {suspend mode (power management register)}{16}
428
\initial {T}
429
\entry {\code {t} (Interactive CLI)}{27}
430
\entry {TCP/IP port range}{10}
431
\entry {TCP/IP port range for \code {or1ksim} service}{17}
432
\entry {\code {timings_file} (CUC configuration)}{11}
433
\entry {\code {timings_fn} (CUC configuration - deprecated)}{11}
434
\entry {toggle breakpoint (Interactive CLI)}{27}
435
\entry {toggle debug channels (Interactive CLI)}{28}
436
\entry {toggle debug mode (Interactive CLI)}{28}
437
\entry {\code {tx_channel} (Ethernet configuration)}{21}
438
\entry {\code {txfile} (Ethernet configuration)}{21}
439
\entry {\code {txfile} (frame buffer configuration)}{23}
440
\entry {\code {txfile} (VGA configuration)}{22}
441
\entry {\code {type} (ATA/ATAPI device configuration)}{25}
442
\entry {\code {type} (memory configuration)}{12}
443
\entry {\code {type=pattern} (memory configuration)}{12}
444
\entry {\code {type=random} (memory configuration)}{12}
445
\entry {\code {type=unknown} (memory configuration)}{12}
446
\entry {\code {type=zero} (memory configuration)}{12}
447
\initial {U}
448
\entry {UART configuration}{18}
449
\entry {UART I/O from/to a physical serial port}{19}
450
\entry {UART I/O from/to an \command {xterm}}{19}
451
\entry {UART I/O from/to files}{19}
452
\entry {UART I/O from/to open file descriptors}{19}
453
\entry {UART I/O from/to TCP/IP}{19}
454
\entry {UART verification (VAPI)}{30}
455
\entry {\code {upr} (CPU configuration)}{11}
456
\entry {\code {ustates} (cache configuration)}{15}
457
\entry {\code {ustates} (MMU configuration)}{14}
458
\initial {V}
459
\entry {VAPI configuration}{9}
460
\entry {VAPI for Debug Unit}{30}
461
\entry {VAPI for DMA}{30}
462
\entry {VAPI for Ethernet}{30}
463
\entry {VAPI for GPIO}{31}
464
\entry {VAPI for UART}{30}
465
\entry {\code {vapi_id} (debug interface configuration)}{17}
466
\entry {\code {vapi_id} (DMA configuration)}{20, 21}
467
\entry {\code {vapi_id} (GPIO configuration)}{22}
468
\entry {\code {vapi_id} (UART configuration)}{19}
469
\entry {\code {vapi_log_file} (verification API configuration)}{10}
470
\entry {\code {vapi_log_fn} (verification API configuration - deprecated)}{10}
471
\entry {\code {ver} (CPU configuration)}{11}
472
\entry {\code {verbose} (simulator configuration)}{8}
473
\entry {Verification API configuration}{9}
474
\entry {Verilog memory dump (Interactive CLI)}{28}
475
\entry {VGA configuration}{22}
476
\initial {W}
477
\entry {\code {word_enabled} (generic peripheral configuration)}{26}

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