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Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [testbench/] [cache.ld] - Blame information for rev 403

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MEMORY
        {
        except : ORIGIN = 0x00000000, LENGTH = 0x00002000
        flash  : ORIGIN = 0xf0000000, LENGTH = 0x00200000
        ram    : ORIGIN = 0x00002000, LENGTH = 0x001fe000
        }
 
SECTIONS
{
      .reset :
        {
        *(.reset)
         _src_beg = .;
        } > flash
      .text :
        AT ( ADDR (.reset) + SIZEOF (.reset) )
        {
        _dst_beg = .;
        *(.text)
        } > ram
      .data :
        AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )
        {
        *(.data)
        *(.rodata)
        _dst_end = .;
        } > ram
      .bss :
        {
        *(.bss)
        } > ram
      .stack  ALIGN(0x10) (NOLOAD):
        {
        *(.stack)
        _ram_end = .;
        } > ram
}

Line No.	Rev	Author	Line
1	19	jeremybenn	`MEMORY`
2			`{`
3			`except : ORIGIN = 0x00000000, LENGTH = 0x00002000`
4			`flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000`
5			`ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000`
6			`}`
7
8			`SECTIONS`
9			`{`
10			`.reset :`
11			`{`
12			`*(.reset)`
13			`_src_beg = .;`
14			`} > flash`
15			`.text :`
16			`AT ( ADDR (.reset) + SIZEOF (.reset) )`
17			`{`
18			`_dst_beg = .;`
19			`*(.text)`
20			`} > ram`
21			`.data :`
22			`AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )`
23			`{`
24			`*(.data)`
25			`*(.rodata)`
26			`_dst_end = .;`
27			`} > ram`
28			`.bss :`
29			`{`
30			`*(.bss)`
31			`} > ram`
32			`.stack ALIGN(0x10) (NOLOAD):`
33			`{`
34			`*(.stack)`
35			`_ram_end = .;`
36			`} > ram`
37			`}`

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Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [testbench/] [cache.ld] - Blame information for rev 403