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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [testbench/] [default.ld] - Blame information for rev 403

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Line No. Rev Author Line
1 19 jeremybenn 
MEMORY
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        {
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        except : ORIGIN = 0x00000000, LENGTH = 0x00002000
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        flash  : ORIGIN = 0xf0000000, LENGTH = 0x00200000
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        ram    : ORIGIN = 0x00002000, LENGTH = 0x001fe000
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        }
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SECTIONS
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{
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      .text :
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        {
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        *(.text)
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        *(.rodata)
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         _src_beg = .;
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        } > flash
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      .dummy ALIGN(0x4):
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        {
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         _src_beg = .;
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        } > flash
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      .except :
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        AT ( ADDR (.dummy))
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        {
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        _except_beg = .;
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        *(.except)
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        _except_end = .;
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        } > except
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      .data :
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        AT ( ADDR (.dummy) + SIZEOF (.except))
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        {
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        _dst_beg = .;
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        *(.data)
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        _dst_end = .;
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        } > ram
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      .bss :
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        {
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        *(.bss)
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        } > ram
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      .stack  ALIGN(0x10) (NOLOAD):
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        {
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        *(.stack)
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        _ram_end = .;
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        } > ram
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}

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