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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [testbench/] [except.S] - Blame information for rev 403

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/* Support file for c based tests */
#include "spr_defs.h"
#include "board.h"
 
#define reset _reset
 
#define MC_CSR          (0x00)
#define MC_POC          (0x04)
#define MC_BA_MASK      (0x08)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
 
        .section .stack
        .space 0x1000
_stack:
 
        .extern _reset_support
        .extern _c_reset
        .extern _excpt_buserr
        .extern _excpt_dpfault
        .extern _excpt_ipfault
        .extern _excpt_tick
        .extern _excpt_align
        .extern _excpt_illinsn
        .extern _excpt_int
        .extern _excpt_dtlbmiss
        .extern _excpt_itlbmiss
        .extern _excpt_range
        .extern _excpt_syscall
        .extern _excpt_break
        .extern _excpt_trap
 
 
              .section .except, "ax"
_buserr_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_buserr)
        l.ori   r10,r10,lo(_excpt_buserr)
        l.jr    r9
        l.nop
_buserr_vector_end:
 
_dpfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_dpfault)
        l.ori   r10,r10,lo(_excpt_dpfault)
        l.jr    r9
        l.nop
_dpfault_vector_end:
 
_ipfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_ipfault)
        l.ori   r10,r10,lo(_excpt_ipfault)
        l.jr    r9
        l.nop
_ipfault_vector_end:
 
_lpint_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_tick)
        l.ori   r10,r10,lo(_excpt_tick)
        l.jr    r9
        l.nop
_lpint_vector_end:
 
_align_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_align)
        l.ori   r10,r10,lo(_excpt_align)
        l.jr    r9
        l.nop
_align_vector_end:
 
_illinsn_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_illinsn)
        l.ori   r10,r10,lo(_excpt_illinsn)
        l.jr    r9
        l.nop
_illinsn_vector_end:
 
_hpint_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_int)
        l.ori   r10,r10,lo(_excpt_int)
        l.jr    r9
        l.nop
_hpint_vector_end:
 
_dtlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_dtlbmiss)
        l.ori   r10,r10,lo(_excpt_dtlbmiss)
        l.jr    r9
        l.nop
_dtlbmiss_vector_end:
 
_itlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_itlbmiss)
        l.ori   r10,r10,lo(_excpt_itlbmiss)
        l.jr    r9
        l.nop
_itlbmiss_vector_end:
 
_range_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_range)
        l.ori   r10,r10,lo(_excpt_range)
        l.jr    r9
        l.nop
_range_vector_end:
 
_syscall_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_syscall)
        l.ori   r10,r10,lo(_excpt_syscall)
        l.jr    r9
        l.nop
_syscall_vector_end:
 
_break_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_break)
        l.ori   r10,r10,lo(_excpt_break)
        l.jr    r9
        l.nop
_break_vector_end:
 
_trap_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_trap)
        l.ori   r10,r10,lo(_excpt_trap)
        l.jr    r9
        l.nop
_trap_vector_end:
 
              .section .text
 
        .org    0x100
_reset_vector:
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.nop
start:
        l.jal   _init_mc
        l.nop
 
        l.movhi r1,hi(_stack)
        l.ori   r1,r1,lo(_stack)
 
        /* Setup exception wrappers */
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.addi  r7,r0,0x100
 
1:      l.addi  r7,r7,0x100
        l.sfeqi r7,0xf00
        l.bf    1f
        l.nop
        l.addi  r4,r7,0
        l.addi  r5,r0,0
2:
        l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,1
        l.sfeqi r5,9
        l.bf    1b
        l.nop
        l.j     2b
        l.nop
1:
        /* Copy data section */
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
 
2:
 
        l.movhi r2,hi(reset)
        l.ori   r2,r2,lo(reset)
        l.jr    r2
        l.nop
 
_init_mc:
 
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
 
store_regs:
        l.sw    0x00(r1),r2
        l.sw    0x04(r1),r3
        l.sw    0x08(r1),r4
        l.sw    0x0c(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
end_except:
        l.lwz   r2,0x00(r1)
        l.lwz   r3,0x04(r1)
        l.lwz   r4,0x08(r1)
        l.lwz   r5,0x0c(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
        l.addi  r1,r1,120
        l.rfe
        l.nop

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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [testbench/] [except.S] - Blame information for rev 403

Line No.	Rev	Author	Line
1	19	jeremybenn	`/* Support file for c based tests */`
2			`#include "spr_defs.h"`
3			`#include "board.h"`
4
5			`#define reset _reset`
6
7			`#define MC_CSR (0x00)`
8			`#define MC_POC (0x04)`
9			`#define MC_BA_MASK (0x08)`
10			`#define MC_CSC(i) (0x10 + (i) * 8)`
11			`#define MC_TMS(i) (0x14 + (i) * 8)`
12
13			`.section .stack`
14			`.space 0x1000`
15			`_stack:`
16
17			`.extern _reset_support`
18			`.extern _c_reset`
19			`.extern _excpt_buserr`
20			`.extern _excpt_dpfault`
21			`.extern _excpt_ipfault`
22			`.extern _excpt_tick`
23			`.extern _excpt_align`
24			`.extern _excpt_illinsn`
25			`.extern _excpt_int`
26			`.extern _excpt_dtlbmiss`
27			`.extern _excpt_itlbmiss`
28			`.extern _excpt_range`
29			`.extern _excpt_syscall`
30			`.extern _excpt_break`
31			`.extern _excpt_trap`
32
33
34			`.section .except, "ax"`
35			`_buserr_vector:`
36			`l.addi r1,r1,-120`
37			`l.sw 0x1c(r1),r9`
38			`l.sw 0x20(r1),r10`
39			`l.movhi r9,hi(store_regs)`
40			`l.ori r9,r9,lo(store_regs)`
41			`l.movhi r10,hi(_excpt_buserr)`
42			`l.ori r10,r10,lo(_excpt_buserr)`
43			`l.jr r9`
44			`l.nop`
45			`_buserr_vector_end:`
46
47			`_dpfault_vector:`
48			`l.addi r1,r1,-120`
49			`l.sw 0x1c(r1),r9`
50			`l.sw 0x20(r1),r10`
51			`l.movhi r9,hi(store_regs)`
52			`l.ori r9,r9,lo(store_regs)`
53			`l.movhi r10,hi(_excpt_dpfault)`
54			`l.ori r10,r10,lo(_excpt_dpfault)`
55			`l.jr r9`
56			`l.nop`
57			`_dpfault_vector_end:`
58
59			`_ipfault_vector:`
60			`l.addi r1,r1,-120`
61			`l.sw 0x1c(r1),r9`
62			`l.sw 0x20(r1),r10`
63			`l.movhi r9,hi(store_regs)`
64			`l.ori r9,r9,lo(store_regs)`
65			`l.movhi r10,hi(_excpt_ipfault)`
66			`l.ori r10,r10,lo(_excpt_ipfault)`
67			`l.jr r9`
68			`l.nop`
69			`_ipfault_vector_end:`
70
71			`_lpint_vector:`
72			`l.addi r1,r1,-120`
73			`l.sw 0x1c(r1),r9`
74			`l.sw 0x20(r1),r10`
75			`l.movhi r9,hi(store_regs)`
76			`l.ori r9,r9,lo(store_regs)`
77			`l.movhi r10,hi(_excpt_tick)`
78			`l.ori r10,r10,lo(_excpt_tick)`
79			`l.jr r9`
80			`l.nop`
81			`_lpint_vector_end:`
82
83			`_align_vector:`
84			`l.addi r1,r1,-120`
85			`l.sw 0x1c(r1),r9`
86			`l.sw 0x20(r1),r10`
87			`l.movhi r9,hi(store_regs)`
88			`l.ori r9,r9,lo(store_regs)`
89			`l.movhi r10,hi(_excpt_align)`
90			`l.ori r10,r10,lo(_excpt_align)`
91			`l.jr r9`
92			`l.nop`
93			`_align_vector_end:`
94
95			`_illinsn_vector:`
96			`l.addi r1,r1,-120`
97			`l.sw 0x1c(r1),r9`
98			`l.sw 0x20(r1),r10`
99			`l.movhi r9,hi(store_regs)`
100			`l.ori r9,r9,lo(store_regs)`
101			`l.movhi r10,hi(_excpt_illinsn)`
102			`l.ori r10,r10,lo(_excpt_illinsn)`
103			`l.jr r9`
104			`l.nop`
105			`_illinsn_vector_end:`
106
107			`_hpint_vector:`
108			`l.addi r1,r1,-120`
109			`l.sw 0x1c(r1),r9`
110			`l.sw 0x20(r1),r10`
111			`l.movhi r9,hi(store_regs)`
112			`l.ori r9,r9,lo(store_regs)`
113			`l.movhi r10,hi(_excpt_int)`
114			`l.ori r10,r10,lo(_excpt_int)`
115			`l.jr r9`
116			`l.nop`
117			`_hpint_vector_end:`
118
119			`_dtlbmiss_vector:`
120			`l.addi r1,r1,-120`
121			`l.sw 0x1c(r1),r9`
122			`l.sw 0x20(r1),r10`
123			`l.movhi r9,hi(store_regs)`
124			`l.ori r9,r9,lo(store_regs)`
125			`l.movhi r10,hi(_excpt_dtlbmiss)`
126			`l.ori r10,r10,lo(_excpt_dtlbmiss)`
127			`l.jr r9`
128			`l.nop`
129			`_dtlbmiss_vector_end:`
130
131			`_itlbmiss_vector:`
132			`l.addi r1,r1,-120`
133			`l.sw 0x1c(r1),r9`
134			`l.sw 0x20(r1),r10`
135			`l.movhi r9,hi(store_regs)`
136			`l.ori r9,r9,lo(store_regs)`
137			`l.movhi r10,hi(_excpt_itlbmiss)`
138			`l.ori r10,r10,lo(_excpt_itlbmiss)`
139			`l.jr r9`
140			`l.nop`
141			`_itlbmiss_vector_end:`
142
143			`_range_vector:`
144			`l.addi r1,r1,-120`
145			`l.sw 0x1c(r1),r9`
146			`l.sw 0x20(r1),r10`
147			`l.movhi r9,hi(store_regs)`
148			`l.ori r9,r9,lo(store_regs)`
149			`l.movhi r10,hi(_excpt_range)`
150			`l.ori r10,r10,lo(_excpt_range)`
151			`l.jr r9`
152			`l.nop`
153			`_range_vector_end:`
154
155			`_syscall_vector:`
156			`l.addi r1,r1,-120`
157			`l.sw 0x1c(r1),r9`
158			`l.sw 0x20(r1),r10`
159			`l.movhi r9,hi(store_regs)`
160			`l.ori r9,r9,lo(store_regs)`
161			`l.movhi r10,hi(_excpt_syscall)`
162			`l.ori r10,r10,lo(_excpt_syscall)`
163			`l.jr r9`
164			`l.nop`
165			`_syscall_vector_end:`
166
167			`_break_vector:`
168			`l.addi r1,r1,-120`
169			`l.sw 0x1c(r1),r9`
170			`l.sw 0x20(r1),r10`
171			`l.movhi r9,hi(store_regs)`
172			`l.ori r9,r9,lo(store_regs)`
173			`l.movhi r10,hi(_excpt_break)`
174			`l.ori r10,r10,lo(_excpt_break)`
175			`l.jr r9`
176			`l.nop`
177			`_break_vector_end:`
178
179			`_trap_vector:`
180			`l.addi r1,r1,-120`
181			`l.sw 0x1c(r1),r9`
182			`l.sw 0x20(r1),r10`
183			`l.movhi r9,hi(store_regs)`
184			`l.ori r9,r9,lo(store_regs)`
185			`l.movhi r10,hi(_excpt_trap)`
186			`l.ori r10,r10,lo(_excpt_trap)`
187			`l.jr r9`
188			`l.nop`
189			`_trap_vector_end:`
190
191			`.section .text`
192
193			`.org 0x100`
194			`_reset_vector:`
195			`l.addi r2,r0,0x0`
196			`l.addi r3,r0,0x0`
197			`l.addi r4,r0,0x0`
198			`l.addi r5,r0,0x0`
199			`l.addi r6,r0,0x0`
200			`l.addi r7,r0,0x0`
201			`l.addi r8,r0,0x0`
202			`l.addi r9,r0,0x0`
203			`l.addi r10,r0,0x0`
204			`l.addi r11,r0,0x0`
205			`l.addi r12,r0,0x0`
206			`l.addi r13,r0,0x0`
207			`l.addi r14,r0,0x0`
208			`l.addi r15,r0,0x0`
209			`l.addi r16,r0,0x0`
210			`l.addi r17,r0,0x0`
211			`l.addi r18,r0,0x0`
212			`l.addi r19,r0,0x0`
213			`l.addi r20,r0,0x0`
214			`l.addi r21,r0,0x0`
215			`l.addi r22,r0,0x0`
216			`l.addi r23,r0,0x0`
217			`l.addi r24,r0,0x0`
218			`l.addi r25,r0,0x0`
219			`l.addi r26,r0,0x0`
220			`l.addi r27,r0,0x0`
221			`l.addi r28,r0,0x0`
222			`l.addi r29,r0,0x0`
223			`l.addi r30,r0,0x0`
224			`l.addi r31,r0,0x0`
225
226			`l.movhi r3,hi(start)`
227			`l.ori r3,r3,lo(start)`
228			`l.jr r3`
229			`l.nop`
230			`start:`
231			`l.jal _init_mc`
232			`l.nop`
233
234			`l.movhi r1,hi(_stack)`
235			`l.ori r1,r1,lo(_stack)`
236
237			`/* Setup exception wrappers */`
238			`l.movhi r3,hi(_src_beg)`
239			`l.ori r3,r3,lo(_src_beg)`
240			`l.addi r7,r0,0x100`
241
242			`1: l.addi r7,r7,0x100`
243			`l.sfeqi r7,0xf00`
244			`l.bf 1f`
245			`l.nop`
246			`l.addi r4,r7,0`
247			`l.addi r5,r0,0`
248			`2:`
249			`l.lwz r6,0(r3)`
250			`l.sw 0(r4),r6`
251			`l.addi r3,r3,4`
252			`l.addi r4,r4,4`
253			`l.addi r5,r5,1`
254			`l.sfeqi r5,9`
255			`l.bf 1b`
256			`l.nop`
257			`l.j 2b`
258			`l.nop`
259			`1:`
260			`/* Copy data section */`
261			`l.movhi r4,hi(_dst_beg)`
262			`l.ori r4,r4,lo(_dst_beg)`
263			`l.movhi r5,hi(_dst_end)`
264			`l.ori r5,r5,lo(_dst_end)`
265			`l.sub r5,r5,r4`
266			`l.sfeqi r5,0`
267			`l.bf 2f`
268			`l.nop`
269			`1: l.lwz r6,0(r3)`
270			`l.sw 0(r4),r6`
271			`l.addi r3,r3,4`
272			`l.addi r4,r4,4`
273			`l.addi r5,r5,-4`
274			`l.sfgtsi r5,0`
275			`l.bf 1b`
276			`l.nop`
277
278			`2:`
279
280			`l.movhi r2,hi(reset)`
281			`l.ori r2,r2,lo(reset)`
282			`l.jr r2`
283			`l.nop`
284
285			`_init_mc:`
286
287			`l.movhi r3,hi(MC_BASE_ADDR)`
288			`l.ori r3,r3,lo(MC_BASE_ADDR)`
289
290			`l.addi r4,r3,MC_CSC(0)`
291			`l.movhi r5,hi(FLASH_BASE_ADDR)`
292			`l.srai r5,r5,6`
293			`l.ori r5,r5,0x0025`
294			`l.sw 0(r4),r5`
295
296			`l.addi r4,r3,MC_TMS(0)`
297			`l.movhi r5,hi(FLASH_TMS_VAL)`
298			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
299			`l.sw 0(r4),r5`
300
301			`l.addi r4,r3,MC_BA_MASK`
302			`l.addi r5,r0,MC_MASK_VAL`
303			`l.sw 0(r4),r5`
304
305			`l.addi r4,r3,MC_CSR`
306			`l.movhi r5,hi(MC_CSR_VAL)`
307			`l.ori r5,r5,lo(MC_CSR_VAL)`
308			`l.sw 0(r4),r5`
309
310			`l.addi r4,r3,MC_TMS(1)`
311			`l.movhi r5,hi(SDRAM_TMS_VAL)`
312			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
313			`l.sw 0(r4),r5`
314
315			`l.addi r4,r3,MC_CSC(1)`
316			`l.movhi r5,hi(SDRAM_BASE_ADDR)`
317			`l.srai r5,r5,6`
318			`l.ori r5,r5,0x0411`
319			`l.sw 0(r4),r5`
320
321			`l.jr r9`
322			`l.nop`
323
324			`store_regs:`
325			`l.sw 0x00(r1),r2`
326			`l.sw 0x04(r1),r3`
327			`l.sw 0x08(r1),r4`
328			`l.sw 0x0c(r1),r5`
329			`l.sw 0x10(r1),r6`
330			`l.sw 0x14(r1),r7`
331			`l.sw 0x18(r1),r8`
332			`l.sw 0x24(r1),r11`
333			`l.sw 0x28(r1),r12`
334			`l.sw 0x2c(r1),r13`
335			`l.sw 0x30(r1),r14`
336			`l.sw 0x34(r1),r15`
337			`l.sw 0x38(r1),r16`
338			`l.sw 0x3c(r1),r17`
339			`l.sw 0x40(r1),r18`
340			`l.sw 0x44(r1),r19`
341			`l.sw 0x48(r1),r20`
342			`l.sw 0x4c(r1),r21`
343			`l.sw 0x50(r1),r22`
344			`l.sw 0x54(r1),r23`
345			`l.sw 0x58(r1),r24`
346			`l.sw 0x5c(r1),r25`
347			`l.sw 0x60(r1),r26`
348			`l.sw 0x64(r1),r27`
349			`l.sw 0x68(r1),r28`
350			`l.sw 0x6c(r1),r29`
351			`l.sw 0x70(r1),r30`
352			`l.sw 0x74(r1),r31`
353			`l.movhi r9,hi(end_except)`
354			`l.ori r9,r9,lo(end_except)`
355			`l.lwz r10,0(r10)`
356			`l.jr r10`
357			`l.nop`
358
359			`end_except:`
360			`l.lwz r2,0x00(r1)`
361			`l.lwz r3,0x04(r1)`
362			`l.lwz r4,0x08(r1)`
363			`l.lwz r5,0x0c(r1)`
364			`l.lwz r6,0x10(r1)`
365			`l.lwz r7,0x14(r1)`
366			`l.lwz r8,0x18(r1)`
367			`l.lwz r9,0x1c(r1)`
368			`l.lwz r10,0x20(r1)`
369			`l.lwz r11,0x24(r1)`
370			`l.lwz r12,0x28(r1)`
371			`l.lwz r13,0x2c(r1)`
372			`l.lwz r14,0x30(r1)`
373			`l.lwz r15,0x34(r1)`
374			`l.lwz r16,0x38(r1)`
375			`l.lwz r17,0x3c(r1)`
376			`l.lwz r18,0x40(r1)`
377			`l.lwz r19,0x44(r1)`
378			`l.lwz r20,0x48(r1)`
379			`l.lwz r21,0x4c(r1)`
380			`l.lwz r22,0x50(r1)`
381			`l.lwz r23,0x54(r1)`
382			`l.lwz r24,0x58(r1)`
383			`l.lwz r25,0x5c(r1)`
384			`l.lwz r26,0x60(r1)`
385			`l.lwz r27,0x64(r1)`
386			`l.lwz r28,0x68(r1)`
387			`l.lwz r29,0x6c(r1)`
388			`l.lwz r30,0x70(r1)`
389			`l.lwz r31,0x74(r1)`
390			`l.addi r1,r1,120`
391			`l.rfe`
392			`l.nop`