1 |
19 |
jeremybenn |
/* mc_dram.c - Memory Controller testbench dram test
|
2 |
|
|
Copyright (C) 2001 by Ivan Guzvinec, ivang@opencores.org
|
3 |
|
|
|
4 |
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
5 |
|
|
|
6 |
|
|
This program is free software; you can redistribute it and/or modify
|
7 |
|
|
it under the terms of the GNU General Public License as published by
|
8 |
|
|
the Free Software Foundation; either version 2 of the License, or
|
9 |
|
|
(at your option) any later version.
|
10 |
|
|
|
11 |
|
|
This program is distributed in the hope that it will be useful,
|
12 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
14 |
|
|
GNU General Public License for more details.
|
15 |
|
|
|
16 |
|
|
You should have received a copy of the GNU General Public License
|
17 |
|
|
along with this program; if not, write to the Free Software
|
18 |
|
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
19 |
|
|
*/
|
20 |
|
|
|
21 |
|
|
#include "support.h"
|
22 |
|
|
|
23 |
|
|
#include "mc_common.h"
|
24 |
|
|
#include "mc_dram.h"
|
25 |
|
|
#include "../peripheral/mc.h"
|
26 |
|
|
#include "../peripheral/gpio.h"
|
27 |
|
|
#include "../peripheral/fields.h"
|
28 |
|
|
|
29 |
|
|
#define T_ROW_SIZE 8
|
30 |
|
|
#define T_ROW_OFF 5
|
31 |
|
|
#define T_ROWS 25
|
32 |
|
|
#define T_GROUPS 3
|
33 |
|
|
|
34 |
|
|
typedef volatile unsigned long *REGISTER;
|
35 |
|
|
|
36 |
|
|
/*
|
37 |
|
|
unsigned long nRowSize = 0;
|
38 |
|
|
unsigned long nColumns = 0;
|
39 |
|
|
*/
|
40 |
|
|
REGISTER mc_poc = (unsigned long*)(MC_BASE + MC_POC);
|
41 |
|
|
REGISTER mc_csr = (unsigned long*)(MC_BASE + MC_CSR);
|
42 |
|
|
REGISTER mc_ba_mask = (unsigned long*)(MC_BASE + MC_BA_MASK);
|
43 |
|
|
|
44 |
|
|
REGISTER rgpio_out = (unsigned long*)(GPIO_BASE + RGPIO_OUT);
|
45 |
|
|
REGISTER rgpio_in = (unsigned long*)(GPIO_BASE + RGPIO_IN);
|
46 |
|
|
|
47 |
|
|
unsigned long lpoc;
|
48 |
|
|
unsigned char mc_cs;
|
49 |
|
|
|
50 |
|
|
unsigned long set_config()
|
51 |
|
|
{
|
52 |
|
|
REGISTER mc_csc;
|
53 |
|
|
unsigned char ch;
|
54 |
|
|
|
55 |
|
|
for (ch=0; ch<8; ch++) {
|
56 |
|
|
if (MC_SDRAM_CSMASK & (0x01 << ch) ) {
|
57 |
|
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
58 |
|
|
SET_FIELD(*mc_csc, MC_CSC, MS, mc_sdram_cs[ch].MS);
|
59 |
|
|
SET_FIELD(*mc_csc, MC_CSC, BW, mc_sdram_cs[ch].BW);
|
60 |
|
|
SET_FIELD(*mc_csc, MC_CSC, SEL, mc_sdram_cs[ch].M);
|
61 |
|
|
SET_FLAG(*mc_csc, MC_CSC, EN);
|
62 |
|
|
printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
|
63 |
|
|
}
|
64 |
|
|
}
|
65 |
|
|
|
66 |
|
|
return 0;
|
67 |
|
|
}
|
68 |
|
|
|
69 |
|
|
unsigned long get_config()
|
70 |
|
|
{
|
71 |
|
|
REGISTER mc_csc;
|
72 |
|
|
REGISTER mc_tms;
|
73 |
|
|
unsigned char ch;
|
74 |
|
|
|
75 |
|
|
mc_cs = 0;
|
76 |
|
|
for (ch=0; ch<8; ch++) {
|
77 |
|
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
78 |
|
|
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
|
79 |
|
|
if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 0) &&
|
80 |
|
|
(TEST_FLAG(*mc_csc, MC_CSC, EN) == 1 ) ) {
|
81 |
|
|
mc_sdram_cs[ch].MS = GET_FIELD(*mc_csc, MC_CSC, MS);
|
82 |
|
|
mc_sdram_cs[ch].BW = GET_FIELD(*mc_csc, MC_CSC, BW);
|
83 |
|
|
mc_sdram_cs[ch].M = GET_FIELD(*mc_csc, MC_CSC, SEL);
|
84 |
|
|
mc_cs |= (1 << ch);
|
85 |
|
|
|
86 |
|
|
printf("get_config(%d) : MS=0x%0lx, BW=0x%0lx, M=0x%0lx\n", ch,
|
87 |
|
|
mc_sdram_cs[ch].MS,
|
88 |
|
|
mc_sdram_cs[ch].BW,
|
89 |
|
|
mc_sdram_cs[ch].M);
|
90 |
|
|
}
|
91 |
|
|
}
|
92 |
|
|
printf("get_config() : cs=0x%0x\n", mc_cs);
|
93 |
|
|
return 0;
|
94 |
|
|
}
|
95 |
|
|
|
96 |
|
|
int main()
|
97 |
|
|
{
|
98 |
|
|
unsigned long ret;
|
99 |
|
|
unsigned char ch;
|
100 |
|
|
|
101 |
|
|
unsigned long j, i;
|
102 |
|
|
unsigned long test;
|
103 |
|
|
unsigned long gpio_pat = 0;
|
104 |
|
|
|
105 |
|
|
unsigned long nRowSize = 0;
|
106 |
|
|
unsigned long nRows = 0;
|
107 |
|
|
unsigned long nRowSh = 0;
|
108 |
|
|
unsigned long nRowGrp = 0;
|
109 |
|
|
|
110 |
|
|
unsigned long nAddress;
|
111 |
|
|
unsigned long mc_sel;
|
112 |
|
|
REGISTER mc_tms;
|
113 |
|
|
REGISTER mc_csc;
|
114 |
|
|
|
115 |
|
|
*rgpio_out = 0xFFFFFFFF;
|
116 |
|
|
|
117 |
|
|
/* set configuration */
|
118 |
|
|
randomin(7435);
|
119 |
|
|
lpoc = *mc_poc;
|
120 |
|
|
|
121 |
|
|
#ifdef MC_READ_CONF
|
122 |
|
|
if (get_config()) {
|
123 |
|
|
printf("Error reading MC configuration\n");
|
124 |
|
|
report(0x00000001);
|
125 |
|
|
return(1);
|
126 |
|
|
}
|
127 |
|
|
#else
|
128 |
|
|
mc_cs = MC_SDRAM_CSMASK;
|
129 |
|
|
#endif
|
130 |
|
|
|
131 |
|
|
for (ch=0; ch<8; ch++) {
|
132 |
|
|
if (mc_cs & (0x01 << ch) ) {
|
133 |
|
|
printf ("--- Begin Test on CS%d ---\n", ch);
|
134 |
|
|
|
135 |
|
|
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
|
136 |
|
|
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
|
137 |
|
|
mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
|
138 |
|
|
|
139 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, OM, 0); /*normal op*/
|
140 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, CL, 3); /*CAS*/
|
141 |
|
|
|
142 |
|
|
switch ( mc_sdram_cs[ch].BW + (3 * mc_sdram_cs[ch].MS) ) {
|
143 |
|
|
case 0:
|
144 |
|
|
case 4:
|
145 |
|
|
nRowSize = MC_SDRAM_ROWSIZE_0;
|
146 |
|
|
nRows = MC_SDRAM_ROWS_0;
|
147 |
|
|
nRowSh = MC_SDRAM_ROWSH_0; break;
|
148 |
|
|
case 1:
|
149 |
|
|
case 5:
|
150 |
|
|
nRowSize = MC_SDRAM_ROWSIZE_1;
|
151 |
|
|
nRows = MC_SDRAM_ROWS_1;
|
152 |
|
|
nRowSh = MC_SDRAM_ROWSH_1; break;
|
153 |
|
|
case 2:
|
154 |
|
|
nRowSize = MC_SDRAM_ROWSIZE_2;
|
155 |
|
|
nRows = MC_SDRAM_ROWS_2;
|
156 |
|
|
nRowSh = MC_SDRAM_ROWSH_2; break;
|
157 |
|
|
case 3:
|
158 |
|
|
nRowSize = MC_SDRAM_ROWSIZE_3;
|
159 |
|
|
nRows = MC_SDRAM_ROWS_3;
|
160 |
|
|
nRowSh = MC_SDRAM_ROWSH_3; break;
|
161 |
|
|
case 6:
|
162 |
|
|
nRowSize = MC_SDRAM_ROWSIZE_6;
|
163 |
|
|
nRows = MC_SDRAM_ROWS_6;
|
164 |
|
|
nRowSh = MC_SDRAM_ROWSH_6; break;
|
165 |
|
|
case 7:
|
166 |
|
|
nRowSize = MC_SDRAM_ROWSIZE_7;
|
167 |
|
|
nRows = MC_SDRAM_ROWS_7;
|
168 |
|
|
nRowSh = MC_SDRAM_ROWSH_7; break;
|
169 |
|
|
case 8:
|
170 |
|
|
nRowSize = MC_SDRAM_ROWSIZE_8;
|
171 |
|
|
nRows = MC_SDRAM_ROWS_8;
|
172 |
|
|
nRowSh = MC_SDRAM_ROWSH_8; break;
|
173 |
|
|
}
|
174 |
|
|
|
175 |
|
|
printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lX, rs = %lu, nr = %lu, sh = %lu, sel = %lu\n",
|
176 |
|
|
*mc_csc, *mc_tms, nRowSize, nRows, nRowSh, mc_sel);
|
177 |
|
|
|
178 |
|
|
/*nRows -= MC_SDRAM_ROW_OFF;*/
|
179 |
|
|
for (test=0; test<16; test++) {
|
180 |
|
|
/* configure MC*/
|
181 |
|
|
CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
|
182 |
|
|
CLEAR_FLAG(*mc_csc, MC_CSC, KRO); /* close row */
|
183 |
|
|
CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
|
184 |
|
|
CLEAR_FLAG(*mc_csc, MC_CSC, WP); /* write enable */
|
185 |
|
|
SET_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* single loc access */
|
186 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* sequential burst */
|
187 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 0); /* 1 */
|
188 |
|
|
switch (test) {
|
189 |
|
|
case 0:
|
190 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST0) != MC_SDRAM_TEST0)
|
191 |
|
|
continue;
|
192 |
|
|
break;
|
193 |
|
|
case 1:
|
194 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST1) != MC_SDRAM_TEST1)
|
195 |
|
|
continue;
|
196 |
|
|
SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
|
197 |
|
|
break;
|
198 |
|
|
case 2:
|
199 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST2) != MC_SDRAM_TEST2)
|
200 |
|
|
continue;
|
201 |
|
|
SET_FLAG(*mc_csc, MC_CSC, KRO); /* keep row */
|
202 |
|
|
break;
|
203 |
|
|
case 3:
|
204 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST3) != MC_SDRAM_TEST3)
|
205 |
|
|
continue;
|
206 |
|
|
SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row*/
|
207 |
|
|
break;
|
208 |
|
|
case 4:
|
209 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST4) != MC_SDRAM_TEST4)
|
210 |
|
|
continue;
|
211 |
|
|
SET_FLAG(*mc_csc, MC_CSC, WP); /* RO */
|
212 |
|
|
break;
|
213 |
|
|
case 5:
|
214 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST5) != MC_SDRAM_TEST5)
|
215 |
|
|
continue;
|
216 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
217 |
|
|
break;
|
218 |
|
|
case 6:
|
219 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST6) != MC_SDRAM_TEST6)
|
220 |
|
|
continue;
|
221 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
222 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
|
223 |
|
|
break;
|
224 |
|
|
case 7:
|
225 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST7) != MC_SDRAM_TEST7)
|
226 |
|
|
continue;
|
227 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
228 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 2); /* 4 */
|
229 |
|
|
break;
|
230 |
|
|
case 8:
|
231 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST8) != MC_SDRAM_TEST8)
|
232 |
|
|
continue;
|
233 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
234 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 3); /* 8 */
|
235 |
|
|
break;
|
236 |
|
|
case 9:
|
237 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST9) != MC_SDRAM_TEST9)
|
238 |
|
|
continue;
|
239 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
240 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 7); /* full page */
|
241 |
|
|
break;
|
242 |
|
|
case 10:
|
243 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST10) != MC_SDRAM_TEST10)
|
244 |
|
|
continue;
|
245 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
246 |
|
|
SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
247 |
|
|
break;
|
248 |
|
|
case 11:
|
249 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST11) != MC_SDRAM_TEST11)
|
250 |
|
|
continue;
|
251 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
252 |
|
|
SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
253 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
|
254 |
|
|
break;
|
255 |
|
|
case 12:
|
256 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST12) != MC_SDRAM_TEST12)
|
257 |
|
|
continue;
|
258 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
259 |
|
|
SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
260 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 2); /* 4 */
|
261 |
|
|
break;
|
262 |
|
|
case 13:
|
263 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST13) != MC_SDRAM_TEST13)
|
264 |
|
|
continue;
|
265 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
266 |
|
|
SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
267 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 3); /* 8 */
|
268 |
|
|
break;
|
269 |
|
|
case 14:
|
270 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST14) != MC_SDRAM_TEST14)
|
271 |
|
|
continue;
|
272 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
273 |
|
|
SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
274 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 7); /* fullrow */
|
275 |
|
|
break;
|
276 |
|
|
case 15:
|
277 |
|
|
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST15) != MC_SDRAM_TEST15)
|
278 |
|
|
continue;
|
279 |
|
|
SET_FLAG(*mc_csc, MC_CSC, KRO); /* keep row */
|
280 |
|
|
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
|
281 |
|
|
SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
|
282 |
|
|
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
|
283 |
|
|
break;
|
284 |
|
|
} /*switch test*/
|
285 |
|
|
|
286 |
|
|
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
|
287 |
|
|
|
288 |
|
|
if (MC_SDRAM_ACC & MC_SDRAM_SROW) {
|
289 |
|
|
/* perform sequential row access */
|
290 |
|
|
printf("Seuential Row\n");
|
291 |
|
|
for (j=0; j<T_ROWS; j++) {
|
292 |
|
|
nAddress = mc_sel << 21;
|
293 |
|
|
nAddress |= MC_MEM_BASE;
|
294 |
|
|
nAddress += ( (j + T_ROW_OFF) << nRowSh);
|
295 |
|
|
|
296 |
|
|
gpio_pat ^= 0x00000008;
|
297 |
|
|
*rgpio_out = gpio_pat;
|
298 |
|
|
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
|
299 |
|
|
|
300 |
|
|
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
|
301 |
|
|
|
302 |
|
|
if (ret) {
|
303 |
|
|
gpio_pat ^= 0x00000080;
|
304 |
|
|
*rgpio_out = gpio_pat;
|
305 |
|
|
report(ret);
|
306 |
|
|
return ret;
|
307 |
|
|
}
|
308 |
|
|
}
|
309 |
|
|
}
|
310 |
|
|
|
311 |
|
|
if (MC_SDRAM_ACC & MC_SDRAM_RROW) {
|
312 |
|
|
/* perform random row access */
|
313 |
|
|
printf("Random Row\n");
|
314 |
|
|
for (j=0; j<T_ROWS; j++) {
|
315 |
|
|
nAddress = mc_sel << 21;
|
316 |
|
|
nAddress |= MC_MEM_BASE;
|
317 |
|
|
nAddress += ( (T_ROW_OFF + random(nRows)) << nRowSh);
|
318 |
|
|
|
319 |
|
|
gpio_pat ^= 0x00000008;
|
320 |
|
|
*rgpio_out = gpio_pat;
|
321 |
|
|
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
|
322 |
|
|
|
323 |
|
|
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
|
324 |
|
|
|
325 |
|
|
if (ret) {
|
326 |
|
|
gpio_pat ^= 0x00000080;
|
327 |
|
|
*rgpio_out = gpio_pat;
|
328 |
|
|
report(ret);
|
329 |
|
|
return ret;
|
330 |
|
|
}
|
331 |
|
|
}
|
332 |
|
|
}
|
333 |
|
|
|
334 |
|
|
if (MC_SDRAM_ACC & MC_SDRAM_SGRP) {
|
335 |
|
|
/* perform sequential row in group access */
|
336 |
|
|
printf("Sequential Group ");
|
337 |
|
|
|
338 |
|
|
printf("Group Size = %d\n", MC_SDRAM_GROUPSIZE);
|
339 |
|
|
for (i=0; i<T_GROUPS; i++) {
|
340 |
|
|
nRowGrp = random(nRows - MC_SDRAM_GROUPSIZE) + T_ROW_OFF;
|
341 |
|
|
for (j=0; j<MC_SDRAM_GROUPSIZE; j++) {
|
342 |
|
|
nAddress = mc_sel << 21;
|
343 |
|
|
nAddress |= MC_MEM_BASE;
|
344 |
|
|
nAddress += ((nRowGrp+j) << nRowSh);
|
345 |
|
|
|
346 |
|
|
gpio_pat ^= 0x00000008;
|
347 |
|
|
*rgpio_out = gpio_pat;
|
348 |
|
|
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
|
349 |
|
|
|
350 |
|
|
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
|
351 |
|
|
|
352 |
|
|
if (ret) {
|
353 |
|
|
gpio_pat ^= 0x00000080;
|
354 |
|
|
*rgpio_out = gpio_pat;
|
355 |
|
|
report(ret);
|
356 |
|
|
return ret;
|
357 |
|
|
}
|
358 |
|
|
}
|
359 |
|
|
}
|
360 |
|
|
}
|
361 |
|
|
|
362 |
|
|
if (MC_SDRAM_ACC & MC_SDRAM_RGRP) {
|
363 |
|
|
/* perform random row in group access */
|
364 |
|
|
printf("Random Group ");
|
365 |
|
|
|
366 |
|
|
printf("Group Size = %d\n", MC_SDRAM_GROUPSIZE);
|
367 |
|
|
for (i=0; i<T_GROUPS; i++) {
|
368 |
|
|
nRowGrp = random(nRows - T_GROUPS) + T_ROW_OFF;
|
369 |
|
|
for (j=0; j<MC_SDRAM_GROUPSIZE; j++) {
|
370 |
|
|
nAddress = mc_sel << 21;
|
371 |
|
|
nAddress |= MC_MEM_BASE;
|
372 |
|
|
nAddress += ((nRowGrp + random(MC_SDRAM_GROUPSIZE)) << nRowSh);
|
373 |
|
|
|
374 |
|
|
gpio_pat ^= 0x00000008;
|
375 |
|
|
*rgpio_out = gpio_pat;
|
376 |
|
|
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
|
377 |
|
|
|
378 |
|
|
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
|
379 |
|
|
|
380 |
|
|
if (ret) {
|
381 |
|
|
gpio_pat ^= 0x00000080;
|
382 |
|
|
*rgpio_out = gpio_pat;
|
383 |
|
|
report(ret);
|
384 |
|
|
return ret;
|
385 |
|
|
}
|
386 |
|
|
}
|
387 |
|
|
}
|
388 |
|
|
} /*for groups*/
|
389 |
|
|
|
390 |
|
|
} /*for test*/
|
391 |
|
|
} /*if*/
|
392 |
|
|
} /*for CS*/
|
393 |
|
|
printf("--- End SDRAM tests ---\n");
|
394 |
|
|
report(0xDEADDEAD);
|
395 |
|
|
|
396 |
|
|
gpio_pat ^= 0x00000020;
|
397 |
|
|
*rgpio_out = gpio_pat;
|
398 |
|
|
|
399 |
|
|
return 0;
|
400 |
|
|
} /* main */
|