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[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.3.0/] [testbench/] [mmu.cfg] - Blame information for rev 403

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Line No. Rev Author Line
1 19 jeremybenn
section memory
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  /*random_seed = 12345
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  type = random*/
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  pattern = 0x00
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  type = unknown /* Fastest */
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  name = "RAM"
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  ce = 1
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  baseaddr = 0x00000000
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  size = 0x00200000
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  delayr = 1
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  delayw = 2
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end
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section memory
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  /*random_seed = 12345
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  type = random*/
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  pattern = 0x00
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  type = unknown /* Fastest */
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  name = "FLASH"
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  ce = 0
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  baseaddr = 0xf0000000
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  size = 0x00200000
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  delayr = 10
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  delayw = -1
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end
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section immu
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  enabled = 1
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  nsets = 64
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  nways = 1
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  ustates = 2
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  pagesize = 8192
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end
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section dmmu
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  enabled = 1
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  nsets = 64
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  nways = 1
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  ustates = 2
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  pagesize = 8192
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end
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section ic
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  enabled = 1
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  nsets = 256
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  nways = 1
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  ustates = 2
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  blocksize = 16
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end
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section dc
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  enabled = 1
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  nsets = 256
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  nways = 1
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  ustates = 2
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  blocksize = 16
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end
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section sim
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  /* verbose = 1 */
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  debug = 0
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  profile = 0
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  prof_fn = "sim.profile"
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  history = 1
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  /* iprompt = 0 */
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  exe_log = 0
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  exe_log_fn = "executed.log"
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end
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section mc
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  enabled = 1
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  baseaddr = 0x93000000
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  POC = 0x00000008                 /* Power on configuration register */
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end
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