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This is ../../doc/or1ksim.info, produced by makeinfo version 4.13 from
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../../doc/or1ksim.texi.
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4
INFO-DIR-SECTION Embedded development
5
START-INFO-DIR-ENTRY
6
* Or1ksim: (or32-uclinux-or1ksim).      The OpenRISC 1000 Architectural
7
                                        Simulator
8
END-INFO-DIR-ENTRY
9
 
10
This file documents the OpenRISC Architectural Simulator, Or1ksim.
11
 
12
Copyright (C) 2008, 2009 Embecosm Limited.
13
 
14
     Permission is granted to copy, distribute and/or modify this
15
     document under the terms of the GNU Free Documentation License,
16
     Version 1.2 or any later version published by the Free Software
17
     Foundation; with no Invariant Sections, with no Front-Cover Texts,
18
     and with no Back-Cover Texts.  A copy of the license is included
19
     in the section entitled "GNU Free Documentation License".
20
 
21

22
File: or1ksim.info,  Node: Top,  Next: Installation,  Up: (dir)
23
 
24
Scope of this Document
25
**********************
26
 
27
This document is the user guide for Or1ksim, the OpenRISC 1000
28
Architectural Simulator.
29
 
30
* Menu:
31
 
32
* Installation::
33
* Usage::
34
* Configuration::
35
* Interactive Command Line::
36
* Verification API::
37
 
38
* Code Internals::
39
 
40
* GNU Free Documentation License::  The license for this documentation
41
* Index::
42
 
43

44
File: or1ksim.info,  Node: Installation,  Next: Usage,  Prev: Top,  Up: Top
45
 
46
1 Installation
47
**************
48
 
49
Installation follows standard GNU protocols.
50
 
51
* Menu:
52
 
53
* Preparation::
54
* Configuring the Build::
55
* Build and Install::
56
* Known Issues::
57
 
58

59
File: or1ksim.info,  Node: Preparation,  Next: Configuring the Build,  Up: Installation
60
 
61
1.1 Preparation
62
===============
63
 
64
Unpack the software and create a _separate_ directory in which to build
65
it:
66
 
67 85 jeremybenn
     tar jxf or1ksim-0.3.1-2010-04-21.tar.bz2
68 19 jeremybenn
     mkdir builddir_or1ksim
69
     cd builddir_or1ksim
70
 
71

72
File: or1ksim.info,  Node: Configuring the Build,  Next: Build and Install,  Prev: Preparation,  Up: Installation
73
 
74
1.2 Configuring the Build
75
=========================
76
 
77
Configure the software using the `configure' script in the main
78
directory.
79
 
80
The most significant argument is `--target', which should specify the
81 82 jeremybenn
OpenRISC 1000 32-bit architecture.  If this argument is omitted, it will
82 19 jeremybenn
default to OpenRISC 1000 32-bit with a warning
83
 
84 85 jeremybenn
     ../or1ksim-0.3.1-2010-04-21/configure --target=or32-uclinux ...
85 19 jeremybenn
 
86
There are several other options available, many of which are standard
87 82 jeremybenn
to GNU `configure' scripts.  Use `configure --help' to see all the
88
options.  The most useful is `--prefix' to specify a directory for
89 19 jeremybenn
installation of the tools.
90
 
91
A number of Or1ksim features in the simulator do require enabling at
92 82 jeremybenn
configuration.  These include
93 19 jeremybenn
 
94
`--enable-profiling'
95
`--disable-profiling'
96 82 jeremybenn
     If enabled, Or1ksim is compiled for profiling with `gprof'.  This
97
     is disabled by default.  Only really of value for developers of
98 19 jeremybenn
     Or1ksim.
99
 
100
`--enable-execution=simple'
101
`--enable-execution=complex'
102
`--enable-execution=dynamic'
103
     Or1ksim has developed to improve functionality and performance.
104
     This feature allows three versions of Or1ksim to be built
105
 
106
    `--enable-execution=simple'
107
          Build the original simple interpreting simulator
108
 
109
    `--enable-execution=complex'
110 82 jeremybenn
          Build a more complex interpreting simulator.  Experiments
111
          suggest this is 50% faster than the simple simulator.  This
112
          is the default.
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114
    `--enable-execution=dynamic'
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          Build a dynamically compiling simulator.  This is the way
116
          many modern ISS are built.  This represents a work in
117
          progress.  Currently Or1ksim will compile, but segfaults if
118
          configured with this option.
119 19 jeremybenn
 
120
 
121
     The default is `--enable-execution=complex'.
122
 
123
`--enable-ethphy'
124
`--disable-ethphy'
125
     If enabled, this option allows the Ethernet to be simulated by
126
     connecting via a socket (the alternative reads and writes, from
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     and to files).  This must then be configured using the relevant
128
     fields in the `ethernet' section of the configuration file.  *Note
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     Ethernet Configuration: Ethernet Configuration.
130
 
131
     The default is for this to be disabled.
132
 
133
`--enable-range-stats'
134
`--disable-range-stats'
135
     If enabled, this option allows statistics to be collected to
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     analyse register access over time.  The default is for this to be
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     disabled.
138
 
139
`--enable-ov-flag'
140
`--disable-ov-flag'
141
     If enabled, this option causes instructions to set the overflow
142 82 jeremybenn
     flag.  The instructions affected by this are `l.add', `l.addc',
143 19 jeremybenn
     `l.addi', `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli',
144
     `l.or', `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra',
145
     `l.srai', `l.sub', `l.xor' and `l.xori'.
146
 
147
     The default is for this to be disabled.
148
 
149
          Caution: This appears a very dangerous option, to the extent
150 82 jeremybenn
          of arguably being a bug.  Whether or not flags are set is
151
          part of the OpenRISC 1000 architectural specification.
152
          Within the above list, the arithmetic instructions (`l.add',
153
          `l.addc', `l.addi', `l.div', `l.divu', `l.mul', `l.muli' and
154
          `l.sub'), together with `l.addic' which is missed out, set
155
          the overflow flag.  All the others (`l.and', `l.andi',
156
          `l.or', `l.ori', `l.sll', `l.slli', `l.srl', `l.srli',
157
          `l.sra', `l.srai', `l.xor' and `l.xori') do not.
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159
          Thus it is impossible to get correct behavior whichever way
160
          this option is set.
161
 
162
`--enable-arith-flag'
163
`--disable-arith-flag'
164
     If enabled, this option causes instructions to set the flag (`F'
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     bit) in the supervision register.  The instructions affected by
166 19 jeremybenn
     this are `l.add', `l.addc', `l.addi', `l.and' and `l.andi'.
167
 
168
     The default is for this to be disabled.
169
 
170
          Caution: As with `--enable-ov-flag', this appears another
171
          very dangerous option, to the extent of arguably being a bug.
172
          It also appears to be only partially implemented--why only
173
          the instructions early in the alphabet?
174
 
175
          Whether or not flags are set is part of the OpenRISC 1000
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          architectural specification.  The only flags which should set
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          this are the "set flag" instructions: `l.sfeq', `l.sfeqi',
178
          `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui', `l.sfgts',
179
          `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles', `l.sflesi',
180
          `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi', `l.sfltu',
181
          `l.sfltui', `l.sfne' and `l.sfnei'.
182
 
183
          The flags are correctly set (irrespective of
184
          `--enable-arith_flag').
185
 
186
          Correct behavior is thus achieved if this flag is not set.
187
          `--enable-arith-flag' should never be used.
188
 
189
 
190
`--enable-debug'
191
`--disable-debug'
192
     This is a feature of the Argtable2 package used to process
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     arguments.  If enabled, some debugging features are turned on in
194
     Argtable2.  It is provided for completeness, but there is no
195
     reason why this feature should ever be needed by any Or1ksim user.
196 19 jeremybenn
 
197 82 jeremybenn
`--enable-all-tests'
198
`--disable-all-tests'
199
     Some of the tests (at the time of writing just one) will not
200
     compile without error.  If enabled with this flag, all test
201
     programs will be compiled with `make check'.
202 19 jeremybenn
 
203 82 jeremybenn
     This flag is intended for those working on the test package, who
204
     wish to get the missing test(s) working.
205
 
206
 
207 19 jeremybenn

208
File: or1ksim.info,  Node: Build and Install,  Next: Known Issues,  Prev: Configuring the Build,  Up: Installation
209
 
210
1.3 Building and Installing
211
===========================
212
 
213 82 jeremybenn
Build the tool with:
214 19 jeremybenn
 
215
     make all
216 82 jeremybenn
 
217
If you have the OpenRISC tool chain and DejaGNU installed, you can
218
verify the tool as follows (otherwise omit this step):
219
 
220
     make check
221
 
222
Install the tool with:
223
 
224 19 jeremybenn
     make install
225
 
226
This will install the three variations of the Or1ksim tool,
227
`or32-uclinux-sim', `or32-uclinux-psim' and `or32-uclinux-mpsim', the
228
Or1ksim library, `libsim', the header file, `or1ksim.h' and this
229
documentation in `info' format.
230
 
231
     Note: Testing Or1ksim with `make check' is not yet supported.
232
 
233
The documentation may be created and installed in alternative formats
234
(PDF, Postscript, DVI, HTML) with for example:
235
 
236
     make pdf
237
     make install-pdf
238
 
239

240
File: or1ksim.info,  Node: Known Issues,  Prev: Build and Install,  Up: Installation
241
 
242
1.4 Known Problems and Issues
243
=============================
244
 
245 82 jeremybenn
The following problems and issues are known about with Or1ksim
246 85 jeremybenn
0.3.1-2010-04-21.  The OpenRISC tracker may be used to see the current
247 82 jeremybenn
state of these issues and to raise new problems and feature requests.
248
It may be found at
249
`http://www.opencores.org/ptracker.cgi/view/or1k/398'.
250 19 jeremybenn
 
251
   * The Supervision Register Little Endian Enable (LEE) bit is
252 82 jeremybenn
     ignored.  Or1ksim can be built for either little endian or big
253 19 jeremybenn
     endian use, but that behavior cannot be changed dynamically.
254
 
255
   * The NPC is a read/write register, but after being written it
256 82 jeremybenn
     clears the pipeline.  This means that if the processor is stalled,
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     the value should subsequently read back as 0, until the processor
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     is unstalled and able to refill its pipeline.  By default Or1ksim
259 19 jeremybenn
     always reports back the value of NPC, even when it has been
260
     written while stalled.
261
 
262
     There is now an option, `--strict-npc', which will enforce this
263 82 jeremybenn
     behavior.  At some stage in the future it will become the default
264 19 jeremybenn
     behavior, but for now it is an option, since its use will break
265
     GDB.
266
 
267
   * The memory components are given names in the configuration file.
268
     However there is currently no way for Or1ksim to report that name
269
     back to the user (for example to identify which memory block
270
     corresponds to a particular access).
271
 
272
   * Or1ksim allows the processor to be stalled (from the command
273 82 jeremybenn
     line), even if there is no debugger present.  This seems to be a
274 19 jeremybenn
     meaningless operation.
275
 
276
   * Or1ksim is not reentrant, so a program cannot instantiate multiple
277 82 jeremybenn
     instances using the library.  This is clearly a problem when
278
     considering multi-core applications.  However it stems from the
279
     original design, and can only be fixed by a complete rewrite.  The
280 19 jeremybenn
     entire source code uses static global constants liberally!
281
 
282
   * There is no support for floating point instructions currently in
283 82 jeremybenn
     Or1ksim.  However this is a work in progress and should be
284
     available in the future.
285 19 jeremybenn
 
286
 
287

288
File: or1ksim.info,  Node: Usage,  Next: Configuration,  Prev: Installation,  Up: Top
289
 
290
2 Usage
291
*******
292
 
293
* Menu:
294
 
295
* Standalone Simulator::
296
* Profiling Utility::
297
* Memory Profiling Utility::
298
* Simulator Library::
299
 
300

301
File: or1ksim.info,  Node: Standalone Simulator,  Next: Profiling Utility,  Up: Usage
302
 
303
2.1 Standalone Simulator
304
========================
305
 
306
The general form the standalone command is:
307
 
308
     or32-uclinux-sim [-vhi] [-f FILE] [--nosrv] [--srv=[N]] [-d STR]
309
                      [--enable-profile] [--enable-mprofile] [FILE]
310
 
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Many of the options have both a short and a long form.  For example
312
`-h' or `--help'.
313 19 jeremybenn
 
314
`-v'
315
`--version'
316
     Print out the version and copyright notice for Or1ksim and exit.
317
 
318
`-h'
319
`--help'
320
     Print out help about the command line options and what they mean.
321
 
322
`-f FILE'
323
`--file FILE'
324
     Read configuration commands from the specified file, looking first
325
     in the current directory, and otherwise in the `$HOME/.or1k'
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     directory.  If this argument is not specified, the file `sim.cfg'
327
     in those two locations is used.  Failure to find the file is a
328
     fatal error.  *Note Configuration: Configuration, for detailed
329
     information on configuring Or1ksim.
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331
`--nosrv'
332 82 jeremybenn
     Do not start up the debug server.  This overrides any setting
333
     specified in the configuration file.  This option may not be
334
     specified with `--srv'.  If it is, a rude message is printed and
335
     the `--nosrv' option is ignored.
336 19 jeremybenn
 
337
`--srv'
338
 
339
`--srv=N'
340 82 jeremybenn
     Start up the debug server.  If the parameter, N, is specified, use
341 19 jeremybenn
     that as the TCP/IP port for the server, otherwise a random value
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     from the private port range (41920-65535) will be used.  This
343
     option may not be specified with `--nosrv'.  If it is, a rude
344
     message is printed and the `--nosrv' option is ignored.
345 19 jeremybenn
 
346
`-d=CONFIG_STRING'
347
`--debug-config=CONFIG_STRING'
348 82 jeremybenn
     Enable selected debug messages in Or1ksim.  This parameter is for
349
     use by developers only, and is not covered further here.  See the
350 19 jeremybenn
     source code for more details.
351
 
352
`-i'
353
`--interactive'
354
     After starting, drop into the Or1ksim interactive command shell.
355
 
356
`--strict-npc'
357
     In real hardware, setting the next program counter (NPC, SPR 16),
358 82 jeremybenn
     flushes the processor pipeline.  The consequence of this is that
359
     until the pipeline refills, reading the NPC will return zero.
360
     This is typically the case when debugging, since the processor is
361 19 jeremybenn
     stalled.
362
 
363
     Historically, Or1ksim has always returned the value of the NPC,
364 82 jeremybenn
     irrespective of when it is changed.  If the `--strict-npc' option
365
     is used, then Or1ksim will mirror real hardware more accurately.
366
     If the NPC is changed while the processor is stalled, subsequent
367 19 jeremybenn
     reads of its value will return 0 until the processor is unstalled.
368
 
369
     This is not currently the default behavior, since tools such as
370
     GDB have been implemented assuming the historic Or1ksim behavior.
371
     However at some time in the future it will become the default.
372
 
373
`--enable-profile'
374
     Enable instruction profiling.
375
 
376
`--enable-mprofile'
377
     Enable memory profiling.
378
 
379
 
380

381
File: or1ksim.info,  Node: Profiling Utility,  Next: Memory Profiling Utility,  Prev: Standalone Simulator,  Up: Usage
382
 
383
2.2 Profiling Utility
384
=====================
385
 
386 82 jeremybenn
This utility analyses instruction profile data generated by Or1ksim.
387
It may be invoked as a standalone command, or from the Or1ksim CLI.
388
The general form the standalone command is:
389 19 jeremybenn
 
390
     or32-uclinux-profile [-vhcq] [-g=FILE]
391
 
392 82 jeremybenn
Many of the options have both a short and a long form.  For example
393
`-h' or `--help'.
394 19 jeremybenn
 
395
`-v'
396
`--version'
397
     Print out the version and copyright notice for the Or1ksim
398
     profiling utility and exit.
399
 
400
`-h'
401
`--help'
402
     Print out help about the command line options and what they mean.
403
 
404
`-c'
405
`--cumulative'
406
     Show cumulative sum of cycles in functions
407
 
408
`-q'
409
`--quiet'
410
     Suppress messages
411
 
412
`-g=FILE'
413
`--generate=FILE'
414 82 jeremybenn
     The data file to analyse.  If omitted, the default file,
415 19 jeremybenn
     `sim.profile' is used.
416
 
417
 
418

419
File: or1ksim.info,  Node: Memory Profiling Utility,  Next: Simulator Library,  Prev: Profiling Utility,  Up: Usage
420
 
421
2.3 Memory Profiling Utility
422
============================
423
 
424 82 jeremybenn
This utility analyses memory profile data generated by Or1ksim.  It may
425
be invoked as a standalone command, or from the Or1ksim CLI.  The
426 19 jeremybenn
general form the standalone command is:
427
 
428
     or32-uclinux-mprofile  [-vh] [-m=M] [-g=N] [-f=FILE] FROM TO
429
 
430 82 jeremybenn
Many of the options have both a short and a long form.  For example
431
`-h' or `--help'.
432 19 jeremybenn
 
433
`-v'
434
`--version'
435
     Print out the version and copyright notice for the Or1ksim memory
436
     profiling utility and exit.
437
 
438
`-h'
439
`--help'
440
     Print out help about the command line options and what they mean.
441
 
442
`-m=M'
443
`--mode=M'
444 82 jeremybenn
     Specify the mode out output.  Permitted options are
445 19 jeremybenn
 
446
    `detailed'
447
    `d'
448 82 jeremybenn
          Detailed output.  This is the default if no mode is specified.
449 19 jeremybenn
 
450
    `pretty'
451
    `p'
452
          Pretty printed output.
453
 
454
    `access'
455
    `a'
456
          Memory accesses only.
457
 
458
    `width'
459
    `w'
460
          Access width only.
461
 
462
 
463
`-g=N'
464
`--group=N'
465
     Group 2^n bits of successive addresses together.
466
 
467
`-f=FILE'
468
`--filename=FILE'
469 82 jeremybenn
     The data file to analyse.  If not specified, the default,
470 19 jeremybenn
     `sim.profile' is used.
471
 
472
`FROM'
473
`TO'
474
     FROM and TO are respectively the start and end address of the
475
     region of memory to be analysed.
476
 
477
 
478

479
File: or1ksim.info,  Node: Simulator Library,  Prev: Memory Profiling Utility,  Up: Usage
480
 
481
2.4 Simulator Library
482
=====================
483
 
484
Or1ksim may be used as a static of dynamic library, `libsim.a' or
485 82 jeremybenn
`libsim.so'.  When compiling with the static library, the flag, `-lsim'
486 19 jeremybenn
should be added to the link command.
487
 
488
The header file `or1ksim.h' contains appropriate declarations of the
489 82 jeremybenn
functions exported by the Or1ksim library.  These are:
490 19 jeremybenn
 
491
 -- `or1ksim.h': int or1ksim_init (const char *CONFIG_FILE, const char
492
          *IMAGE_FILE, void *CLASS_PTR, unsigned long int (*UPR)(void
493
          *CLASS_PTR, unsigned long int ADDR, unsigned long int MASK),
494
          void (*UPW)(void *CLASS_PTR, unsigned long int ADDR, unsigned
495
          long int MASK, unsigned long int WDATA))
496
     The initialization function is supplied with the name of a
497
     configuration file, CONFIG_FILE, an executable image, IMAGE_FILE,
498
     a pointer to the calling class, CLASS_PTR (since the library may
499
     be used from C++) and two up-call functions, one for reads, UPR,
500
     and one for writes, UPW.
501
 
502
     *Note Configuration: Configuration, for detailed information on
503
     configuring Or1ksim and the format of the configuration file.
504
 
505
     UPW is called for any write to an address external to the model
506 82 jeremybenn
     (determined by a `generic' section in the configuration file).
507
     UPR is called for any reads to an external address.  The CLASS_PTR
508
     is passed back with these upcalls, allowing the function to
509
     associate the call with the class which originally initialized the
510
     library.
511 19 jeremybenn
 
512
     MASK indicates which bytes in the word are to be written or read.
513 82 jeremybenn
     Bytes to be read/written should have 0xff set in MASK.  Otherwise
514 19 jeremybenn
     the byte should be zero.
515
 
516
     ADDR, MASK, WDATA and the result from UPR all use host-endianess,
517 82 jeremybenn
     _not_ model-endianess.  The internal Or1ksim routines manage all
518 19 jeremybenn
     the conversion.
519
 
520
 
521
 -- `or1ksim.h': int or1ksim_run (double DURATION)
522
     Run the simulator for the simulated duration specified (in
523
     seconds).
524
 
525
 
526
 -- `or1ksim.h': void or1ksim_reset_duration (double DURATION)
527
     Change the duration of a run specified in an earlier call to
528 82 jeremybenn
     `or1ksim_run'.  Typically this is called from an upcall, which
529 19 jeremybenn
     realizes it needs to change the duration of the run specified in
530
     the call to `or1ksim_run' that has been interrupted by the upcall.
531
 
532
     The time specified is the amount of time that the run must continue
533
     for (i.e the duration from _now_, not the duration from the
534
     original call to `or1ksim_run').
535
 
536
 
537
 -- `or1ksim.h': void or1ksim_set_time_point ()
538 82 jeremybenn
     Set a timing point.  For use with `or1ksim_get_time_period'.
539 19 jeremybenn
 
540
 
541
 -- `or1ksim.h': double or1ksim_get_time_period ()
542
     Return the simulated time (in seconds) that has elapsed since the
543
     last call to `or1ksim_set_time_point'.
544
 
545
 
546
 -- `or1ksim.h': int or1ksim_is_le ()
547
     Return 1 (logical true) if the Or1ksim simulation is
548
     little-endian, 0 otherwise.
549
 
550
 
551
 -- `or1ksim.h': unsigned long int or1ksim_clock_rate ()
552 82 jeremybenn
     Return the Or1ksim clock rate (in Hz).  This is the value
553
     specified in the configuration file.
554 19 jeremybenn
 
555
 
556
 -- `or1ksim.h': void or1ksim_interrupt (int I)
557 82 jeremybenn
     Generate an edge-triggered interrupt on interrupt line I.  The
558
     interrupt is then immediately cleared automatically.  A warning
559 19 jeremybenn
     will be generated and the interrupt request ignored if level
560
     sensitive interrupts have been configured with the programmable
561
     interrupt controller (*note Interrupt Configuration: Interrupt
562
     Configuration.).
563
 
564
 
565
 -- `or1ksim.h': void or1ksim_interrupt_set (int I)
566 82 jeremybenn
     Assert a level-triggered interrupt on interrupt line I.  The
567 19 jeremybenn
     interrupt must be cleared separately by an explicit call to
568 82 jeremybenn
     `or1ksim_interrupt_clear'.  A warning will be generated, and the
569 19 jeremybenn
     interrupt request ignored if edge sensitive interrupts have been
570
     configured with the programmable interrupt controller (*note
571
     Interrupt Configuration: Interrupt Configuration.).
572
 
573
 
574
 -- `or1ksim.h': void or1ksim_interrupt_clear (int I)
575
     Clear a level-triggered interrupt on interrupt line I, which was
576 82 jeremybenn
     previously asserted by a call to `or1ksim_interrupt_set'.  A
577 19 jeremybenn
     warning will be generated, and the interrupt request ignored if
578
     edge sensitive interrupts have been configured with the
579
     programmable interrupt controller (*note Interrupt Configuration:
580
     Interrupt Configuration.).
581
 
582
 
583
The libraries will be installed in the `lib' sub-directory of the main
584
installation directory (as specified with the `--prefix' option to the
585
`configure' script).
586
 
587
For example if the main installation directory is `/opt/or1ksim', the
588 82 jeremybenn
library will be found in the `/opt/or1ksim/lib' directory.  It is
589 19 jeremybenn
available as both a static library (`libsim.a') and a shared object
590
(`libsim.so').
591
 
592
To link against the library add the `-lsim' flag when linking and do
593
one of the following:
594
 
595
   * Add the library directory to the `LD_LIBRARY_PATH' environment
596 82 jeremybenn
     variable during execution.  For example:
597 19 jeremybenn
 
598
          export LD_LIBRARY_PATH=/opt/or1ksim/lib:$LD_LIBRARY_PATH
599
 
600
   * Add the library directory to the `LD_RUN_PATH' environment
601 82 jeremybenn
     variable during linking.  For example:
602 19 jeremybenn
 
603
          export LD_RUN_PATH=/opt/or1ksim/lib:$LD_RUN_PATH
604
 
605
   * Use the linker `--rpath' option and specify the library directory
606 82 jeremybenn
     when linking your program.  For example
607 19 jeremybenn
 
608 82 jeremybenn
          gcc ...  -Wl,--rpath -Wl,/opt/or1ksim/lib ...
609 19 jeremybenn
 
610
   * Add the library directory to `/etc/ld.so.conf'
611
 
612
 
613

614
File: or1ksim.info,  Node: Configuration,  Next: Interactive Command Line,  Prev: Usage,  Up: Top
615
 
616
3 Configuration
617
***************
618
 
619 82 jeremybenn
Or1ksim is configured through a configuration file.  This is specified
620 19 jeremybenn
through the `-f' parameter to the Or1ksim command, or passed as a
621 82 jeremybenn
string when initializing the Or1ksim library.  If no file is specified,
622
the default `sim.cfg' is used.  The file is looked for first in the
623 19 jeremybenn
current directory, then in the `$HOME/.or1k' directory of the user.
624
 
625
* Menu:
626
 
627
* Configuration File Format::
628
* Simulator Configuration::
629
* Core OpenRISC Configuration::
630
* Peripheral Configuration::
631
 
632

633
File: or1ksim.info,  Node: Configuration File Format,  Next: Simulator Configuration,  Up: Configuration
634
 
635
3.1 Configuration File Format
636
=============================
637
 
638
The configuration file is a plain text file.
639
 
640
* Menu:
641
 
642
* Configuration File Preprocessing::
643
* Configuration File Syntax::
644
 
645

646
File: or1ksim.info,  Node: Configuration File Preprocessing,  Next: Configuration File Syntax,  Up: Configuration File Format
647
 
648
3.1.1 Configuration File Preprocessing
649
--------------------------------------
650
 
651 82 jeremybenn
The configuration file may include C style comments (i.e.  delimited by
652 19 jeremybenn
`/*' and `*/').
653
 
654
Configure files may be included, using
655
 
656
     include FILENAME_TO_INCLUDE
657
 
658

659
File: or1ksim.info,  Node: Configuration File Syntax,  Prev: Configuration File Preprocessing,  Up: Configuration File Format
660
 
661
3.1.2 Configuration File Syntax
662
-------------------------------
663
 
664
The configuration file is divided into a series of sections, with the
665
general form:
666
 
667
     section SECTION_NAME
668
 
669
       ...
670
 
671
     end
672
 
673
Sections may also have sub-sections within them (currently only the
674
ATA/ATAPI disc interface uses this).
675
 
676
Within a section, or sub-section are a series of parameter assignments,
677
one per line, withe the general form
678
 
679
       PARAMETER = VALUE
680
 
681
Depending on the parameter, the value may be a named value (an
682
enumeration), an integer (specified in any format acceptable in C) or a
683 82 jeremybenn
string in doubple quotes.  For flag parameters, the value 1 is used to
684
mean "true" or "on" and the value "0" to mean "false" or "off".  An
685 19 jeremybenn
example from a memory section shows each of these
686
 
687
     section memory
688
       type    = random
689
       pattern = 0x00
690
       name    = "FLASH"
691
       ...
692
     end
693
 
694
Many parameters are optional and take reasonable default values if not
695 82 jeremybenn
specified.  However there are some parameters (for example the `ce'
696 19 jeremybenn
parameter in `section memory') _must_ be specified.
697
 
698
Subsections are introduced by a keyword, with a parameter value (no `='
699 82 jeremybenn
sign), and end with the same keyword prefixed by `end'.  Thus the
700 19 jeremybenn
ATA/ATAPI inteface (`section ata') has a `device' subsection, thus:
701
 
702
     section ata
703
       ...
704
       device 0
705
         type    = 1
706
         file = "FILENAME"
707
         ...
708
       enddevice
709
       ...
710
     end
711
 
712
Some sections (for example `section sim') should appear only once.
713
Others (for example `section memory' may appear multiple times.
714
 
715
Sections may be omitted, _unless they contain parameters which are
716 82 jeremybenn
non-optional_.  If the section describes a part of the simulator which
717 19 jeremybenn
is optional (for example whether it has a UART), then that
718 82 jeremybenn
functionality will not be provided.  If the section describes a part of
719 19 jeremybenn
the simulator which is not optional (for example the CPU), then all the
720
parameters of that section will take their default values.
721
 
722
All optional parts of the functionality are always described by
723
sections including a `enabled' parameter, which can be set to 0 to
724
ensure that functionality is explicitly omitted.
725
 
726
Even if a section is disabled, all its parameters will be read and
727 82 jeremybenn
stored.  This is helpful if the section is subsequently enabled from
728
the Or1ksim command line (*note Interactive Command Line: Interactive
729 19 jeremybenn
Command Line.).
730
 
731
     Tip: It generally clearer to have sections describing _all_
732
     components, with omitted functionality explicitly indicated by
733
     setting the `enabled' parameter to 0
734
 
735
The following sections describe the various configuration sections and
736
the parameters which may be set in each.
737
 
738

739
File: or1ksim.info,  Node: Simulator Configuration,  Next: Core OpenRISC Configuration,  Prev: Configuration File Format,  Up: Configuration
740
 
741
3.2 Simulator Configuration
742
===========================
743
 
744
* Menu:
745
 
746
* Simulator Behavior::
747
* Verification API Configuration::
748
* CUC Configuration::
749
 
750

751
File: or1ksim.info,  Node: Simulator Behavior,  Next: Verification API Configuration,  Up: Simulator Configuration
752
 
753
3.2.1 Simulator Behavior
754
------------------------
755
 
756 82 jeremybenn
Simulator behavior is described in `section sim'.  This section should
757
appear only once.  The following parameters may be specified.
758 19 jeremybenn
 
759
`verbose = 0|1'
760 82 jeremybenn
     If 1 (true), print extra messages.  Default 0.
761 19 jeremybenn
 
762
`debug = 0-9'
763 82 jeremybenn
 
764
     higher the value the greater the number of messages.  Default 0.
765
     Negative values will be treated as 0 (with a warning).  Values
766
     that are too large will be treated as 9 (with a warning).
767 19 jeremybenn
 
768
`profile = 0|1'
769
     If 1 (true) generate a profiling file using the file specified in
770 82 jeremybenn
     the `prof_file' parameter or otherwise `sim.profile'.  Default 0.
771 19 jeremybenn
 
772
`prof_file = ``FILENAME'''
773 82 jeremybenn
     Specifies the file to be used with the `profile' parameter.
774
     Default `sim.profile'.  For backwards compatibility, the
775
     alternative name `prof_fn' is supported for this parameter, but
776
     deprecated.
777 19 jeremybenn
 
778
`mprofile = 0|1'
779
     If 1 (true) generate a memory profiling file using the file
780
     specified in the `mprof_file' parameter or otherwise
781 82 jeremybenn
     `sim.mprofile'.  Default 0.
782 19 jeremybenn
 
783
`mprof_fn = ``FILENAME'''
784
     Specifies the file to be used with the `mprofile' parameter.
785 82 jeremybenn
     Default `sim.mprofile'.  For backwards compatibility, the
786 19 jeremybenn
     alternative name `mprof_fn' is supported for this parameter, but
787
     deprecated.
788
 
789
`history = 0|1'
790 82 jeremybenn
     If 1 (true) track execution flow.  Default 0.
791 19 jeremybenn
 
792
          Note: Setting this parameter seriously degrades performance.
793
 
794
          Note: If this execution flow tracking is enabled, then
795
          `dependstats' must be enabled in the CPU configuration
796
          section (*note CPU Configuration: CPU Configuration.).
797
 
798
`exe_log = 0|1'
799 82 jeremybenn
     If 1 (true), generate an execution log.  Log is written to the
800
     file specified in parameter `exe_log_file'.  Default 0.
801 19 jeremybenn
 
802
          Note: Setting this parameter seriously degrades performance.
803
 
804
`exe_log_type = default|hardware|simple|software'
805
     Type of execution log to produce.
806
 
807
    `default'
808 82 jeremybenn
          Produce default output for the execution log.  In the current
809 19 jeremybenn
          implementation this is the equivalent of `hardware'.
810
 
811
    `hardware'
812
          After each instruction execution, log the number of
813
          instructions executed so far, the next instruction to execute
814
          (in hex), the general purpose registers (GPRs), status
815
          register, exception program counter, exception, effective
816
          address register and exception status register.
817
 
818
    `simple'
819
          After each instruction execution, log the number of
820
          instructions executed so far and the next instruction to
821
          execute, symbolically disassembled.
822
 
823
    `software'
824
          After each instruction execution, log the number of
825
          instructions executed so far and the next instruction to
826 82 jeremybenn
          execute, symbolically disassembled.  Also show the value of
827 19 jeremybenn
          each operand to the instruction.
828
 
829
 
830 82 jeremybenn
     Default value `hardware'.  Any unrecognized keyword (case
831 19 jeremybenn
     insensitive) will be treated as the default with a warning.
832
 
833
          Note: Execution logs can be _very_ big.
834
 
835
`exe_log_start = VALUE'
836 82 jeremybenn
     Address of the first instruction to start logging.  Default 0.
837 19 jeremybenn
 
838
`exe_log_end = VALUE'
839 82 jeremybenn
     Address of the last instruction to log.  Default no limit (i.e
840
     once started logging will continue until the simulator exits).
841 19 jeremybenn
 
842
`exe_log_marker = VALUE'
843
     Specifies the number of instructions between printing horizontal
844 82 jeremybenn
     markers.  Default is to produce no markers.
845 19 jeremybenn
 
846
`exe_log_file = FILENAME'
847
     Filename for the execution log filename if `exe_log' is enabled.
848 82 jeremybenn
     Default `executed.log'.  For backwards compatibility, the
849 19 jeremybenn
     alternative name `exe_log_fn' is supported for this parameter, but
850
     deprecated.
851
 
852
`clkcycle = VALUE[ps|ns|us|ms]'
853 82 jeremybenn
     Specify the time taken by one clock cycle.  If no units are
854
     specified, `ps' is assumed.  Default 4000ps (250MHz).
855 19 jeremybenn
 
856
 
857

858
File: or1ksim.info,  Node: Verification API Configuration,  Next: CUC Configuration,  Prev: Simulator Behavior,  Up: Simulator Configuration
859
 
860
3.2.2 Verification API (VAPI) Configuration
861
-------------------------------------------
862
 
863
The Verification API (VAPI) provides a TCP/IP interface to allow
864 82 jeremybenn
components of the simulation to be controlled externally.  *Note
865 19 jeremybenn
Verification API: Verification API, for more details.
866
 
867 82 jeremybenn
Verification API configuration is described in `section vapi'.  This
868
section may appear at most once.  The following parameters may be
869 19 jeremybenn
specified.
870
 
871
`enabled = 0|1'
872
     If 1 (true), verification API is enabled and its server started.
873
     If 0 (the default), it is disabled.
874
 
875
`server_port = VALUE'
876
     When VAPI is enabled, communication will be via TCP/IP on the port
877 82 jeremybenn
     specified by VALUE.  The value must lie in the range 1 to 65535.
878 19 jeremybenn
     The default value is 50000.
879
 
880 82 jeremybenn
          Tip: There is no registered port for Or1ksim VAPI.  Good
881 19 jeremybenn
          practice suggests users should adopt port values in the
882 82 jeremybenn
          "Dynamic" or "Private" port range, i.e.  49152-65535.
883 19 jeremybenn
 
884
`log_enabled = 0|1'
885
     If 1 (true), all VAPI requests and sent commands will be logged.
886 82 jeremybenn
     If 0 (the default), logging is diabled.  Logs are written to the
887 19 jeremybenn
     file specified by the `vapi_log_file' field (see below).
888
 
889
          Caution: This can generate a substantial amount of file I/O
890
          and seriously degrade simulator performance.
891
 
892
`hide_device_id = 0|1'
893 82 jeremybenn
     If 1 (true) don't log the device ID.  If 0 (the default), log the
894
     device ID.  This feature (when set to 1) is provided for backwards
895 19 jeremybenn
     compatibility with an old version of VAPI.
896
 
897
`vapi_log_file = "FILENAME"'
898
     Use `filename' as the file for logged data is logging is enabled
899 82 jeremybenn
     (see `log_enabled' above).  The default is `"vapi.log"'.  For
900 19 jeremybenn
     backwards compatibility, the alternative name `vapi_log_fn' is
901
     supported for this parameter, but deprecated.
902
 
903
 
904

905
File: or1ksim.info,  Node: CUC Configuration,  Prev: Verification API Configuration,  Up: Simulator Configuration
906
 
907
3.2.3 Custom Unit Compiler (CUC) Configuration
908
----------------------------------------------
909
 
910
The Custom Unit Compiler (CUC) was a project by Marko Mlinar to generate
911 82 jeremybenn
Verilog from ANSI C functions.  The project seems to not have progressed
912
beyond the initial prototype phase.  The configuration parameters are
913 19 jeremybenn
described here for the record.
914
 
915 82 jeremybenn
CUC configuration is described in `section cuc'.  This section may
916
appear at most once.  The following parameters may be specified.
917 19 jeremybenn
 
918
`memory_order = none|weak|strong|exact'
919
     This parameter specifies the memory ordering required:
920
 
921
    `memory_order=none'
922
          Different memory ordering, even if there are dependencies.
923
          Bursts can be made, width can change.
924
 
925 82 jeremybenn
          Different memory ordering, even if there are dependencies.  If
926 19 jeremybenn
          dependencies cannot occur, then bursts can be made, width can
927
          change.
928
 
929 82 jeremybenn
          Same memory ordering.  Bursts can be made, width can change.
930 19 jeremybenn
 
931
          Exactly the same memory ordering and widths.
932
 
933
 
934 82 jeremybenn
     The default value is `memory_order=exact'.  Invalid memory
935 19 jeremybenn
     orderings are ignored with a warning.
936
 
937
`calling_convention = 0|1'
938 82 jeremybenn
     If 1 (true), programs follow OpenRISC calling conventions.  If 0
939 19 jeremybenn
     (the default), they may use other convenitions.
940
 
941
`enable_bursts = 0 | 1'
942 82 jeremybenn
     If 1 (true), bursts are detected.  If 0 (the default), bursts are
943 19 jeremybenn
     not detected.
944
 
945
`no_multicycle = 0 | 1'
946 82 jeremybenn
     If 1 (true), no multicycle logic paths will be generated.  If 0
947
     (the default), multicycle logic paths will be generated.
948 19 jeremybenn
 
949
`timings_file = "FILENAME"'
950 82 jeremybenn
     FILENAME specifies a file containing timing information.  The
951
     default value is `"virtex.tim"'.  For backwards compatibility, the
952 19 jeremybenn
     alternative name `timings_fn' is supported for this parameter, but
953
     deprecated.
954
 
955
 
956

957
File: or1ksim.info,  Node: Core OpenRISC Configuration,  Next: Peripheral Configuration,  Prev: Simulator Configuration,  Up: Configuration
958
 
959
3.3 Configuring the OpenRISC Architectural Components
960
=====================================================
961
 
962
* Menu:
963
 
964
* CPU Configuration::
965
* Memory Configuration::
966
* Memory Management Configuration::
967
* Cache Configuration::
968
* Interrupt Configuration::
969
* Power Management Configuration::
970
* Branch Prediction Configuration::
971
* Debug Interface Configuration::
972
 
973

974
File: or1ksim.info,  Node: CPU Configuration,  Next: Memory Configuration,  Up: Core OpenRISC Configuration
975
 
976
3.3.1 CPU Configuration
977
-----------------------
978
 
979 82 jeremybenn
CPU configuration is described in `section cpu'.  This section should
980
appear only once.  At present Or1ksim does not model multi-CPU systems.
981 19 jeremybenn
The following parameters may be specified.
982
 
983
`ver = VALUE'
984
 
985
`cfg = VALUE'
986
 
987
`rev = VALUE'
988
     The values are used to form the corresponding fields in the `VR'
989 82 jeremybenn
     Special Purpose Register (SPR 0).  Default values 0.  A warning is
990 19 jeremybenn
     given and the value truncated if it is too large (8 bits for `ver'
991
     and `cfg', 6 bits for `rev').
992
 
993
`upr = VALUE'
994
     Used as the value of the Unit Present Register (UPR) Special
995 82 jeremybenn
     Purpose Register (SPR 1) to VALUE.  Default value is 0x0000075f,
996 19 jeremybenn
     i.e.
997
        * UPR present (0x00000001)
998
 
999
        * Data cache present (0x00000002)
1000
 
1001
        * Instruction cache present (0x00000004)
1002
 
1003
        * Data MMY present (0x00000008)
1004
 
1005
        * Instruction MMU present (0x00000010)
1006
 
1007
        * Debug unit present (0x00000040)
1008
 
1009
        * Power management unit present (0x00000100)
1010
 
1011
        * Programmable interrupt controller present (0x00000200)
1012
 
1013
        * Tick timer present (0x00000400)
1014
 
1015
     However, with the exection of the UPR present (0x00000001) and tick
1016
     timer present, the various fields will be modified with the values
1017
     specified in their corresponding configuration sections.
1018
 
1019
`cfgr = VALUE'
1020
     Sets the CPU configuration register (Special Purpose Register 2) to
1021 82 jeremybenn
     VALUE.  Default value is 0x00000020, i.e.  support for the ORBIS32
1022
     instruction set.  Attempts to set any other value are accepted, but
1023 19 jeremybenn
     issue a warning that there is no support for the instruction set.
1024
 
1025
`sr = VALUE'
1026
     Sets the supervision register Special Purpose Register (SPR 0x11)
1027 82 jeremybenn
     to VALUE.  Default value is 0x00008001, i.e.  start in supervision
1028 19 jeremybenn
     mode (0x00000001) and set the "Fixed One" bit (0x00008000).
1029
 
1030
`superscalar = 0|1'
1031 82 jeremybenn
     If 1, the processor operates in superscalar mode.  Default value is
1032 19 jeremybenn
     0.
1033
 
1034
     In the current simulator, the only functional effect of superscalar
1035
     mode is to affect the calculation of the number of cycles taken to
1036
     execute an instruction.
1037
 
1038
          Caution: The code for this does not appear to be complete or
1039
          well tested, so users are advised not to use this option.
1040
 
1041
`hazards = 0|1'
1042 82 jeremybenn
     If 1, data hazards are tracked in a superscalar CPU.  Default
1043
     value is 0.
1044 19 jeremybenn
 
1045
     In the current simulator, the only functional effect is to cause
1046
     logging of hazard waiting information if the CPU is superscalar.
1047
     However nowhere in the simulator is this data actually computed,
1048
     so the net result is probably to have no effect.
1049
 
1050
     if harzards are tracked, current hazards can be displayed using the
1051
     simulator's `r' command.
1052
 
1053
          Caution: The code for this does not appear to be complete or
1054
          well tested, so users are advised not to use this option.
1055
 
1056
`dependstats = 0|1'
1057 82 jeremybenn
     If 1, inter-instruction dependencies are calculated.  Default
1058
     value 0.
1059 19 jeremybenn
 
1060
     If these values are calculated, the depencies can be displayed
1061
     using the simulator's `stat' command.
1062
 
1063
          Note: This field must be enabled, if execution execution flow
1064
          tracking (field `history') has been requested in the simulator
1065
          configuration section (*note Simulator Behavior: Simulator
1066
          Behavior.).
1067
 
1068
`sbuf_len = VALUE'
1069
     The length of the store buffer is set to VALUE, which must be no
1070 82 jeremybenn
     greater than 256.  Larger values will be truncated to 256 with a
1071
     warning.  Negative values will be treated as 0 with a warning.
1072
     Use 0 to disable the store buffer.
1073 19 jeremybenn
 
1074
     When the store buffer is active, stores are accumulated and
1075
     committed when I/O is idle.
1076
 
1077
 
1078

1079
File: or1ksim.info,  Node: Memory Configuration,  Next: Memory Management Configuration,  Prev: CPU Configuration,  Up: Core OpenRISC Configuration
1080
 
1081
3.3.2 Memory Configuration
1082
--------------------------
1083
 
1084 82 jeremybenn
Memory configuration is described in `section memory'.  This section
1085
may appear multiple times, specifying multiple blocks of memory.  The
1086 19 jeremybenn
following parameters may be specified.
1087
 
1088
`type=random|pattern|unknown|zero'
1089 82 jeremybenn
     Specifies the values to which memory should be initialized.  The
1090 19 jeremybenn
     default value is `unknown'.
1091
 
1092
    `random'
1093 82 jeremybenn
          Set the memory values to be a random value.  A seed for the
1094 19 jeremybenn
          random generator may be set using the `random_seed' field in
1095
          this section (see below), thus ensuring the same "random"
1096
          values are used each time.
1097
 
1098
    `pattern'
1099
          Set the memory values to be a pattern value, which is set
1100
          using the `pattern' field in this section (see below).
1101
 
1102
    `unknown'
1103 82 jeremybenn
          The memory values are not initialized (i.e.  left "unknown").
1104 19 jeremybenn
          This option will yield faster initialization of the simulator.
1105
 
1106
    `zero'
1107 82 jeremybenn
          Set the memory values to be 0.  This is the equivalent of
1108 19 jeremybenn
          `type=pattern' and a `pattern' value of 0, and implemented as
1109
          such.
1110
 
1111
               Note: As a consequence, if the `pattern' field is
1112
               _subsequently_ specified in this section, the value in
1113
               that field will be used instead of zero to initialize
1114
               the memory.
1115
 
1116
 
1117
`random_seed = VALUE'
1118 82 jeremybenn
     Set the seed for the random number generator to VALUE.  This only
1119 19 jeremybenn
     has any effect for memory type `random'.
1120
 
1121
     The default value is -1, which means the seed will be set from a
1122
     call to the `time' function, thus ensuring different random values
1123 82 jeremybenn
     are used on each run.  The simulator prints out the seed used in
1124 19 jeremybenn
     this case, allowing repeat runs to regenerate the same random
1125
     values used in any particular run.
1126
 
1127
`pattern = VALUE'
1128 82 jeremybenn
     Set the pattern to be used when initializing memory to VALUE.  The
1129
     default value is 0.  This only has any effect for memory type
1130
     `pattern'.  The least significant 8 bits of this value is used to
1131
     initialize each byte.  More than 8 bits can be specified, but will
1132 19 jeremybenn
     ignored with a warning.
1133
 
1134
          Tip: The default value, is equivalent to setting the memory
1135 82 jeremybenn
          `type' to be `zero'.  If that is what is intended, then using
1136 19 jeremybenn
          `type=zero' explicitly is better than using `type=pattern'
1137
          and not specifying a value for `pattern'.
1138
 
1139
`baseaddr = VALUE'
1140 82 jeremybenn
     Set the base address of the memory to VALUE.  It should be aligned
1141 19 jeremybenn
     to a multiple of the memory size rounded up to the nearest 2^n.
1142
     The default value is 0.
1143
 
1144
`size = VALUE'
1145 82 jeremybenn
     Set the size of the memory block to be VALUE bytes.  This should
1146
     be a multiple of 4 (i.e.  word aligned).  The default value is
1147
     1024.
1148 19 jeremybenn
 
1149
          Note: When allocating memory, the simulator will allocate the
1150
          nearest 2^n bytes greater than or equal to VALUE, and will not
1151
          notice memory misses in any part of the memory between VALUE
1152
          and the amount allocated.
1153
 
1154
          As a consequence users are strongly recommended to specify
1155 82 jeremybenn
          memory sizes that are an exact power of 2.  If some other
1156 19 jeremybenn
          amount of memory is required, it should be specified as
1157
          separate, contiguous blocks, each of which is a power of 2 in
1158
          size.
1159
 
1160
`name = "TEXT"'
1161 82 jeremybenn
     Name the block.  Typically these describe the type of memory being
1162
     modeled (thus `"SRAM"' or `"Flash"'.  The default is
1163 19 jeremybenn
     `"anonymous memory block"'.
1164
 
1165
          Note: It is not clear that this information is currently ever
1166 82 jeremybenn
          used in normal operation of the simulator.  Even the `info'
1167 19 jeremybenn
          command of the simulator ignores it.
1168
 
1169
`ce = VALUE'
1170 82 jeremybenn
     Set the chip enable index of the memory instance.  Each memory
1171 19 jeremybenn
     instance should have a unique chip enable index, which should be
1172 82 jeremybenn
     greater than or equal to zero.  This is used by the memory
1173 19 jeremybenn
     controller when identifying different memory instances.
1174
 
1175
     The default value is -1 (invalid).
1176
 
1177
`mc = VALUE'
1178 82 jeremybenn
     Specifies the memory controller this memory is connected to.  It
1179 19 jeremybenn
     should correspond to the `index' field specified in a `section mc'
1180
     for a memory controller (*note Memory Controller Configuration:
1181
     Memory Controller Configuration.).
1182
 
1183
     Default value is 0, which is also the default value of a memory
1184 82 jeremybenn
     controller `index' field.  This is suitable therefore for designs
1185 19 jeremybenn
     with just one memory controller.
1186
 
1187
`delayr = VALUE'
1188 82 jeremybenn
     The number of cycles required for a read access.  Set to -1 if the
1189
     memory does not support reading.  Default value 1.  The simulator
1190 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1191
     count when reading from main memory.
1192
 
1193
`delayw = VALUE'
1194 82 jeremybenn
     The number of cycles required for a write access.  Set to -1 if the
1195
     memory does not support writing.  Default value 1.  The simulator
1196 19 jeremybenn
     will add this number of cycles to the total instruction cycle
1197
     count when writing to main memory.
1198
 
1199
`log = "FILE"'
1200
     If specified, `file' names a file for all memory accesses to be
1201 82 jeremybenn
     logged.  If not specified, the default value, NULL is used, meaning
1202 19 jeremybenn
     that the memory is not logged.
1203
 
1204
 
1205

1206
File: or1ksim.info,  Node: Memory Management Configuration,  Next: Cache Configuration,  Prev: Memory Configuration,  Up: Core OpenRISC Configuration
1207
 
1208
3.3.3 Memory Management Configuration
1209
-------------------------------------
1210
 
1211
Memory Management Unit (MMU) configuration is described in `section
1212
dmmu' (for the data MMU) and `section immu' (for the instruction MMU).
1213 82 jeremybenn
Each section should appear at most once.  The following parameters may
1214 19 jeremybenn
be specified.
1215
 
1216
`enabled = 0|1'
1217
     If 1 (true), the data or instruction (as appropriate) MMU is
1218 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1219 19 jeremybenn
 
1220
`nsets = VALUE'
1221
     Sets the number of data or instruction (as appropriate) TLB sets to
1222 82 jeremybenn
     VALUE, which must be a power of two, not exceeding 128.  Values
1223
     which do not fit these criteria are ignored with a warning.  The
1224 19 jeremybenn
     default value is 1.
1225
 
1226
`nways = VALUE'
1227
     Sets the number of data or instruction (as appropriate) TLB ways to
1228 82 jeremybenn
     VALUE.  The value must be in the range 1 to 4.  Values outside
1229
     this range are ignored with a warning.  The default value is 1.
1230 19 jeremybenn
 
1231
`pagesize = VALUE'
1232
     The data or instruction (as appropriate) MMU page size is set to
1233 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1234
     of 2 are ignored with a warning.  The default is 8192 (0x2000).
1235 19 jeremybenn
 
1236
`entrysize = VALUE'
1237
     The data or instruction (as appropriate) MMU entry size is set to
1238 82 jeremybenn
     VALUE, which must be a power of 2.  Values which are not a power
1239
     of 2 are ignored with a warning.  The default value is 1.
1240 19 jeremybenn
 
1241
          Note: Or1ksim does not appear to use the `entrysize' parameter
1242 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1243 19 jeremybenn
          not seem to matter.
1244
 
1245
`ustates = VALUE'
1246
     The number of instruction usage states for the data or instruction
1247
     (as appropriate) MMU is set to VALUE, which must be 2, 3 or 4.
1248 82 jeremybenn
     Values outside this range are ignored with a warning.  The default
1249 19 jeremybenn
     value is 2.
1250
 
1251
          Note: Or1ksim does not appear to use the `ustates' parameter
1252 82 jeremybenn
          in its simulation of the MMUs.  Thus setting this value does
1253 19 jeremybenn
          not seem to matter.
1254
 
1255
`hitdelay = VALUE'
1256
     Set the number of cycles a data or instruction (as appropriate) MMU
1257 82 jeremybenn
     hit costs.  Default value 1.
1258 19 jeremybenn
 
1259
`missdelay = VALUE'
1260
     Set the number of cycles a data or instruction (as appropriate) MMU
1261 82 jeremybenn
     miss costs.  Default value 1.
1262 19 jeremybenn
 
1263
 
1264

1265
File: or1ksim.info,  Node: Cache Configuration,  Next: Interrupt Configuration,  Prev: Memory Management Configuration,  Up: Core OpenRISC Configuration
1266
 
1267
3.3.4 Cache Configuration
1268
-------------------------
1269
 
1270
Cache configuration is described in `section dc' (for the data cache)
1271 82 jeremybenn
and `seciton ic' (for the instruction cache).  Each section should
1272
appear at most once.  The following parameters may be specified.
1273 19 jeremybenn
 
1274
`enabled = 0|1'
1275
     If 1 (true), the data or instruction (as appropriate) cache is
1276 82 jeremybenn
     enabled.  If 0 (the default), it is disabled.
1277 19 jeremybenn
 
1278
`nsets = VALUE'
1279
     Sets the number of data or instruction (as appropriate) cache sets
1280
     to VALUE, which must be a power of two, not exceeding
1281
     `MAX_DC_SETS' (for the data cache) or `MAX_IC_SETS' (for the
1282 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1283
     both defined in the code to be 1024).  The default value is 1.
1284 19 jeremybenn
 
1285
`nways = VALUE'
1286
     Sets the number of data or instruction (as appropriate) cache ways
1287
     to VALUE, which must be a power of two, not exceeding
1288
     `MAX_DC_WAYS' (for the data cache) or `MAX_IC_WAYS' (for the
1289 82 jeremybenn
     instruction cache).  At the time of writing, these constants are
1290
     both defined in the code to be 32).  The default value is 1.
1291 19 jeremybenn
 
1292
`blocksize = VALUE'
1293
     The data or instruction (as appropriate) cache block size is set to
1294 82 jeremybenn
     VALUE bytes, which must be either 16 or 32.  The default is 16.
1295 19 jeremybenn
 
1296
`ustates = VALUE'
1297
     The number of instruction usage states for the data or instruction
1298
     (as appropriate) cache is set to VALUE, which must be 2, 3 or 4.
1299
     The default value is 2.
1300
 
1301
`hitdelay = VALUE'
1302 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1303
     cache hit costs.  Default value 1.
1304 19 jeremybenn
 
1305
`missdelay = VALUE'
1306 82 jeremybenn
     _Instruction cache only_.  Set the number of cycles an instruction
1307
     cache miss costs.  Default value 1.
1308 19 jeremybenn
 
1309
`load_hitdelay = VALUE'
1310 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache hit
1311
     costs.  Default value 2.
1312 19 jeremybenn
 
1313
`load_missdelay = VALUE'
1314 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data load cache
1315
     miss costs.  Default value 2.
1316 19 jeremybenn
 
1317
`store_hitdelay = VALUE'
1318 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache hit
1319
     costs.  Default value 0.
1320 19 jeremybenn
 
1321
`store_missdelay = VALUE'
1322 82 jeremybenn
     _Data cache only_.  Set the number of cycles a data store cache
1323
     miss costs.  Default value 0.
1324 19 jeremybenn
 
1325
 
1326

1327
File: or1ksim.info,  Node: Interrupt Configuration,  Next: Power Management Configuration,  Prev: Cache Configuration,  Up: Core OpenRISC Configuration
1328
 
1329
3.3.5 Interrupt Configuration
1330
-----------------------------
1331
 
1332
Programmable Interrupt Controller (PIC) configuration is described in
1333 82 jeremybenn
`section pic'.  This section may appear at most once--Or1ksim has no
1334
mechanism for handling multiple interrupt controllers.  The following
1335 19 jeremybenn
parameters may be specified.
1336
 
1337
`enabled = 0|1'
1338 82 jeremybenn
     If 1 (true), the programmable interrupt controller is enabled.  If
1339
 
1340 19 jeremybenn
 
1341
`edge_trigger = 0|1'
1342
     If 1 (true, the default), the programmable interrupt controller is
1343 82 jeremybenn
     edge triggered.  If 0 (false), it is level triggered.
1344 19 jeremybenn
 
1345
 
1346

1347
File: or1ksim.info,  Node: Power Management Configuration,  Next: Branch Prediction Configuration,  Prev: Interrupt Configuration,  Up: Core OpenRISC Configuration
1348
 
1349
3.3.6 Power Management Configuration
1350
------------------------------------
1351
 
1352 82 jeremybenn
Power management implementation is incomplete.  At present the effect
1353 19 jeremybenn
(which only happens when the power management unit is enabled) of
1354
setting the different bits in the power management Special Purpose
1355
Register (PMR, SPR 0x4000) is
1356
 
1357
`SDF (bit mask 0x0000000f)'
1358
     No effect - these bits are ignored
1359
 
1360
`DME (bit mask 0x00000010)'
1361
`SME (bit mask 0x00000020)'
1362
     Both these bits cause the processor to stop executing
1363 82 jeremybenn
     instructions.  However all other functions (debug interaction, CLI,
1364 19 jeremybenn
     VAPI etc) carry on as normal.
1365
 
1366
`DCGE (bit mask 0x00000004)'
1367
     No effect - this bit is ignored
1368
 
1369
`SUME (bit mask 0x00000008)'
1370
     Enabling this bit causes a message to be printed, advising that the
1371
     processor is suspending and the simulator exits.
1372
 
1373
 
1374
On reset all bits are cleared.
1375
 
1376 82 jeremybenn
Power management configuration is described in `section pm'.  This
1377
section may appear at most once.  The following parameter may be
1378 19 jeremybenn
specified.
1379
 
1380
`enabled = 0|1'
1381 82 jeremybenn
     If 1 (true), power management is enabled.  If 0 (the default), it
1382
     is disabled.
1383 19 jeremybenn
 
1384
 
1385

1386
File: or1ksim.info,  Node: Branch Prediction Configuration,  Next: Debug Interface Configuration,  Prev: Power Management Configuration,  Up: Core OpenRISC Configuration
1387
 
1388
3.3.7 Branch Prediction Configuration
1389
-------------------------------------
1390
 
1391
From examining the code base, it seems the branch prediction function
1392 82 jeremybenn
is not fully implemented.  At present the functionality seems
1393
restricted to collection of statistics.
1394 19 jeremybenn
 
1395 82 jeremybenn
Branch prediction configuration is described in `section bpb'.  This
1396
section may appear at most once.  The following parameters may be
1397 19 jeremybenn
specified.
1398
 
1399
`enabled = 0|1'
1400 82 jeremybenn
     If 1 (true), branch prediction is enabled.  If 0 (the default), it
1401 19 jeremybenn
     is disabled.
1402
 
1403
`btic = 0|1'
1404
     If 1 (true), the branch target instruction cache model is enabled.
1405
     If 0 (the default), it is disabled.
1406
 
1407
`sbp_bf_fwd = 0|1'
1408 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bf' instruction.  If
1409 19 jeremybenn
 
1410
     instruction.
1411
 
1412
`sbp_bnf_fwd = 0|1'
1413 82 jeremybenn
     If 1 (true), use forward prediction for the `l.bnf' instruction.
1414
     If 0 (the default), do not use forward prediction for this
1415 19 jeremybenn
     instruction.
1416
 
1417
`hitdelay = VALUE'
1418 82 jeremybenn
     Set the number of cycles a branch prediction hit costs.  Default
1419 19 jeremybenn
     value 0.
1420
 
1421
`missdelay = VALUE'
1422 82 jeremybenn
     Set the number of cycles a branch prediction miss costs.  Default
1423 19 jeremybenn
     value 0.
1424
 
1425
 
1426

1427
File: or1ksim.info,  Node: Debug Interface Configuration,  Prev: Branch Prediction Configuration,  Up: Core OpenRISC Configuration
1428
 
1429
3.3.8 Debug Interface Configuration
1430
-----------------------------------
1431
 
1432
The debug unit and debug interface configuration is described in
1433 82 jeremybenn
`section debug'.  This section may appear at most once.  The following
1434 19 jeremybenn
parameters may be specified.
1435
 
1436
`enabled = 0|1'
1437 82 jeremybenn
     If 1 (true), the debug unit is enabled.  If 0 (the default), it is
1438 19 jeremybenn
     disabled.
1439
 
1440
          Note: This enables the functionality of the debug unit (its
1441 82 jeremybenn
          registers etc) within the mode.  It does not provide any
1442
          external interface to the debug unit.  For that, see
1443 19 jeremybenn
          `gdb_enabled' and `rsp_enabled' below.
1444
 
1445
`rsp_enabled = 0|1'
1446
     If 1 (true), the GDB "Remote Serial Protocol" server is started,
1447
     provding an interface to an external GNU debugger, using the port
1448
     specified in the `rsp_port' field (see below), or the
1449 82 jeremybenn
     `or1ksim-rsp' TCP/IP service.  If 0 (the default), the server is
1450 19 jeremybenn
     not started, and no external interface is provided.
1451
 
1452
     For more detailed information on the interface to the GNU Debugger
1453
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1454
     Practical Experience with the OpenRISC 1000 Architecture', by
1455
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1456
 
1457 82 jeremybenn
          Note: `rsp_enabled' may not be enabled with `gdb_enabled' (see
1458
          below).  If both are enabled, a warning is issued and only
1459
          the "Remote Serial Protocol" interface is enabled.
1460 19 jeremybenn
 
1461
`rsp_port = VALUE'
1462
     VALUE specifies the port to be used for the GDB "Remote Serial
1463 82 jeremybenn
     Protocol" interface to the GNU Debugger (GDB).  Default value
1464
     51000.  If the value 0 is specified, Or1ksim will instead look for
1465 19 jeremybenn
     a TCP/IP service named `or1ksim-rsp'.
1466
 
1467
          Tip: There is no registered port for Or1ksim "Remote Serial
1468 82 jeremybenn
          Protocol" service `or1ksim-rsp'.  Good practice suggests
1469
          users should adopt port values in the "Dynamic" or "Private"
1470
          port range, i.e.  49152-65535.
1471 19 jeremybenn
 
1472
`gdb_enabled = 0|1'
1473
     If 1 (true), the OpenRISC Remote JTAG protocol server is started,
1474
     provding an interface to an external GNU debugger, using the port
1475
     specified in the `server_port' field (see below), or the `or1ksim'
1476 82 jeremybenn
     TCP/IP service.  If 0 (the default), the server is not started,
1477
     and no external interface is provided.
1478 19 jeremybenn
 
1479
     For more detailed information on the interface to the GNU Debugger
1480
     see Embecosm Application Note 2, `Howto: Porting the GNU Debugger
1481
     Practical Experience with the OpenRISC 1000 Architecture', by
1482
     Jeremy Bennett, published by Embecosm Limited (`www.embecosm.com').
1483
 
1484
          Note: The OpenRISC Remote JTAG protocol is unique to
1485 82 jeremybenn
          OpenRISC, and remains only for backward compatibility.  New
1486 19 jeremybenn
          users should adopt the standard GDB "Remote Serial Protocol"
1487
          interface (see `rsp_enabled' above) providing access to a
1488
          wider range of GDB functionality.
1489
 
1490 82 jeremybenn
          Note: `gdb_enabled' may not be enabled with `rsp_enabled'.
1491
          If both are enabled, a warning is issued and only the "Remote
1492 19 jeremybenn
          Serial Protocol" interface is enabled.
1493
 
1494
`server_port = VALUE'
1495
     VALUE specifies the port to be used for the OpenRISC Rmote JTAG
1496 82 jeremybenn
     protocol interface to the GNU Debugger (GDB).  Default value
1497
     51000.  If the value 0 is specified, Or1ksim will instead look for
1498
     a TCP/IP service named `or1ksim'.
1499 19 jeremybenn
 
1500
          Tip: There is no registered port for Or1ksim Remote JTAG
1501 82 jeremybenn
          Interface or service `or1ksim'.  Good practice suggests users
1502 19 jeremybenn
          should adopt port values in the "Dynamic" or "Private" port
1503 82 jeremybenn
          range, i.e.  49152-65535.
1504 19 jeremybenn
 
1505
`vapi_id = VALUE'
1506
     VALUE specifies the value of the Verification API (VAPI) base
1507 82 jeremybenn
     address to be used with the debug unit.  *Note Verification API:
1508 19 jeremybenn
     Verification API, for more details.
1509
 
1510
     If this is specified and VALUE is non-zero, all OpenRISC Remote
1511
     JTAG protocol transactions will be logged to the VAPI log file, if
1512 82 jeremybenn
     enabled.  This is the only functionality associated with VAPI for
1513
     the debug unit.  No VAPI commands are sent, nor requests handled.
1514 19 jeremybenn
 
1515
 
1516

1517
File: or1ksim.info,  Node: Peripheral Configuration,  Prev: Core OpenRISC Configuration,  Up: Configuration
1518
 
1519
3.4 Configuring Memory Mapped Peripherals
1520
=========================================
1521
 
1522 82 jeremybenn
All peripheral components are optional.  If they are specified, then
1523 19 jeremybenn
(unlike other components) by default they are enabled.
1524
 
1525
* Menu:
1526
 
1527
* Memory Controller Configuration::
1528
* UART Configuration::
1529
* DMA Configuration::
1530
* Ethernet Configuration::
1531
* GPIO Configuration::
1532
* Display Interface Configuration::
1533
* Frame Buffer Configuration::
1534
* Keyboard Configuration::
1535
* Disc Interface Configuration::
1536
* Generic Peripheral Configuration::
1537
 
1538

1539
File: or1ksim.info,  Node: Memory Controller Configuration,  Next: UART Configuration,  Up: Peripheral Configuration
1540
 
1541
3.4.1 Memory Controller Configuration
1542
-------------------------------------
1543
 
1544
The memory controller used in Or1ksim is the component implemented at
1545 82 jeremybenn
OpenCores, and found in the top level CVS directory, `mem_ctrl'.  It is
1546 19 jeremybenn
described in the document `Memory Controller IP Core' by Rudolf
1547 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1548
memory mapped component, which resides on the main OpenRISC Wishbone
1549
data bus.
1550 19 jeremybenn
 
1551 82 jeremybenn
The memory controller configuration is described in `section mc'.  This
1552 19 jeremybenn
section may appear multiple times, specifying multiple memory
1553 82 jeremybenn
controllers.  The following parameters may be specified.
1554 19 jeremybenn
 
1555
`enabled = 0|1'
1556 82 jeremybenn
     If 1 (true, the default), this memory controller is enabled.  If
1557
     0, it is disabled.
1558 19 jeremybenn
 
1559
          Note: The memory controller can effectively also be disabled
1560
          by setting an appropriate power on control register value
1561 82 jeremybenn
          (see below).  However this should only be used if it is
1562 19 jeremybenn
          desired to specifically model this behavior of the memory
1563
          controller, not as a way of disabling the memory controller
1564
          in general.
1565
 
1566
`baseaddr = VALUE'
1567
     Set the base address of the memory controller's memory mapped
1568 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1569 19 jeremybenn
     sensible value.
1570
 
1571
     The memory controller has a 7 bit address bus, with a total of 19
1572
     32-bit registers, at addresses 0x00 through 0x4c (address 0x0c and
1573
     addresses 0x50 through 0x7c are not used).
1574
 
1575
`poc = VALUE'
1576
     Specifies the value of the power on control register, The least
1577
     signficant two bits specify the bus width (use 0 for an 8-bit bus,
1578
     1 for a 16-bit bus and 2 for a 32-bit bus) and the next two bits
1579
     the type of memory connected (use 0 for a disabled interface, 1
1580
     for SSRAM, 2 for asyncrhonous devices and 3 for synchronous
1581
     devices).
1582
 
1583
     If other bits are specified, they are ignored with a warning.
1584
 
1585
          Caution: The default value, 0, corresponds to a disabled
1586
          8-bit bus, and is likely not the most suitable value
1587
 
1588
`index = VALUE'
1589
     Specify the index of this memory controller amongst all the memory
1590 82 jeremybenn
     controllers.  This value should be unique for each memory
1591 19 jeremybenn
     controller, and is used to associate specific memories with the
1592
     controller, through the `mc' field in the `section memory'
1593
     configuration (*note Memory Configuration: Memory Configuration.).
1594
 
1595
     The default value, 0, is suitable when there is only one memory
1596
     controller.
1597
 
1598
 
1599

1600
File: or1ksim.info,  Node: UART Configuration,  Next: DMA Configuration,  Prev: Memory Controller Configuration,  Up: Peripheral Configuration
1601
 
1602
3.4.2 UART Configuration
1603
------------------------
1604
 
1605
The UART implemented in Or1ksim follows the specification of the
1606 82 jeremybenn
National Semiconductor 16450 and 16550 parts.  It is a memory mapped
1607 19 jeremybenn
component, which resides on the main OpenRISC Wishbone data bus.
1608
 
1609
The component provides a number of interfaces to emulate the behavior
1610
of an external terminal connected to the UART.
1611
 
1612 82 jeremybenn
UART configuration is described in `section uart'.  This section may
1613
appear multiple times, specifying multiple UARTs.  The following
1614 19 jeremybenn
parameters may be specified.
1615
 
1616
`enabled = 0|1'
1617 82 jeremybenn
     If 1 (true, the default), this UART is enabled.  If 0, it is
1618 19 jeremybenn
     disabled.
1619
 
1620
`baseaddr = VALUE'
1621
     Set the base address of the UART's memory mapped registers to
1622 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1623 19 jeremybenn
 
1624
     The UART has a 3 bit address bus, with a total of 8 8-bit
1625
     registers, at addresses 0x0 through 0x7.
1626
 
1627
`channel = "TYPE:ARGS"'
1628
     Specify the channel representing the terminal connected to the UART
1629
     Rx & Tx pins.
1630
 
1631
    `channel="file:`rxfile',`txfile'"'
1632
          Read input characters from the file `rxfile' and write output
1633
          characters to the file `txfile' (which will be created if
1634
          required).
1635
 
1636
    `channel="xterm:ARGS"'
1637
          Create an xterm on startup, write UART Tx traffic to the
1638
          xterm and take Rx traffic from the keyboard when the xterm
1639 82 jeremybenn
          window is selected.  Additional arguments to the xterm
1640
          command (for example specifying window size may be specified
1641
          in ARGS, or this may be left blank.
1642 19 jeremybenn
 
1643
    `channel="tcp:VALUE"'
1644
          Open the TCP/IP port specified by VALUE and read and write
1645
          UART traffic from and to it.
1646
 
1647
          Typically a telnet session is connected to the other end of
1648
          this port.
1649
 
1650
               Tip: There is no registered port for Or1ksim telnet UART
1651 82 jeremybenn
               connection.  Priviledged access is required to read
1652 19 jeremybenn
               traffic on the registered "well-known" telnet port (23).
1653
               Instead users should use port values in the "Dynamic" or
1654 82 jeremybenn
               "Private" port range, i.e.  49152-65535.
1655 19 jeremybenn
 
1656
    `channel="fd:`rxfd',`txfd'"'
1657
          Read and write characters from and to the existing open
1658
          numerical file descriptors, file `rxfd' and `txfd'.
1659
 
1660
    `channel="tty:device=/dev/ttyS0,baud=9600"'
1661
          Read and write characters from and to a physical serial port.
1662
          The precise device (shown here as `/dev/ttyS0') may vary from
1663
          machine to machine.
1664
 
1665
 
1666
     The default value for this field is `"xterm:"'.
1667
 
1668
`irq = VALUE'
1669 82 jeremybenn
     Use VALUE as the IRQ number of this UART.  Default value 0.
1670 19 jeremybenn
 
1671
`16550 = 0|1'
1672 82 jeremybenn
     If 1 (true), the UART has the functionality of a 16550.  If 0 (the
1673
     default), it has the functionality of a 16450.  The principal
1674 19 jeremybenn
     difference is that the 16550 can buffer multiple characters.
1675
 
1676
`jitter = VALUE'
1677
     Set the jitter, modeled as a time to block, to VALUE milliseconds.
1678 82 jeremybenn
     Set to -1 to disable jitter modeling.  Default value 0.
1679 19 jeremybenn
 
1680
          Note: This functionality has yet to be implemented, so this
1681
          parameter has no effect.
1682
 
1683
`vapi_id = VALUE'
1684
     VALUE specifies the value of the Verification API (VAPI) base
1685 82 jeremybenn
     address to be used with the UART.  *Note Verification API:
1686 19 jeremybenn
     Verification API, for more details, which details the use of the
1687
     VAPI with the UART.
1688
 
1689
 
1690

1691
File: or1ksim.info,  Node: DMA Configuration,  Next: Ethernet Configuration,  Prev: UART Configuration,  Up: Peripheral Configuration
1692
 
1693
3.4.3 DMA Configuration
1694
-----------------------
1695
 
1696
The DMA controller used in Or1ksim is the component implemented at
1697 82 jeremybenn
OpenCores, and found in the top level CVS directory, `wb_dma'.  It is
1698 19 jeremybenn
described in the document `Wishbone DMA/Bridge IP Core' by Rudolf
1699 82 jeremybenn
Usselmann, which can be found in the `doc' subdirectory.  It is a
1700
memory mapped component, which resides on the main OpenRISC Wishbone
1701
data bus.  The present implementation is incomplete, intended only to
1702
support the Ethernet interface (*note Ethernet Configuration::),
1703
although the Ethernet interface is not yet completed.
1704 19 jeremybenn
 
1705 82 jeremybenn
DMA configuration is described in `section dma'.  This section may
1706
appear multiple times, specifying multiple DMA controllers.  The
1707 19 jeremybenn
following parameters may be specified.
1708
 
1709
`enabled = 0|1'
1710 82 jeremybenn
     If 1 (true, the default), this DMA controller is enabled.  If 0,
1711
     it is disabled.
1712 19 jeremybenn
 
1713
`baseaddr = VALUE'
1714
     Set the base address of the DMA's memory mapped registers to
1715 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1716 19 jeremybenn
 
1717
     The DMA controller has a 10 bit address bus, with a total of 253
1718 82 jeremybenn
     32-bit registers.  The first 5 registers at addresses 0x000 through
1719
     0x010 control the overall behavior of the DMA controller.  There
1720
     are then 31 blocks of 8 registers, controlling each of the 31 DMA
1721
     channels available.  Addresses 0x014 through 0x01c are not used.
1722 19 jeremybenn
 
1723
`irq = VALUE'
1724 82 jeremybenn
     Use VALUE as the IRQ number of this DMA controller.  Default value
1725 19 jeremybenn
     0.
1726
 
1727
`vapi_id = VALUE'
1728
     VALUE specifies the value of the Verification API (VAPI) base
1729 82 jeremybenn
     address to be used with the DMA controller.  *Note Verification
1730 19 jeremybenn
     API: Verification API, for more details, which details the use of
1731
     the VAPI with the DMA controller.
1732
 
1733
 
1734

1735
File: or1ksim.info,  Node: Ethernet Configuration,  Next: GPIO Configuration,  Prev: DMA Configuration,  Up: Peripheral Configuration
1736
 
1737
3.4.4 Ethernet Configuration
1738
----------------------------
1739
 
1740
The Ethernet MAC used in Or1ksim is the component implemented at
1741 82 jeremybenn
OpenCores, and found in the top level CVS directory, `ethernet'.  It
1742
also forms part of the OpenRISC SoC, ORPSoC.  It is described in the
1743 19 jeremybenn
document `Ethernet IP Core Specification' by Igor Mohor, which can be
1744 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1745
which resides on the main OpenRISC Wishbone data bus.
1746 19 jeremybenn
 
1747 82 jeremybenn
Ethernet configuration is described in `section ethernet'.  This
1748
section may appear multiple times, specifying multiple Ethernet
1749
interfaces.  The following parameters may be specified.
1750 19 jeremybenn
 
1751
`enabled = 0|1'
1752 82 jeremybenn
     If 1 (true, the default), this Ethernet MAC is enabled.  If 0, it
1753
     is disabled.
1754 19 jeremybenn
 
1755
`baseaddr = VALUE'
1756
     Set the base address of the MAC's memory mapped registers to
1757 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1758 19 jeremybenn
 
1759
     The Ethernet MAC has a 7-bit address bus, with a total of 21
1760 82 jeremybenn
     32-bit registers.  Addresses 0x54 through 0x7c are not used.
1761 19 jeremybenn
 
1762
          Note: The Ethernet specification describes a Tx control
1763 82 jeremybenn
          register, `TXCTRL', at address 0x50.  However this register
1764
          is not implemented in the Or1ksim model.
1765 19 jeremybenn
 
1766
`dma = VALUE'
1767
     VALUE specifies the DMA controller with which this Ethernet is
1768 82 jeremybenn
     associated.  The default value is 0.
1769 19 jeremybenn
 
1770
          Note: Support for external DMA is not provided in the current
1771 82 jeremybenn
          implementation, and this value is ignored.  In any case there
1772 19 jeremybenn
          is no equivalent field to which this can be matched in the
1773
          current DMA component implementation (*note DMA
1774
          Configuration: DMA Configuration.).
1775
 
1776
`irq = VALUE'
1777 82 jeremybenn
     Use VALUE as the IRQ number of this Ethernet MAC.  Default value 0.
1778 19 jeremybenn
 
1779
`rtx_type = 0|1'
1780
     If 1 (true) use a socket interface to the Ethernet (see parameter
1781 82 jeremybenn
     `sockif' below).  If 0 (the default), use a file interface,
1782
     reading and writing from and to the files specified in the
1783
     `rxfile' and `txfile' parameters (see below).
1784 19 jeremybenn
 
1785
          Note: By default the socket interface is not provided in
1786 82 jeremybenn
          Or1ksim.  If it is required, this must be requested when
1787 19 jeremybenn
          configuring, by use of the `--enable-ethphy' option to
1788
          `configure'.
1789
 
1790
               configure --target=or32-uclinux --enable-ethphy ...
1791
 
1792
`rx_channel = RXVALUE'
1793
`tx_channel = TXVALUE'
1794
     RXVALUE specifies the DMA channel to use for receive and TXVALUE
1795 82 jeremybenn
     the DMA channel to use for transmit.  Both default to 0.
1796 19 jeremybenn
 
1797
          Note: As noted above, support for external DMA is not
1798
          provided in the current implementation, and so these values
1799
          are ignored.
1800
 
1801
`rxfile = "RXFILE"'
1802
`txfile = "TXFILE"'
1803
     When `rtx_type' is 0 (see above), RXFILE specifies the file to use
1804
     as input and TXFILE specifies the fie to use as output.
1805
 
1806 82 jeremybenn
     The file contains a sequence of packets.  Each packet consists of a
1807
     packet length (32 bits), followed by that many bytes of data.
1808
     Once the input file is empty, the Ethernet MAC behaves as though
1809
     there were no data on the Ethernet.  The default values of these
1810 19 jeremybenn
     parameters are `"eth_rx"' and `"eth_tx"' respectively.
1811
 
1812 82 jeremybenn
     The input file must exist and be readable.  The output file must be
1813
     writable and will be created if necessary.  If either of these
1814 19 jeremybenn
     conditions is not met, a warning will be given.
1815
 
1816
`sockif = "SERVICE"'
1817
     When `rtx_type' is 1 (see above), SERVICE specifies the service to
1818 82 jeremybenn
     use for communication.  This may be TCP/IP or UDP/IP.  The default
1819 19 jeremybenn
     value of this parameter is `"or1ksim_eth"'.
1820
 
1821
`vapi_id = VALUE'
1822
     VALUE specifies the value of the Verification API (VAPI) base
1823 82 jeremybenn
     address to be used with the Ethernet PHY.  *Note Verification API:
1824 19 jeremybenn
     Verification API, for more details, which details the use of the
1825
     VAPI with the DMA controller.
1826
 
1827
 
1828

1829
File: or1ksim.info,  Node: GPIO Configuration,  Next: Display Interface Configuration,  Prev: Ethernet Configuration,  Up: Peripheral Configuration
1830
 
1831
3.4.5 GPIO Configuration
1832
------------------------
1833
 
1834
The GPIO used in Or1ksim is the component implemented at OpenCores, and
1835 82 jeremybenn
found in the top level CVS directory, `gpio'.  It is described in the
1836 19 jeremybenn
document `GPIO IP Core Specification' by Damjan Lampret and Goran
1837 82 jeremybenn
Djakovic, which can be found in the `doc' subdirectory.  It is a memory
1838 19 jeremybenn
mapped component, which resides on the main OpenRISC Wishbone data bus.
1839
 
1840 82 jeremybenn
GPIO configuration is described in `section gpio'.  This section may
1841
appear multiple times, specifying multiple GPIO devices.  The following
1842 19 jeremybenn
parameters may be specified.
1843
 
1844
`enabled = 0|1'
1845 82 jeremybenn
     If 1 (true, the default), this GPIO is enabled.  If 0, it is
1846 19 jeremybenn
     disabled.
1847
 
1848
`baseaddr = VALUE'
1849
     Set the base address of the GPIO's memory mapped registers to
1850 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
1851 19 jeremybenn
 
1852
     The GPIO has a 6 bit address bus, with a total of 10 32-bit
1853
     registers, although the number of bits that are actively used
1854 82 jeremybenn
     varies.  Addresses 0x28 through 0x3c are not used.
1855 19 jeremybenn
 
1856
`irq = VALUE'
1857 82 jeremybenn
     Use VALUE as the IRQ number of this GPIO.  Default value 0.
1858 19 jeremybenn
 
1859
`vapi_id = VALUE'
1860
     VALUE specifies the value of the Verification API (VAPI) base
1861 82 jeremybenn
     address to be used with the GPIO.  *Note Verification API:
1862 19 jeremybenn
     Verification API, for more details, which details the use of the
1863 82 jeremybenn
     VAPI with the GPIO controller.  For backwards compatibility, the
1864 19 jeremybenn
     alternative name `base_vapi_id' is supported for this parameter,
1865
     but deprecated.
1866
 
1867
 
1868

1869
File: or1ksim.info,  Node: Display Interface Configuration,  Next: Frame Buffer Configuration,  Prev: GPIO Configuration,  Up: Peripheral Configuration
1870
 
1871
3.4.6 Display Interface Configuration
1872
-------------------------------------
1873
 
1874
Or1ksim models a VGA interface to an external monitor.  The VGA
1875
controller used in Or1ksim is the component implemented at OpenCores,
1876
and found in the top level CVS directory, `vga_lcd', with no support
1877 82 jeremybenn
for the optional hardware cursors.  It is described in the document
1878 19 jeremybenn
`VGA/LCD Core v2.0 Specifications' by Richard Herveille, which can be
1879 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
1880
which resides on the main OpenRISC Wishbone data bus.
1881 19 jeremybenn
 
1882
The current implementation provides only functionality to dump the
1883
screen to a file at intervals.
1884
 
1885 82 jeremybenn
VGA controller configuration is described in `section vga'.  This
1886 19 jeremybenn
section may appear multiple times, specifying multiple VGA controllers.
1887
The following parameters may be specified.
1888
 
1889
`enabled = 0|1'
1890 82 jeremybenn
     If 1 (true, the default), this VGA is enabled.  If 0, it is
1891 19 jeremybenn
     disabled.
1892
 
1893
`baseaddr = VALUE'
1894
     Set the base address of the VGA controller's memory mapped
1895 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
1896 19 jeremybenn
     sensible value.
1897
 
1898
     The VGA controller has a 12-bit address bus, with 7 32-bit
1899
     registers, at addresses 0x000 through 0x018, and two color lookup
1900 82 jeremybenn
     tables at addresses 0x800 through 0xfff.  The hardware cursor
1901 19 jeremybenn
     registers are not implemented, so addresses 0x01c through 0x7fc
1902
     are not used.
1903
 
1904
`irq = VALUE'
1905 82 jeremybenn
     Use VALUE as the IRQ number of this VGA controller.  Default value
1906 19 jeremybenn
     0.
1907
 
1908
`refresh_rate = VALUE'
1909 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
1910 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
1911
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
1912
     50 times per simulated second.
1913
 
1914
`txfile = "FILE"'
1915
     FILE specifies the base of the filename for screen dumps.
1916
     Successive screen dumps will be in BMP format, in files with the
1917
     name `FILENNNN.bmp', where NNNN is a sequential count of the
1918 82 jeremybenn
     screen dumps starting at zero.  The default value is `"vga_out"'.
1919 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
1920
     supported for this parameter, but deprecated.
1921
 
1922
 
1923

1924
File: or1ksim.info,  Node: Frame Buffer Configuration,  Next: Keyboard Configuration,  Prev: Display Interface Configuration,  Up: Peripheral Configuration
1925
 
1926
3.4.7 Frame Buffer Configuration
1927
--------------------------------
1928
 
1929 82 jeremybenn
     Caution: The frame buffer is only partially implemented.  Its
1930 19 jeremybenn
     configuration fields are described here, but the component should
1931 82 jeremybenn
     not be used at this time.  Like the VGA controller, it is designed
1932 19 jeremybenn
     to make screen dumps to file.
1933
 
1934 82 jeremybenn
Frame buffer configuration is described in `section fb'.  This section
1935
may appear multiple times, specifying multiple frame buffers.  The
1936 19 jeremybenn
following parameters may be specified.
1937
 
1938
`enabled = 0|1'
1939 82 jeremybenn
     If 1 (true, the default), this frame buffer is enabled.  If 0, it
1940 19 jeremybenn
     is disabled.
1941
 
1942
`baseaddr = VALUE'
1943
     Set the base address of the frame buffer's memory mapped registers
1944 82 jeremybenn
     to VALUE.  The default is 0, which is probably not a sensible
1945
     value.
1946 19 jeremybenn
 
1947
     The frame buffer has an 121-bit address bus, with 4 32-bit
1948
     registers, at addresses 0x000 through 0x00c, and a PAL lookup
1949 82 jeremybenn
     table at addresses 0x400 through 0x4ff.  Addresses 0x010 through
1950 19 jeremybenn
     0x3fc and addresses 0x500 through 0x7ff are not used.
1951
 
1952
`refresh_rate = VALUE'
1953 82 jeremybenn
     VALUE specifies number of cycles between screen dumps.  Default
1954 19 jeremybenn
     value is derived from the simulation clock cycle time (*note
1955
     Simulator Behavior: Simulator Behavior.), to correspond to dumping
1956
     50 times per simulated second.
1957
 
1958
`txfile = "FILE"'
1959
     FILE specifies the base of the filename for screen dumps.
1960
     Successive screen dumps will be in BMP format, in files with the
1961
     name `FILENNNN.bmp', where NNNN is a sequential count of the
1962 82 jeremybenn
     screen dumps starting at zero.  The default value is `"fb_out"'.
1963 19 jeremybenn
     For backwards compatibility, the alternative name `filename' is
1964
     supported for this parameter, but deprecated.
1965
 
1966
 
1967

1968
File: or1ksim.info,  Node: Keyboard Configuration,  Next: Disc Interface Configuration,  Prev: Frame Buffer Configuration,  Up: Peripheral Configuration
1969
 
1970
3.4.8 Keyboard Configuration (PS2)
1971
----------------------------------
1972
 
1973 82 jeremybenn
The PS2 interface provided by Or1ksim is not documented.  It may be
1974 19 jeremybenn
based on the PS2 project at OpenCores, and found in the top level CVS
1975 82 jeremybenn
directory, `ps2'.  However this project lacks any documentation beyond
1976
its project webpage.  Since most PS2 interfaces follow the Intel i8042
1977 19 jeremybenn
standard, this is presumably what is expected with this device.
1978
 
1979
The implementation only provides for keyboard support, which is
1980 82 jeremybenn
modelled as a file of keystrokes.  There is no mouse support.
1981 19 jeremybenn
 
1982
     Caution: A standard i8042 device has two registers at addresses
1983 82 jeremybenn
     0x60 (command) and 0x64 (status).  Inspection of the code,
1984
     suggests that the Or1ksim component places these registers at
1985
     addresses 0x00 and 0x04.
1986 19 jeremybenn
 
1987
     The port of Linux for the OpenRISC 1000, which runs on Or1ksim
1988
     implements the i8042 device driver, anticipating these registers
1989 82 jeremybenn
     reside at their conventional address.  It seems unlikel that this
1990 19 jeremybenn
     code will work.
1991
 
1992
     This component should be used with caution.
1993
 
1994 82 jeremybenn
Keyboard configuration is described in `section kbd'.  This section may
1995
appear multiple times, specifying multiple keyboard interfaces.  The
1996 19 jeremybenn
following parameters may be specified.
1997
 
1998
`enabled = 0|1'
1999 82 jeremybenn
     If 1 (true, the default), this keyboard is enabled.  If 0, it is
2000 19 jeremybenn
     disabled.
2001
 
2002
`baseaddr = VALUE'
2003
     Set the base address of the keyboard's memory mapped registers to
2004 82 jeremybenn
     VALUE.  The default is 0, which is probably not a sensible value.
2005 19 jeremybenn
 
2006
     The keyboard PS/2 interface has an 3-bit address bus, with 2 8-bit
2007
     registers, at addresses 0x000 and 0x004.
2008
 
2009
          Caution: As noted above, a standard Intel 8042 interface
2010
          would expect to find these registers at locations 0x60 and
2011
          0x64, thus requiring at least a 7-bit bus.
2012
 
2013
`irq = VALUE'
2014 82 jeremybenn
     Use VALUE as the IRQ number of this Keyboard interface.  Default
2015 19 jeremybenn
     value 0.
2016
 
2017
`rxfile = "FILE"'
2018
     `file' specifies a file containing raw key stroke data, which
2019 82 jeremybenn
     models the input from a physical keyboard.  The default value is
2020 19 jeremybenn
     `"kbd_in"'.
2021
 
2022
 
2023

2024
File: or1ksim.info,  Node: Disc Interface Configuration,  Next: Generic Peripheral Configuration,  Prev: Keyboard Configuration,  Up: Peripheral Configuration
2025
 
2026
3.4.9 Disc Interface Configuration
2027
----------------------------------
2028
 
2029
The ATA/ATAPI disc controller used in Or1ksim is the OCIDEC (OpenCores
2030
IDE Controller) component implemented at OpenCores, and found in the
2031 82 jeremybenn
top level CVS directory, `ata'.  It is described in the document
2032 19 jeremybenn
`ATA/ATAPI-5 Core Specification' by Richard Herveille, which can be
2033 82 jeremybenn
found in the `doc' subdirectory.  It is a memory mapped component,
2034
which resides on the main OpenRISC Wishbone data bus.
2035 19 jeremybenn
 
2036 82 jeremybenn
ATA/ATAPI configuration is described in `section ata'.  This section
2037
may appear multiple times, specifying multiple disc controllers.  The
2038 19 jeremybenn
following parameters may be specified.
2039
 
2040
`enabled = 0|1'
2041 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2042 19 jeremybenn
     0, it is disabled.
2043
 
2044
`baseaddr = VALUE'
2045
     Set the base address of the ATA/ATAPI interface's memory mapped
2046 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2047 19 jeremybenn
     sensible value.
2048
 
2049
     The ATA/ATAPI PS/2 interface has an 5-bit address bus, with 8
2050 82 jeremybenn
     32-bit registers.  Depending on the version of the OCIDEC
2051
     ATA/ATAPI interface selected (see `dev_id' below), not all
2052
     registers will be available.
2053 19 jeremybenn
 
2054
`irq = VALUE'
2055 82 jeremybenn
     Use VALUE as the IRQ number of this ATA/ATAPI interface.  Default
2056 19 jeremybenn
     value 0.
2057
 
2058
`dev_id = 1|2|3'
2059
     This parameter specifies which version of the OCIDEC ATA/ATAPI
2060 82 jeremybenn
     interface to model.  The default value is 1.
2061 19 jeremybenn
 
2062
     Version 1 supports only the `CTRL', `STAT' and `PCTR' registers.
2063
     Versions 2 & 3 add the `FCTR' registers, Version 3 adds the `DTR'
2064
     registers and the `RXD'/`TXD' registers.
2065
 
2066
`rev = VALUE'
2067
     Set the VALUE as the revision of the OCIDEC ATA/ATAPI interface.
2068 82 jeremybenn
     The default value is 1.  The default value is 0.  Its value should
2069
     be in the range 0-15.  Larger values are truncated with a warning.
2070 19 jeremybenn
     This only affects the reset value of the `STAT' register, where it
2071
     forms bits 24-27.
2072
 
2073
`pio_mode0_t1 = VALUE'
2074
`pio_mode0_t2 = VALUE'
2075
`pio_mode0_t4 = VALUE'
2076
`pio_mode0_teoc = VALUE'
2077
     These parameters specify the timings for use with Programmed
2078 82 jeremybenn
     Input/Output (PIO) transfers.  They are specified as the number of
2079 19 jeremybenn
     clock cycles - 2, rounded up to the next highest integer, or zero
2080 82 jeremybenn
     if that would be negative.  The values should not exceed 255.  If
2081 19 jeremybenn
     they do, they will be ignored with a warning.
2082
 
2083
     See the ATA/ATAPI-5 specification for explanations of each of these
2084 82 jeremybenn
     timing parameters.  The default values are:
2085 19 jeremybenn
 
2086
          pio_mode0_t1   =  6
2087
          pio_mode0_t2   = 28
2088
          pio_mode0_t4   =  2
2089
          pio_mode0_teoc = 23
2090
 
2091
`dma_mode0_tm = VALUE'
2092
`dma_mode0_td = VALUE'
2093
`dma_mode0_teoc = VALUE'
2094
     These parameters specify the timings for use with DMA transfers.
2095
     They are specified as the number of clock cycles - 2, rounded up
2096
     to the next highest integer, or zero if that would be negative.
2097 82 jeremybenn
     The values should not exceed 255.  If they do, they will be
2098
     ignored with a warning.
2099 19 jeremybenn
 
2100
     See the ATA/ATAPI-5 specification for explanations of each of these
2101 82 jeremybenn
     timing parameters.  The default values are:
2102 19 jeremybenn
 
2103
          dma_mode0_tm   =  4
2104
          dma_mode0_td   = 21
2105
          dma_mode0_teoc = 21
2106
 
2107
 
2108
3.4.9.1 ATA/ATAPI Device Configuration
2109
......................................
2110
 
2111 82 jeremybenn
Within the `section ata', each device is specified separately.  The
2112 19 jeremybenn
device subsection is introduced by
2113
 
2114
     device VALUE
2115
 
2116 82 jeremybenn
VALUE is the device number, which should be 0 or 1.  The subsection
2117
ends with `enddevice'.  Note that if the same device number is
2118
specified more than once, the previous values will be overwritten.
2119
Within the `device' subsection, the following parameters may appear:
2120 19 jeremybenn
 
2121
`type = VALUE'
2122
     VALUEspecifies the type of device: 0 (the default) for "not
2123
     connected", 1 for hard disk simulated in a file and 2 for local
2124
     system hard disk.
2125
 
2126
`file = "FILENAME"'
2127
     `filename' specifies the file to be used for a simulated ATA
2128 82 jeremybenn
     device if the file type (see `type' above) is 1.  Default value
2129 19 jeremybenn
     `"ata-FileN"', where N is the device number.
2130
 
2131
`size = VALUE'
2132
     VALUE specifies the size of a simulated ATA device if the file
2133 82 jeremybenn
     type (see `type' above) is 1.  The default value is zero.
2134 19 jeremybenn
 
2135
`packet = 0|1'
2136 82 jeremybenn
     If 1 (true), implement the PACKET command feature set.  If 0 (the
2137 19 jeremybenn
     default), do not implement the PACKET command feature set.
2138
 
2139
`firmware = "STR"'
2140
     Firmware to report in response to the "Identify Device" command.
2141
     Default `"02207031"'.
2142
 
2143
`heads = VALUE'
2144 82 jeremybenn
     Number of heads in the device.  Default 7, use -1 to disable all
2145 19 jeremybenn
     heads.
2146
 
2147
`sectors = VALUE'
2148 82 jeremybenn
     Number of sectors per track in the device.  Default 32.
2149 19 jeremybenn
 
2150
`mwdma = 0|1|2|-1'
2151 82 jeremybenn
     Highest multi-word DMA mode supported.  Default 2, use -1 to
2152 19 jeremybenn
     disable.
2153
 
2154
`pio = 0|1|2|3|4'
2155 82 jeremybenn
     Highest PIO mode supported.  Default 4.
2156 19 jeremybenn
 
2157
 
2158

2159
File: or1ksim.info,  Node: Generic Peripheral Configuration,  Prev: Disc Interface Configuration,  Up: Peripheral Configuration
2160
 
2161
3.4.10 Generic Peripheral Configuration
2162
---------------------------------------
2163
 
2164
When used as a library (*note Simulator Library: Simulator Library.),
2165
Or1ksim makes provision for any additional peripheral to be implemented
2166 82 jeremybenn
externally.  Any read or write access to this peripheral's memory map
2167
generates "upcall"s to an external handler.  This interface can support
2168 19 jeremybenn
either C or C++, and was particularly designed to facilitate support
2169
for OSCI SystemC (see `http://www.systemc.org').
2170
 
2171
Generic peripheral configuration is described in `section generic'.
2172
This section may appear multiple times, specifying multiple external
2173 82 jeremybenn
peripherals.  The following parameters may be specified.
2174 19 jeremybenn
 
2175
`enabled = 0|1'
2176 82 jeremybenn
     If 1 (true, the default), this ATA/ATAPI interface is enabled.  If
2177 19 jeremybenn
     0, it is disabled.
2178
 
2179
`baseaddr = VALUE'
2180
     Set the base address of the generic peripheral's memory mapped
2181 82 jeremybenn
     registers to VALUE.  The default is 0, which is probably not a
2182 19 jeremybenn
     sensible value.
2183
 
2184
     The size of the memory mapped register space is controlled by the
2185
     `size' paramter, described below.
2186
 
2187
`size = VALUE'
2188
     Set the size of the generic peripheral's memory mapped register
2189 82 jeremybenn
     space to VALUE bytes.  Any read or write accesses to addresses with
2190 19 jeremybenn
     offsets of 0 to VALUE-1 bytes from the base address specified in
2191
     parameter `baseaddr' (see above) will be directed to the external
2192
     interface.
2193
 
2194 82 jeremybenn
     VALUE will be rounded up the nearest power of 2.  It's default
2195
     value is zero.  If VALUE is not an exact power of two, accesses to
2196 19 jeremybenn
     address offsets of VALUE or above up to the next power of 2 will
2197
     generate a warning, and have no effect (reads will return zero).
2198
 
2199
`name = "STR"'
2200 82 jeremybenn
     This gives the peripheral the name `"STR"'.  This is used to
2201 19 jeremybenn
     identify the peripheral in error messages and warnings, and when
2202 82 jeremybenn
     reporting its status.  The default value is
2203 19 jeremybenn
     `"anonymous external peripheral"'.
2204
 
2205
`byte_enabled = 0|1'
2206
`hw_enabled = 0|1'
2207
`word_enabled = 0|1'
2208
     If 1 (true, the default), these parameters respectively enable the
2209 82 jeremybenn
     device for byte wide, half-word wide and word wide accesses.  If 0,
2210 19 jeremybenn
     accesses of that width will fail.
2211
 
2212
 
2213

2214
File: or1ksim.info,  Node: Interactive Command Line,  Next: Verification API,  Prev: Configuration,  Up: Top
2215
 
2216
4 Interactive Command Line
2217
**************************
2218
 
2219
If started with the `-f' flag, or if interrupted with `ctrl-C', Or1ksim
2220 82 jeremybenn
provides the user with an interactive command line.  The commands
2221 19 jeremybenn
available, which may not be abbreviated, are:
2222
 
2223
`q'
2224
     Exit the simulator
2225
 
2226
`r'
2227 82 jeremybenn
     Display all the General Purpose Registers (GPRs).  Also shows the
2228 19 jeremybenn
     just executed and next to be executed instructions symbolically
2229
     and the state of the flag in the Supervision Register.
2230
 
2231
`t'
2232
     Execute the next instruction and then display register/instruction
2233
     information as with the `r' command (see above).
2234
 
2235
`run NUM [ hush ]'
2236 82 jeremybenn
     Execute NUM instructions.  The register/instruction information is
2237 19 jeremybenn
     displayed after each instruction, as with the `r' command (see
2238
     above) _unless_ `hush' is specified.
2239
 
2240
`pr REG VALUE'
2241
     Patch register REG with VALUE.
2242
 
2243
`dm FROMADDR [ TOADDR ]'
2244 82 jeremybenn
     Display memory bytes between FROMADDR and TOADDR.  If TOADDR is
2245
     not given, 64 bytes are displayed, starting at FROMADDR.
2246 19 jeremybenn
 
2247
          Caution: The output from this command is broken (a bug).
2248 82 jeremybenn
          Or1ksim attempts to print out 16 bytes per row.  However,
2249 19 jeremybenn
          instead of printing out the address at the start of each row,
2250
          it prints the address (of the first of the 16 bytes) before
2251
          _each_ byte.
2252
 
2253
`de FROMADDR [ TOADDR ]'
2254 82 jeremybenn
     Disassemble code between FROMADDR and TOADDR.  If TOADDR is not
2255 19 jeremybenn
     given, 16 instructions are disassembled.
2256
 
2257
     The disassembly is entirely numerical, and gives no symbolic
2258
     information.
2259
 
2260
`pm ADDR VALUE'
2261
     Patch the 4 bytes in memory starting at ADDR with the 32-bit VALUE.
2262
 
2263
`pc VALUE'
2264
     Patch the program counter with VALUE.
2265
 
2266
`cm FROMADDR TOADDR SIZE'
2267
     Copy SIZE bytes in memory from FROMADDR to TOADDR.
2268
 
2269
`break ADDR'
2270
     Toggle the breakpoint set at ADDR.
2271
 
2272
`breaks'
2273
     List all set breakpoints
2274
 
2275
`reset'
2276 82 jeremybenn
     Reset the simulator.  Includes modeling a reset of the processor,
2277
     so execution will restart from the reset vector location, 0x100.
2278 19 jeremybenn
 
2279
`hist'
2280
     If saving the execution history has been configured (*note
2281
     Simulator Behavior: Simulator Behavior.), display the execution
2282
     history.
2283
 
2284
`stall'
2285
     Stall the processor, so that control is passed to the debug unit.
2286 82 jeremybenn
     When stalled, the processor can execute no instructions.  This
2287 19 jeremybenn
     command is useful when debugging the JTAG interface, used by
2288
     debuggers such as GDB.
2289
 
2290
`unstall'
2291 82 jeremybenn
     Unstall the processor, so that normal execution can continue.
2292
     This command is useful when debugging the JTAG interface, used by
2293 19 jeremybenn
     debuggers such as GDB.
2294
 
2295
`stats CATEGORY | clear'
2296
     Print the statistics for the given CATEGORY, if available, or
2297 82 jeremybenn
     clear if `clear' is specified.  The categories are:
2298 19 jeremybenn
 
2299
    1
2300
          Miscellaneous statistics: branch predictions (if branch
2301
          predictions are enabled), branch target cache model (if
2302
          enabled), cache (if enbaled), MMU (if enabled) and number of
2303
          addtional load & store cycles.
2304
 
2305
          *Note Configuring the OpenRisc Achitectural Components: Core
2306
          OpenRISC Configuration, for details of how to enable these
2307
          various features.
2308
 
2309
    2
2310 82 jeremybenn
          Instruction usage statistics.  Requires hazard analysis to be
2311 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2312
 
2313
    3
2314 82 jeremybenn
          Instruction dependency statistics.  Requires hazard analysis
2315 19 jeremybenn
          to be enabled (*note CPU Configuration: CPU Configuration.).
2316
 
2317
    4
2318 82 jeremybenn
          Functional unit dependency statistics.  Requires hazard
2319 19 jeremybenn
          analysis to be enabled (*note CPU Configuration: CPU
2320
          Configuration.).
2321
 
2322
    5
2323 82 jeremybenn
          Raw register usage over time.  Requires hazard analysis to be
2324 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2325
 
2326
    6
2327 82 jeremybenn
          Store buffer statistics.  Requires the store buffer to be
2328 19 jeremybenn
          enabled (*note CPU Configuration: CPU Configuration.).
2329
 
2330
 
2331
`info'
2332
     Display detailed information about the simulator configuration.
2333
     This is quite a lengthy about, because all MMU TLB information is
2334
     displayed.
2335
 
2336
`dv FROMADDR [ TOADDR ] [ MODULE ]'
2337
     Dump the area of memory between FROMADDR and TOADDR as Verilog
2338 82 jeremybenn
     code for a synchronous, 23-bit wide SRAM module, named MODULE.  If
2339 19 jeremybenn
     TOADDR is not specified, then 64 bytes are dumped (as 16 32-bit
2340 82 jeremybenn
     words).  If MODULE is not specified, `or1k_mem' is used.
2341 19 jeremybenn
 
2342
     To save to a file, use the redirection function (described after
2343
     this table, below).
2344
 
2345
`dh FROMADDR [ TOADDR ]'
2346
     Dump the area of memory between FROMADDR and TOADDR as 32-bit hex
2347 82 jeremybenn
     numbers (no `0x', or `32'h' prefix).  If TOADDR is not specified,
2348 19 jeremybenn
     then 64 bytes are dumped (as 16 32-bit words).
2349
 
2350
     To save to a file, use the redirection function (described after
2351
     this table, below).
2352
 
2353
`setdbch'
2354 82 jeremybenn
     Toggle debug channels on/off.  *Note Standalone Simulator:
2355 19 jeremybenn
     Standalone Simulator, for a description of specifying debug
2356
     channels on the command line.
2357
 
2358
`set SECTION PARAM = VALUE'
2359
     Set the configuration parameter PARA in section SECTION to VALUE.
2360
     *Note Configuration: Configuration, for details of configuration
2361
     parameters and their settings.
2362
 
2363
`debug'
2364 82 jeremybenn
     Toggle the simulator debug mode.  *Note Debug Interface
2365 19 jeremybenn
     Configuration: Debug Interface Configuration, for information on
2366
     this parameter.
2367
 
2368
          Caution: This is effectively enabling or disabling the debug
2369 82 jeremybenn
          unit.  It does not effect the remote GDB debug interface.
2370 19 jeremybenn
          However using the remote debug interface while the debug unit
2371
          is disabled will lead to undefined behavior and likely crash
2372
          Or1ksim
2373
 
2374
`cuc'
2375
     Enter the the Custom Unit Compiler command prompt (*note CUC
2376
     Configuration: CUC Configuration.).
2377
 
2378
          Caution: The CUC must be properly configured, for this to
2379 82 jeremybenn
          succeed.  In particular a timing file must be available and
2380
          readable.  Otherwise Or1ksim will crash.
2381 19 jeremybenn
 
2382
`help'
2383
     Print out brief information about each command available.
2384
 
2385
`mprofile [-vh] [-m M] [-g N] [-f FILE] FROM TO'
2386 82 jeremybenn
     Run the memory profiling utility.  This follows the same usage as
2387 19 jeremybenn
     the standalone command (*note Memory Profiling Utility: Memory
2388
     Profiling Utility.).
2389
 
2390
`profile [-vhcq] [-g FILE]'
2391 82 jeremybenn
     Run the instruction profiling utility.  This follows the same
2392
     usage as the standalone command (*note Profiling Utility:
2393
     Profiling Utility.).
2394 19 jeremybenn
 
2395
 
2396
For all commands, it is possible to redirect the output to a file, by
2397
using the redirection operator, `>'.
2398
 
2399
     COMMAND > FILENAME
2400
 
2401
This is particularly useful for commands dumping a large amount of
2402
output, such as `dv'.
2403
 
2404
     Caution: Unfortunately there is a serious bug with the redirection
2405 82 jeremybenn
     operator.  It does not return output to standard output after the
2406
     command completes.  Until this bug is fixed, file redirection
2407 19 jeremybenn
     should not be used.
2408
 
2409

2410
File: or1ksim.info,  Node: Verification API,  Next: Code Internals,  Prev: Interactive Command Line,  Up: Top
2411
 
2412
5 Verification API (VAPI)
2413
*************************
2414
 
2415
The Verification API (VAPI) provides a TCP/IP interface to allow
2416 82 jeremybenn
components of the simulation to be controlled externally.  The
2417
interface is polled for new requests on each simulated clock cycle.
2418
Components within the simulator may send responses to such requests.
2419 19 jeremybenn
 
2420 82 jeremybenn
The inteface is an asynchronous duplex protocol.  On the request side
2421
it provides for simple commands, known as VAPI IDs (a 32 bit integer),
2422
with a single piece of data (also a 32 bit integer).  On the send side,
2423
it provides for sending a single VAPI ID and data.  However there is no
2424
explicit command-response structure.  Some components just accept
2425
requests (e.g.  to set values), some just generate sends (to report
2426 19 jeremybenn
values), and some do both.
2427
 
2428
Each component has a base ID (32 bit) and its commands will start from
2429 82 jeremybenn
that base ID.  This provides a simple partitioning of the command space
2430
amongst components.  Request commands will be directed to the component
2431 19 jeremybenn
with the closest base ID lower than the VAPI ID of the command.
2432
 
2433
Thus if there are two components with base IDs of 0x200 and 0x300, and
2434
a request with VAPI ID of 0x203 is received, it will be directed to the
2435
first component as its command #3.
2436
 
2437
The results of VAPI interactions are logged (by default in `vapi.log'
2438
unless an alternative is specified in `section vapi').
2439
 
2440
Currently the following components support VAPI:
2441
 
2442
Debug Unit
2443
     Although the Debug Unit can specify a base VAPI ID, it is not used
2444
     to send commands or receive requests.
2445
 
2446
     Instead, if the base VAPI ID is set, all remote JTAG protocol
2447
     exchanges are logged in the VAPI log file.
2448
 
2449
UART
2450
     If a base VAPI ID is specified, the UART sends details of any
2451
     chars or break characters sent, with dteails of the line control
2452
     register etc encoded in the data packet sent.
2453
 
2454
     This supports a single VAPI command request, but encodes a
2455
     sub-command in the top 8 bits of the associated data.
2456
 
2457
    `0x00'
2458
          This stuffs the least significant 8 bits of the data into the
2459
          serial register of the UART and the next 8 bits into the line
2460
          control register, effectively providing control of the next
2461
          character to be sent or received.
2462
 
2463
    `0x01'
2464
          The divisor latch bytes are set from the least significant 16
2465
          bits of the data.
2466
 
2467
    `0x02'
2468
          The line control register is set from bits 15-8 of the data.
2469
 
2470
    `0x03'
2471
          The UART skew is set from the least significant 16 bits of
2472
          the data
2473
 
2474
    `0x04'
2475
          If the 16th most significant bit of the data is 1, start
2476 82 jeremybenn
          sending breaks, otherwise stop sending breaks.  The breaks
2477
          are sent or cleared after the number of UART clock divider
2478
          ticks specified by the data (immediately if the data is zero).
2479 19 jeremybenn
 
2480
 
2481
DMA
2482
     Although the DMA unit supports a base VAPI ID in its configuration
2483
     (`section dma'), no VAPI data is sent, nor VAPI requests currently
2484
     implemented.
2485
 
2486
Ethernet
2487 82 jeremybenn
     The following requests are handled by the Ethernet.  Specified
2488 19 jeremybenn
     symbolically, these are the increments from the base VAPI ID of the
2489 82 jeremybenn
     Ethernet.  At present no implementation is provided behind these
2490 19 jeremybenn
     VAPI requests.
2491
 
2492
    `ETH_VAPI_DATA (0)'
2493
 
2494
    `ETH_VAPI_CTRL (0)'
2495
 
2496
GPIO
2497
     If a base VAPI ID is specified, the GPIO sends out on its base
2498
     VAPI ID (symbolically, GPIO_VAPI_DATA (0) offset from the base
2499
     VAPI ID) any changes in outputs.
2500
 
2501 82 jeremybenn
     The following requests are handled by the GPIO.  Specified
2502 19 jeremybenn
     symbolically, these are the increments from the VAPI base ID of the
2503
     GPIO.
2504
 
2505
    `GPIO_VAPI_DATA (0)'
2506
          Set the next input to the commands data field
2507
 
2508
    `GPIO_VAPI_AUX (1)'
2509
          Set the GPIO auxiliary inputs to the data field
2510
 
2511
    `GPIO_VAPI_CLOCK (2)'
2512
          Add an external GPIO clock trigger of period specified in the
2513
          data field.
2514
 
2515
    `GPIO_VAPI_RGPIO_OE (3)'
2516
          Set the GPIO output enable to the data field
2517
 
2518
    `GPIO_VAPI_RGPIO_INTE (4)'
2519
          Set the next interrupt to the data field
2520
 
2521
    `GPIO_VAPI_RGPIO_PTRIG (5)'
2522
          Set the next trigger to the data field
2523
 
2524
    `GPIO_VAPI_RGPIO_AUX (6)'
2525
          Set the next auxiliary input to the data field
2526
 
2527
    `GPIO_VAPI_RGPIO_CTRL (7)'
2528
          Set th next control input to the data field
2529
 
2530
 
2531
 
2532

2533
File: or1ksim.info,  Node: Code Internals,  Next: GNU Free Documentation License,  Prev: Verification API,  Up: Top
2534
 
2535
6 A Guide to Or1ksim Internals
2536
******************************
2537
 
2538 82 jeremybenn
These are notes to help those wanting to extend Or1ksim.  This section
2539 19 jeremybenn
assumes the use of a tag file, so file locations of entities'
2540 82 jeremybenn
definitions are not in general provided.  For more on tags, see the
2541
Linux manual page for `etags'.  A tag file can be created with:
2542 19 jeremybenn
 
2543
     make tags
2544
 
2545
* Menu:
2546
 
2547
* Coding Conventions::
2548
* Global Data Structures::
2549
* Concepts::
2550
* Internal Debugging::
2551
 
2552

2553
File: or1ksim.info,  Node: Coding Conventions,  Next: Global Data Structures,  Up: Code Internals
2554
 
2555
6.1 Coding Conventions for Or1ksim
2556
==================================
2557
 
2558
This chapter provides some guidelines for coding, to facilitate
2559
extensions to Or1ksim
2560
 
2561
_GNU Coding Standard_
2562
     Code should follow the GNU coding standard for C
2563 82 jeremybenn
     (`http://www.gnu.org/prep/standards/'.  If in doubt, put your code
2564 19 jeremybenn
     through the `indent' program.
2565
 
2566
_`#include' headers_
2567
     All C source code files should include `config.h' before any other
2568
     file.
2569
 
2570
     This should be followed by inclusion of any system headers (but see
2571
     the comments about portability and `port.h' below) and then by any
2572
     Or1ksim package headers.
2573
 
2574
     If `port.h' is required, it should be the first package header to
2575
     be included after the system headers.
2576
 
2577
     All C source code and header files should directly include any
2578 82 jeremybenn
     system or package header they depend on, i.e.  not rely on any
2579
     other header having already included it.  The two exceptions are
2580 19 jeremybenn
 
2581
       1. All header files may assume that `config.h' has already been
2582
          included.
2583
 
2584
       2. System headers which impose portability problems should be
2585
          included by using the package header `port.h', rather than
2586 82 jeremybenn
          the system headers themselves.  This is the case for code
2587 19 jeremybenn
          requiring
2588
 
2589
             * `strndup' (from `string.h')
2590
 
2591
             * Integer types (`intN_t', `uintN_t') (from `inttypes.h').
2592
 
2593
             * `isblank' (from `ctype.h')
2594
 
2595
 
2596
 
2597
_`#include' files once only_
2598
     All include files should be protected by `#ifndef' to ensure their
2599 82 jeremybenn
     definitions are only included once.  For instance a header file
2600 19 jeremybenn
     `X-Y.H' should surround its contents with:
2601
 
2602
          #ifndef X_Y__H
2603
          #define X_Y__H
2604
 
2605
          
2606
 
2607
          #endif  /* X_Y__H */
2608
 
2609
_Avoid `typedef'_
2610
     The GNU coding style for C does not have a clear way to distinguish
2611 82 jeremybenn
     between user type name and user variables.  For this reason
2612 19 jeremybenn
     `typedef' should be avoided except for the most ubiquitous user
2613 82 jeremybenn
     defined types.  This makes the code much easier to read.
2614 19 jeremybenn
 
2615
     There are some `typedef' declarations in the `argtable2' library
2616
     and the ELF and COFF headers, because this code is taken from
2617
     other places.
2618
 
2619
     Within Or1ksim legacy uses of `typedef' have largely been purged,
2620
     except in the Custom Unit Compiler (*note Custom Unit Compiler
2621
     (CUC) Configuration: CUC Configuration.).
2622
 
2623
     The remaining uses of `typedef' occur in two places:
2624
 
2625
        * `port/port.h' defines types to replace those in header files
2626
          that are not available (character functions, string
2627
          duplication, integer types).
2628
 
2629
          `cpu/or1k/arch.h' defines types for the key Or1ksim entities:
2630
          addresses (`oraddr_t'), unsigned register values (`uorreg_t')
2631
          and signed register (`orreg_t') values.
2632
 
2633
 
2634
     Where new types are defined, they should appear in one of these two
2635 82 jeremybenn
     files as appropriate.  Or1ksim specific types appearing in
2636
     `arch.h' should always have the suffix `_h'.
2637 19 jeremybenn
 
2638
_Don't begin names with underscore_
2639
     Names beginning with `_' are intended to be part of the C
2640 82 jeremybenn
     infrastructure.  They should not be used in the simulator code.
2641 19 jeremybenn
 
2642
_Keep Non-global top level entities static_
2643
     All top level entities (functions, variables), which are not
2644
     explicitly part of a global interface should be declared static.
2645
     This ensures that unwanted connections are not inadvertently built
2646
     across the program.
2647
 
2648
_Use of `inline'_
2649 82 jeremybenn
     Code should not be declared `inline'.  Modern compilers can work
2650 19 jeremybenn
     out for themselves what is best in this respect.
2651
 
2652
_Initialization_
2653 82 jeremybenn
     All data structures should be explicitly initialized.  In
2654
     particular code should not rely on static data structures being
2655
     initialized to zero.
2656 19 jeremybenn
 
2657
     The rationale is that in future static data structures may become
2658 82 jeremybenn
     dynamic.  This has been a particular source of bugs in Or1ksim
2659 19 jeremybenn
     historically.
2660
 
2661
     A specific case is with new peripherals, which should always
2662
     include a `start' function to pre-initialize all configuration
2663
     parameters to sensible defaults
2664
 
2665
_Configuration Validation_
2666
     All configuration values should be validated, preferably when
2667
     encountered, if not when the `section' is closed, or otherwise at
2668
     run time when the parameter is first used.
2669
 
2670
 
2671

2672
File: or1ksim.info,  Node: Global Data Structures,  Next: Concepts,  Prev: Coding Conventions,  Up: Code Internals
2673
 
2674
6.2 Global Data Structures
2675
==========================
2676
 
2677
`config'
2678
     The global variable `config' of type `struct config' holds the
2679
     configuration data for some of the Or1ksim components which are
2680 82 jeremybenn
     always present.  At present the components are:
2681 19 jeremybenn
 
2682
        * The simulator defined in `section sim' (*note Simulator
2683
          Configuration: Simulator Configuration.).
2684
 
2685
        * The Verification API (VAPI) defined  in `section vapi' (*note
2686
          Verification API (VAPI) Configuration: Verification API
2687
          Configuration.).
2688
 
2689
        * The Custom Unit Compiler (CUC), defined in `section cuc'
2690
          (*note Custom Unit Compiler (CUC) Configuration: CUC
2691
          Configuration.).
2692
 
2693
        * The CPU, defined in `section cpu' (*note CPU Configuration:
2694
          CPU Configuration.).
2695
 
2696
        * The data cache (but not the instruction cache), defined in
2697
          `section dc' (*note Cache Configuration: Cache
2698
          Configuration.).
2699
 
2700
        * The power management unit, defined in `section pm' (*note
2701
          Power Management Configuration: Power Management
2702
          Configuration.).
2703
 
2704
        * The programmable interrupt controller, defined in
2705
          `section pic' (*note Interrupt Configuration: Interrupt
2706
          Configuration.).
2707
 
2708
        * Branch prediciton, defined in `section bpb' (*note Branch
2709
          Prediction Configuration: Branch Prediction Configuration.).
2710
 
2711
        * The debug unit, defined in `section debug' (*note Debug
2712
          Interface Configuration: Debug Interface Configuration.).
2713
 
2714
 
2715
     This struct is made of a collection of structs, one for each
2716 82 jeremybenn
     component.  For example the simulator configuration is held in
2717 19 jeremybenn
     `config.sim'.
2718
 
2719
`config'
2720
     This is a linked list of data structures holding configuration data
2721
     for all sections which are not held in the main `config' data
2722 82 jeremybenn
     structure.  In general these are components (such as peripherals
2723
     and memory) which may occur multiple times.  However it also
2724
     handles some architectural components which may occur only once,
2725
     such as the memory management units, the instruction cache, the
2726
     interrupt controller and branch prediction.
2727 19 jeremybenn
 
2728
`runtime'
2729
     The global variable `runtime' of type `struct runtime' holds all
2730 82 jeremybenn
     the runtime information about the simulation.  To access this
2731 19 jeremybenn
     variable, `sim-config.h' must be included.
2732
 
2733
     This struct is itself made of 3 other structs, `cpu' (for CPU run
2734
     time state), `vapi' (for Verification API state) and `cuc' (for
2735
     Custom Unit Compiler state).
2736
 
2737
 
2738

2739
File: or1ksim.info,  Node: Concepts,  Next: Internal Debugging,  Prev: Global Data Structures,  Up: Code Internals
2740
 
2741
6.3 Concepts
2742
============
2743
 
2744
_Output Redirection_
2745 82 jeremybenn
     The current output stream is held in `runtime.cpu.fout'.  Output
2746 19 jeremybenn
     should be explicitly written to this stream, or may use the
2747
     `PRINTF' macro, which will write its arguments to this output
2748
     stream.
2749
 
2750
_Reset Hooks_
2751
     Any peripheral may register a routine to be called when the the
2752
     processor is reset by calling `reg_sim_reset', providing a
2753 82 jeremybenn
     function and pointer to a data structure as arguments.  On reset
2754 19 jeremybenn
     that function will be called with the data stucture pointer as
2755
     argument.
2756
 
2757
 
2758

2759
File: or1ksim.info,  Node: Internal Debugging,  Prev: Concepts,  Up: Code Internals
2760
 
2761
6.4 Internal Debugging
2762
======================
2763
 
2764
The function `debug' is like `printf', but with an extra first
2765 82 jeremybenn
argument, which is the debug level.  If the debug level specified in
2766
the simulator configuration (*note Simulator Behavior: Simulator
2767
Behavior.) is greater than or equal to this value, the remaining
2768
arguments are printed to the current output stream (*note Output
2769
Redirection: Output Redirection.).
2770 19 jeremybenn
 
2771

2772
File: or1ksim.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Code Internals,  Up: Top
2773
 
2774
7 GNU Free Documentation License
2775
********************************
2776
 
2777
                      Version 1.2, November 2002
2778
 
2779
     Copyright (C) 2000,2001,2002 Free Software Foundation, Inc.
2780
     51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
2781
 
2782
     Everyone is permitted to copy and distribute verbatim copies
2783
     of this license document, but changing it is not allowed.
2784
 
2785
  0. PREAMBLE
2786
 
2787
     The purpose of this License is to make a manual, textbook, or other
2788
     functional and useful document "free" in the sense of freedom: to
2789
     assure everyone the effective freedom to copy and redistribute it,
2790
     with or without modifying it, either commercially or
2791
     noncommercially.  Secondarily, this License preserves for the
2792
     author and publisher a way to get credit for their work, while not
2793
     being considered responsible for modifications made by others.
2794
 
2795
     This License is a kind of "copyleft", which means that derivative
2796
     works of the document must themselves be free in the same sense.
2797
     It complements the GNU General Public License, which is a copyleft
2798
     license designed for free software.
2799
 
2800
     We have designed this License in order to use it for manuals for
2801
     free software, because free software needs free documentation: a
2802
     free program should come with manuals providing the same freedoms
2803
     that the software does.  But this License is not limited to
2804
     software manuals; it can be used for any textual work, regardless
2805
     of subject matter or whether it is published as a printed book.
2806
     We recommend this License principally for works whose purpose is
2807
     instruction or reference.
2808
 
2809
  1. APPLICABILITY AND DEFINITIONS
2810
 
2811
     This License applies to any manual or other work, in any medium,
2812
     that contains a notice placed by the copyright holder saying it
2813
     can be distributed under the terms of this License.  Such a notice
2814
     grants a world-wide, royalty-free license, unlimited in duration,
2815
     to use that work under the conditions stated herein.  The
2816
     "Document", below, refers to any such manual or work.  Any member
2817
     of the public is a licensee, and is addressed as "you".  You
2818
     accept the license if you copy, modify or distribute the work in a
2819
     way requiring permission under copyright law.
2820
 
2821
     A "Modified Version" of the Document means any work containing the
2822
     Document or a portion of it, either copied verbatim, or with
2823
     modifications and/or translated into another language.
2824
 
2825
     A "Secondary Section" is a named appendix or a front-matter section
2826
     of the Document that deals exclusively with the relationship of the
2827
     publishers or authors of the Document to the Document's overall
2828
     subject (or to related matters) and contains nothing that could
2829
     fall directly within that overall subject.  (Thus, if the Document
2830
     is in part a textbook of mathematics, a Secondary Section may not
2831
     explain any mathematics.)  The relationship could be a matter of
2832
     historical connection with the subject or with related matters, or
2833
     of legal, commercial, philosophical, ethical or political position
2834
     regarding them.
2835
 
2836
     The "Invariant Sections" are certain Secondary Sections whose
2837
     titles are designated, as being those of Invariant Sections, in
2838
     the notice that says that the Document is released under this
2839
     License.  If a section does not fit the above definition of
2840
     Secondary then it is not allowed to be designated as Invariant.
2841
     The Document may contain zero Invariant Sections.  If the Document
2842
     does not identify any Invariant Sections then there are none.
2843
 
2844
     The "Cover Texts" are certain short passages of text that are
2845
     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
2846
     that says that the Document is released under this License.  A
2847
     Front-Cover Text may be at most 5 words, and a Back-Cover Text may
2848
     be at most 25 words.
2849
 
2850
     A "Transparent" copy of the Document means a machine-readable copy,
2851
     represented in a format whose specification is available to the
2852
     general public, that is suitable for revising the document
2853
     straightforwardly with generic text editors or (for images
2854
     composed of pixels) generic paint programs or (for drawings) some
2855
     widely available drawing editor, and that is suitable for input to
2856
     text formatters or for automatic translation to a variety of
2857
     formats suitable for input to text formatters.  A copy made in an
2858
     otherwise Transparent file format whose markup, or absence of
2859
     markup, has been arranged to thwart or discourage subsequent
2860
     modification by readers is not Transparent.  An image format is
2861
     not Transparent if used for any substantial amount of text.  A
2862
     copy that is not "Transparent" is called "Opaque".
2863
 
2864
     Examples of suitable formats for Transparent copies include plain
2865
     ASCII without markup, Texinfo input format, LaTeX input format,
2866
     SGML or XML using a publicly available DTD, and
2867
     standard-conforming simple HTML, PostScript or PDF designed for
2868
     human modification.  Examples of transparent image formats include
2869
     PNG, XCF and JPG.  Opaque formats include proprietary formats that
2870
     can be read and edited only by proprietary word processors, SGML or
2871
     XML for which the DTD and/or processing tools are not generally
2872
     available, and the machine-generated HTML, PostScript or PDF
2873
     produced by some word processors for output purposes only.
2874
 
2875
     The "Title Page" means, for a printed book, the title page itself,
2876
     plus such following pages as are needed to hold, legibly, the
2877
     material this License requires to appear in the title page.  For
2878
     works in formats which do not have any title page as such, "Title
2879
     Page" means the text near the most prominent appearance of the
2880
     work's title, preceding the beginning of the body of the text.
2881
 
2882
     A section "Entitled XYZ" means a named subunit of the Document
2883
     whose title either is precisely XYZ or contains XYZ in parentheses
2884
     following text that translates XYZ in another language.  (Here XYZ
2885
     stands for a specific section name mentioned below, such as
2886
     "Acknowledgements", "Dedications", "Endorsements", or "History".)
2887
     To "Preserve the Title" of such a section when you modify the
2888
     Document means that it remains a section "Entitled XYZ" according
2889
     to this definition.
2890
 
2891
     The Document may include Warranty Disclaimers next to the notice
2892
     which states that this License applies to the Document.  These
2893
     Warranty Disclaimers are considered to be included by reference in
2894
     this License, but only as regards disclaiming warranties: any other
2895
     implication that these Warranty Disclaimers may have is void and
2896
     has no effect on the meaning of this License.
2897
 
2898
  2. VERBATIM COPYING
2899
 
2900
     You may copy and distribute the Document in any medium, either
2901
     commercially or noncommercially, provided that this License, the
2902
     copyright notices, and the license notice saying this License
2903
     applies to the Document are reproduced in all copies, and that you
2904
     add no other conditions whatsoever to those of this License.  You
2905
     may not use technical measures to obstruct or control the reading
2906
     or further copying of the copies you make or distribute.  However,
2907
     you may accept compensation in exchange for copies.  If you
2908
     distribute a large enough number of copies you must also follow
2909
     the conditions in section 3.
2910
 
2911
     You may also lend copies, under the same conditions stated above,
2912
     and you may publicly display copies.
2913
 
2914
  3. COPYING IN QUANTITY
2915
 
2916
     If you publish printed copies (or copies in media that commonly
2917
     have printed covers) of the Document, numbering more than 100, and
2918
     the Document's license notice requires Cover Texts, you must
2919
     enclose the copies in covers that carry, clearly and legibly, all
2920
     these Cover Texts: Front-Cover Texts on the front cover, and
2921
     Back-Cover Texts on the back cover.  Both covers must also clearly
2922
     and legibly identify you as the publisher of these copies.  The
2923
     front cover must present the full title with all words of the
2924
     title equally prominent and visible.  You may add other material
2925
     on the covers in addition.  Copying with changes limited to the
2926
     covers, as long as they preserve the title of the Document and
2927
     satisfy these conditions, can be treated as verbatim copying in
2928
     other respects.
2929
 
2930
     If the required texts for either cover are too voluminous to fit
2931
     legibly, you should put the first ones listed (as many as fit
2932
     reasonably) on the actual cover, and continue the rest onto
2933
     adjacent pages.
2934
 
2935
     If you publish or distribute Opaque copies of the Document
2936
     numbering more than 100, you must either include a
2937
     machine-readable Transparent copy along with each Opaque copy, or
2938
     state in or with each Opaque copy a computer-network location from
2939
     which the general network-using public has access to download
2940
     using public-standard network protocols a complete Transparent
2941
     copy of the Document, free of added material.  If you use the
2942
     latter option, you must take reasonably prudent steps, when you
2943
     begin distribution of Opaque copies in quantity, to ensure that
2944
     this Transparent copy will remain thus accessible at the stated
2945
     location until at least one year after the last time you
2946
     distribute an Opaque copy (directly or through your agents or
2947
     retailers) of that edition to the public.
2948
 
2949
     It is requested, but not required, that you contact the authors of
2950
     the Document well before redistributing any large number of
2951
     copies, to give them a chance to provide you with an updated
2952
     version of the Document.
2953
 
2954
  4. MODIFICATIONS
2955
 
2956
     You may copy and distribute a Modified Version of the Document
2957
     under the conditions of sections 2 and 3 above, provided that you
2958
     release the Modified Version under precisely this License, with
2959
     the Modified Version filling the role of the Document, thus
2960
     licensing distribution and modification of the Modified Version to
2961
     whoever possesses a copy of it.  In addition, you must do these
2962
     things in the Modified Version:
2963
 
2964
       A. Use in the Title Page (and on the covers, if any) a title
2965
          distinct from that of the Document, and from those of
2966
          previous versions (which should, if there were any, be listed
2967
          in the History section of the Document).  You may use the
2968
          same title as a previous version if the original publisher of
2969
          that version gives permission.
2970
 
2971
       B. List on the Title Page, as authors, one or more persons or
2972
          entities responsible for authorship of the modifications in
2973
          the Modified Version, together with at least five of the
2974
          principal authors of the Document (all of its principal
2975
          authors, if it has fewer than five), unless they release you
2976
          from this requirement.
2977
 
2978
       C. State on the Title page the name of the publisher of the
2979
          Modified Version, as the publisher.
2980
 
2981
       D. Preserve all the copyright notices of the Document.
2982
 
2983
       E. Add an appropriate copyright notice for your modifications
2984
          adjacent to the other copyright notices.
2985
 
2986
       F. Include, immediately after the copyright notices, a license
2987
          notice giving the public permission to use the Modified
2988
          Version under the terms of this License, in the form shown in
2989
          the Addendum below.
2990
 
2991
       G. Preserve in that license notice the full lists of Invariant
2992
          Sections and required Cover Texts given in the Document's
2993
          license notice.
2994
 
2995
       H. Include an unaltered copy of this License.
2996
 
2997
       I. Preserve the section Entitled "History", Preserve its Title,
2998
          and add to it an item stating at least the title, year, new
2999
          authors, and publisher of the Modified Version as given on
3000
          the Title Page.  If there is no section Entitled "History" in
3001
          the Document, create one stating the title, year, authors,
3002
          and publisher of the Document as given on its Title Page,
3003
          then add an item describing the Modified Version as stated in
3004
          the previous sentence.
3005
 
3006
       J. Preserve the network location, if any, given in the Document
3007
          for public access to a Transparent copy of the Document, and
3008
          likewise the network locations given in the Document for
3009
          previous versions it was based on.  These may be placed in
3010
          the "History" section.  You may omit a network location for a
3011
          work that was published at least four years before the
3012
          Document itself, or if the original publisher of the version
3013
          it refers to gives permission.
3014
 
3015
       K. For any section Entitled "Acknowledgements" or "Dedications",
3016
          Preserve the Title of the section, and preserve in the
3017
          section all the substance and tone of each of the contributor
3018
          acknowledgements and/or dedications given therein.
3019
 
3020
       L. Preserve all the Invariant Sections of the Document,
3021
          unaltered in their text and in their titles.  Section numbers
3022
          or the equivalent are not considered part of the section
3023
          titles.
3024
 
3025
       M. Delete any section Entitled "Endorsements".  Such a section
3026
          may not be included in the Modified Version.
3027
 
3028
       N. Do not retitle any existing section to be Entitled
3029
          "Endorsements" or to conflict in title with any Invariant
3030
          Section.
3031
 
3032
       O. Preserve any Warranty Disclaimers.
3033
 
3034
     If the Modified Version includes new front-matter sections or
3035
     appendices that qualify as Secondary Sections and contain no
3036
     material copied from the Document, you may at your option
3037
     designate some or all of these sections as invariant.  To do this,
3038
     add their titles to the list of Invariant Sections in the Modified
3039
     Version's license notice.  These titles must be distinct from any
3040
     other section titles.
3041
 
3042
     You may add a section Entitled "Endorsements", provided it contains
3043
     nothing but endorsements of your Modified Version by various
3044
     parties--for example, statements of peer review or that the text
3045
     has been approved by an organization as the authoritative
3046
     definition of a standard.
3047
 
3048
     You may add a passage of up to five words as a Front-Cover Text,
3049
     and a passage of up to 25 words as a Back-Cover Text, to the end
3050
     of the list of Cover Texts in the Modified Version.  Only one
3051
     passage of Front-Cover Text and one of Back-Cover Text may be
3052
     added by (or through arrangements made by) any one entity.  If the
3053
     Document already includes a cover text for the same cover,
3054
     previously added by you or by arrangement made by the same entity
3055
     you are acting on behalf of, you may not add another; but you may
3056
     replace the old one, on explicit permission from the previous
3057
     publisher that added the old one.
3058
 
3059
     The author(s) and publisher(s) of the Document do not by this
3060
     License give permission to use their names for publicity for or to
3061
     assert or imply endorsement of any Modified Version.
3062
 
3063
  5. COMBINING DOCUMENTS
3064
 
3065
     You may combine the Document with other documents released under
3066
     this License, under the terms defined in section 4 above for
3067
     modified versions, provided that you include in the combination
3068
     all of the Invariant Sections of all of the original documents,
3069
     unmodified, and list them all as Invariant Sections of your
3070
     combined work in its license notice, and that you preserve all
3071
     their Warranty Disclaimers.
3072
 
3073
     The combined work need only contain one copy of this License, and
3074
     multiple identical Invariant Sections may be replaced with a single
3075
     copy.  If there are multiple Invariant Sections with the same name
3076
     but different contents, make the title of each such section unique
3077
     by adding at the end of it, in parentheses, the name of the
3078
     original author or publisher of that section if known, or else a
3079
     unique number.  Make the same adjustment to the section titles in
3080
     the list of Invariant Sections in the license notice of the
3081
     combined work.
3082
 
3083
     In the combination, you must combine any sections Entitled
3084
     "History" in the various original documents, forming one section
3085
     Entitled "History"; likewise combine any sections Entitled
3086
     "Acknowledgements", and any sections Entitled "Dedications".  You
3087
     must delete all sections Entitled "Endorsements."
3088
 
3089
  6. COLLECTIONS OF DOCUMENTS
3090
 
3091
     You may make a collection consisting of the Document and other
3092
     documents released under this License, and replace the individual
3093
     copies of this License in the various documents with a single copy
3094
     that is included in the collection, provided that you follow the
3095
     rules of this License for verbatim copying of each of the
3096
     documents in all other respects.
3097
 
3098
     You may extract a single document from such a collection, and
3099
     distribute it individually under this License, provided you insert
3100
     a copy of this License into the extracted document, and follow
3101
     this License in all other respects regarding verbatim copying of
3102
     that document.
3103
 
3104
  7. AGGREGATION WITH INDEPENDENT WORKS
3105
 
3106
     A compilation of the Document or its derivatives with other
3107
     separate and independent documents or works, in or on a volume of
3108
     a storage or distribution medium, is called an "aggregate" if the
3109
     copyright resulting from the compilation is not used to limit the
3110
     legal rights of the compilation's users beyond what the individual
3111
     works permit.  When the Document is included in an aggregate, this
3112
     License does not apply to the other works in the aggregate which
3113
     are not themselves derivative works of the Document.
3114
 
3115
     If the Cover Text requirement of section 3 is applicable to these
3116
     copies of the Document, then if the Document is less than one half
3117
     of the entire aggregate, the Document's Cover Texts may be placed
3118
     on covers that bracket the Document within the aggregate, or the
3119
     electronic equivalent of covers if the Document is in electronic
3120
     form.  Otherwise they must appear on printed covers that bracket
3121
     the whole aggregate.
3122
 
3123
  8. TRANSLATION
3124
 
3125
     Translation is considered a kind of modification, so you may
3126
     distribute translations of the Document under the terms of section
3127
     4.  Replacing Invariant Sections with translations requires special
3128
     permission from their copyright holders, but you may include
3129
     translations of some or all Invariant Sections in addition to the
3130
     original versions of these Invariant Sections.  You may include a
3131
     translation of this License, and all the license notices in the
3132
     Document, and any Warranty Disclaimers, provided that you also
3133
     include the original English version of this License and the
3134
     original versions of those notices and disclaimers.  In case of a
3135
     disagreement between the translation and the original version of
3136
     this License or a notice or disclaimer, the original version will
3137
     prevail.
3138
 
3139
     If a section in the Document is Entitled "Acknowledgements",
3140
     "Dedications", or "History", the requirement (section 4) to
3141
     Preserve its Title (section 1) will typically require changing the
3142
     actual title.
3143
 
3144
  9. TERMINATION
3145
 
3146
     You may not copy, modify, sublicense, or distribute the Document
3147
     except as expressly provided for under this License.  Any other
3148
     attempt to copy, modify, sublicense or distribute the Document is
3149
     void, and will automatically terminate your rights under this
3150
     License.  However, parties who have received copies, or rights,
3151
     from you under this License will not have their licenses
3152
     terminated so long as such parties remain in full compliance.
3153
 
3154
 10. FUTURE REVISIONS OF THIS LICENSE
3155
 
3156
     The Free Software Foundation may publish new, revised versions of
3157
     the GNU Free Documentation License from time to time.  Such new
3158
     versions will be similar in spirit to the present version, but may
3159
     differ in detail to address new problems or concerns.  See
3160
     `http://www.gnu.org/copyleft/'.
3161
 
3162
     Each version of the License is given a distinguishing version
3163
     number.  If the Document specifies that a particular numbered
3164
     version of this License "or any later version" applies to it, you
3165
     have the option of following the terms and conditions either of
3166
     that specified version or of any later version that has been
3167
     published (not as a draft) by the Free Software Foundation.  If
3168
     the Document does not specify a version number of this License,
3169
     you may choose any version ever published (not as a draft) by the
3170
     Free Software Foundation.
3171
 
3172
ADDENDUM: How to use this License for your documents
3173
====================================================
3174
 
3175
To use this License in a document you have written, include a copy of
3176
the License in the document and put the following copyright and license
3177
notices just after the title page:
3178
 
3179
       Copyright (C)  YEAR  YOUR NAME.
3180
       Permission is granted to copy, distribute and/or modify this document
3181
       under the terms of the GNU Free Documentation License, Version 1.2
3182
       or any later version published by the Free Software Foundation;
3183
       with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
3184
       Texts.  A copy of the license is included in the section entitled ``GNU
3185
       Free Documentation License''.
3186
 
3187
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
3188
replace the "with...Texts." line with this:
3189
 
3190
         with the Invariant Sections being LIST THEIR TITLES, with
3191
         the Front-Cover Texts being LIST, and with the Back-Cover Texts
3192
         being LIST.
3193
 
3194
If you have Invariant Sections without Cover Texts, or some other
3195
combination of the three, merge those two alternatives to suit the
3196
situation.
3197
 
3198
If your document contains nontrivial examples of program code, we
3199
recommend releasing these examples in parallel under your choice of
3200
free software license, such as the GNU General Public License, to
3201
permit their use in free software.
3202
 
3203

3204
File: or1ksim.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
3205
 
3206
Index
3207
*****
3208
 
3209
 
3210
* Menu:
3211
3212
* --cumulative:                          Profiling Utility.   (line  26)
3213
* --debug-config:                        Standalone Simulator.
3214
                                                              (line  48)
3215 82 jeremybenn
* --disable-all-tests:                   Configuring the Build.
3216
                                                              (line 128)
3217 19 jeremybenn
* --disable-arith-flag:                  Configuring the Build.
3218
                                                              (line  93)
3219
* --disable-debug:                       Configuring the Build.
3220
                                                              (line 121)
3221
* --disable-ethphy:                      Configuring the Build.
3222
                                                              (line  54)
3223
* --disable-ov-flag:                     Configuring the Build.
3224
                                                              (line  70)
3225
* --disable-profiling:                   Configuring the Build.
3226
                                                              (line  25)
3227
* --disable-range-stats:                 Configuring the Build.
3228
                                                              (line  64)
3229 82 jeremybenn
* --enable-all-tests:                    Configuring the Build.
3230
                                                              (line 127)
3231 19 jeremybenn
* --enable-arith-flag:                   Configuring the Build.
3232
                                                              (line  92)
3233
* --enable-debug:                        Configuring the Build.
3234
                                                              (line 120)
3235
* --enable-ethphy:                       Configuring the Build.
3236
                                                              (line  53)
3237
* --enable-execution:                    Configuring the Build.
3238
                                                              (line  32)
3239
* --enable-mprofile:                     Standalone Simulator.
3240
                                                              (line  77)
3241
* --enable-ov-flag:                      Configuring the Build.
3242
                                                              (line  69)
3243
* --enable-profile:                      Standalone Simulator.
3244
                                                              (line  74)
3245
* --enable-profiling:                    Configuring the Build.
3246
                                                              (line  24)
3247
* --enable-range-stats:                  Configuring the Build.
3248
                                                              (line  63)
3249
* --file:                                Standalone Simulator.
3250
                                                              (line  24)
3251
* --filename:                            Memory Profiling Utility.
3252
                                                              (line  51)
3253
* --generate:                            Profiling Utility.   (line  34)
3254
* --group:                               Memory Profiling Utility.
3255
                                                              (line  47)
3256
* --help:                                Standalone Simulator.
3257
                                                              (line  20)
3258
* --help (memory profiling utility):     Memory Profiling Utility.
3259
                                                              (line  22)
3260
* --help (profiling utility):            Profiling Utility.   (line  22)
3261
* --interactive:                         Standalone Simulator.
3262
                                                              (line  54)
3263
* --mode:                                Memory Profiling Utility.
3264
                                                              (line  26)
3265
* --nosrv:                               Standalone Simulator.
3266
                                                              (line  32)
3267
* --quiet:                               Profiling Utility.   (line  30)
3268
* --srv:                                 Standalone Simulator.
3269
                                                              (line  40)
3270
* --strict-npc:                          Standalone Simulator.
3271
                                                              (line  57)
3272
* --version:                             Standalone Simulator.
3273
                                                              (line  16)
3274
* --version (memory profiling utility):  Memory Profiling Utility.
3275
                                                              (line  17)
3276
* --version (profiling utility):         Profiling Utility.   (line  17)
3277
* -c:                                    Profiling Utility.   (line  26)
3278
* -d:                                    Standalone Simulator.
3279
                                                              (line  48)
3280
* -f <1>:                                Memory Profiling Utility.
3281
                                                              (line  51)
3282
* -f:                                    Standalone Simulator.
3283
                                                              (line  24)
3284
* -g <1>:                                Memory Profiling Utility.
3285
                                                              (line  47)
3286
* -g:                                    Profiling Utility.   (line  34)
3287
* -h:                                    Standalone Simulator.
3288
                                                              (line  20)
3289
* -h (memory profiling utility):         Memory Profiling Utility.
3290
                                                              (line  22)
3291
* -h (profiling utility):                Profiling Utility.   (line  22)
3292
* -i:                                    Standalone Simulator.
3293
                                                              (line  54)
3294
* -m:                                    Memory Profiling Utility.
3295
                                                              (line  26)
3296
* -q:                                    Profiling Utility.   (line  30)
3297
* -v:                                    Standalone Simulator.
3298
                                                              (line  16)
3299
* -v (memory profiling utility):         Memory Profiling Utility.
3300
                                                              (line  17)
3301
* -v (profiling utility):                Profiling Utility.   (line  17)
3302
* 0x00 UART VAPI sub-command (UART verification): Verification API.
3303
                                                              (line  49)
3304
* 0x01 UART VAPI sub-command (UART verification): Verification API.
3305
                                                              (line  55)
3306
* 0x02 UART VAPI sub-command (UART verification): Verification API.
3307
                                                              (line  59)
3308
* 0x03 UART VAPI sub-command (UART verification): Verification API.
3309
                                                              (line  62)
3310
* 0x04 UART VAPI sub-command (UART verification): Verification API.
3311
                                                              (line  66)
3312
* 16550 (UART configuration):            UART Configuration.  (line  73)
3313 82 jeremybenn
* all tests enabled:                     Configuring the Build.
3314
                                                              (line 128)
3315 19 jeremybenn
* Argtable2 debugging:                   Configuring the Build.
3316
                                                              (line 121)
3317
* ATA/ATAPI configuration:               Disc Interface Configuration.
3318
                                                              (line   6)
3319
* ATA/ATAPI device configuration:        Disc Interface Configuration.
3320
                                                              (line  88)
3321
* base_vapi_id (GPIO configuration - deprecated): GPIO Configuration.
3322
                                                              (line  32)
3323
* baseaddr (ATA/ATAPI configuration):    Disc Interface Configuration.
3324
                                                              (line  22)
3325
* baseaddr (DMA configuration):          DMA Configuration.   (line  24)
3326
* baseaddr (Ethernet configuration):     Ethernet Configuration.
3327
                                                              (line  22)
3328
* baseaddr (frame buffer configuration): Frame Buffer Configuration.
3329
                                                              (line  20)
3330
* baseaddr (generic peripheral configuration): Generic Peripheral Configuration.
3331
                                                              (line  22)
3332
* baseaddr (GPIO configuration):         GPIO Configuration.  (line  21)
3333
* baseaddr (keyboard configuration):     Keyboard Configuration.
3334
                                                              (line  36)
3335
* baseaddr (memory configuration):       Memory Configuration.
3336
                                                              (line  62)
3337
* baseaddr (memory controller configuration): Memory Controller Configuration.
3338 82 jeremybenn
                                                              (line  29)
3339 19 jeremybenn
* baseaddr (UART configuration):         UART Configuration.  (line  22)
3340
* baseaddr (VGA configuration):          Display Interface Configuration.
3341
                                                              (line  26)
3342
* blocksize (cache configuration):       Cache Configuration. (line  29)
3343
* BPB configuration:                     Branch Prediction Configuration.
3344
                                                              (line   6)
3345
* branch prediction configuration:       Branch Prediction Configuration.
3346
                                                              (line   6)
3347
* break (Interactive CLI):               Interactive Command Line.
3348
                                                              (line  57)
3349
* breakpoint list (Interactive CLI):     Interactive Command Line.
3350
                                                              (line  60)
3351
* breakpoint set/clear (Interactive CLI): Interactive Command Line.
3352
                                                              (line  57)
3353
* breaks (Interactive CLI):              Interactive Command Line.
3354
                                                              (line  60)
3355
* btic (branch prediction configuration): Branch Prediction Configuration.
3356
                                                              (line  19)
3357
* byte_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3358
                                                              (line  48)
3359
* cache configuration:                   Cache Configuration. (line   6)
3360
* calling_convention (CUC configuration): CUC Configuration.  (line  34)
3361
* ce (memory configuration):             Memory Configuration.
3362 82 jeremybenn
                                                              (line  92)
3363 19 jeremybenn
* cfgr (CPU configuration):              CPU Configuration.   (line  47)
3364
* channel (UART configuration):          UART Configuration.  (line  29)
3365
* clear breakpoint (Interactive CLI):    Interactive Command Line.
3366
                                                              (line  57)
3367 82 jeremybenn
* clkcycle (simulator configuration):    Simulator Behavior.  (line 103)
3368 19 jeremybenn
* cm (Interactive CLI):                  Interactive Command Line.
3369
                                                              (line  54)
3370
* command line for Or1ksim standalone use: Standalone Simulator.
3371
                                                              (line   6)
3372
* complex model:                         Configuring the Build.
3373
                                                              (line  32)
3374
* config:                                Global Data Structures.
3375
                                                              (line   7)
3376
* config.bpb:                            Global Data Structures.
3377
                                                              (line  37)
3378
* config.cpu:                            Global Data Structures.
3379
                                                              (line  22)
3380
* config.cuc:                            Global Data Structures.
3381
                                                              (line  18)
3382
* config.dc:                             Global Data Structures.
3383
                                                              (line  25)
3384
* config.debug:                          Global Data Structures.
3385
                                                              (line  40)
3386
* config.pic:                            Global Data Structures.
3387
                                                              (line  33)
3388
* config.pm:                             Global Data Structures.
3389
                                                              (line  29)
3390
* config.sim:                            Global Data Structures.
3391
                                                              (line  11)
3392
* config.vapi:                           Global Data Structures.
3393
                                                              (line  14)
3394
* configuration dynamic structure:       Global Data Structures.
3395
                                                              (line  49)
3396
* configuration file structure:          Configuration File Format.
3397
                                                              (line   6)
3398
* configuration global structure:        Global Data Structures.
3399
                                                              (line   7)
3400
* configuration info (Interactive CLI):  Interactive Command Line.
3401
                                                              (line 119)
3402
* configuration of generic peripherals:  Generic Peripheral Configuration.
3403
                                                              (line   6)
3404
* configuration parameter setting (Interactive CLI): Interactive Command Line.
3405
                                                              (line 146)
3406
* configuring branch prediction:         Branch Prediction Configuration.
3407
                                                              (line   6)
3408
* configuring data & instruction caches: Cache Configuration. (line   6)
3409
* configuring data & instruction MMUs:   Memory Management Configuration.
3410
                                                              (line   6)
3411
* configuring DMA:                       DMA Configuration.   (line   6)
3412
* configuring memory:                    Memory Configuration.
3413
                                                              (line   6)
3414
* configuring Or1ksim:                   Configuration.       (line   6)
3415
* configuring power management:          Power Management Configuration.
3416
                                                              (line   6)
3417
* configuring the ATA/ATAPI interfaces:  Disc Interface Configuration.
3418
                                                              (line   6)
3419
* configuring the behavior of Or1ksim:   Simulator Behavior.  (line   6)
3420
* configuring the CPU:                   CPU Configuration.   (line   6)
3421
* configuring the Custom Unit Compiler (CUC): CUC Configuration.
3422
                                                              (line   6)
3423
* configuring the debug unit and interface to external debuggers: Debug Interface Configuration.
3424
                                                              (line   6)
3425
* configuring the Ethernet interface:    Ethernet Configuration.
3426
                                                              (line   6)
3427
* configuring the frame buffer:          Frame Buffer Configuration.
3428
                                                              (line   6)
3429
* configuring the GPIO:                  GPIO Configuration.  (line   6)
3430
* configuring the interrupt controller:  Interrupt Configuration.
3431
                                                              (line   6)
3432
* configuring the keyboard interface:    Keyboard Configuration.
3433
                                                              (line   6)
3434
* configuring the memory controller:     Memory Controller Configuration.
3435
                                                              (line   6)
3436
* configuring the processor:             CPU Configuration.   (line   6)
3437
* configuring the PS2 interface:         Keyboard Configuration.
3438
                                                              (line   6)
3439
* configuring the UART:                  UART Configuration.  (line   6)
3440
* configuring the Verification API (VAPI): Verification API Configuration.
3441
                                                              (line   6)
3442
* configuring the VGA interface:         Display Interface Configuration.
3443
                                                              (line   6)
3444
* copying memory (Interactive CLI):      Interactive Command Line.
3445
                                                              (line  54)
3446
* CPU configuration:                     CPU Configuration.   (line   6)
3447
* CUC configuration:                     CUC Configuration.   (line   6)
3448
* Custom Unit Compiler (Interactive CLI): Interactive Command Line.
3449
                                                              (line 162)
3450
* Custom Unit Compiler Configuration:    CUC Configuration.   (line   6)
3451
* data cache configuration:              Cache Configuration. (line   6)
3452
* data MMU configuration:                Memory Management Configuration.
3453
                                                              (line   6)
3454
* DCGE (power management register):      Power Management Configuration.
3455
                                                              (line  21)
3456
* debug (Interactive CLI):               Interactive Command Line.
3457
                                                              (line 151)
3458
* debug (simulator configuration):       Simulator Behavior.  (line  13)
3459
* debug channel toggle (Interactive CLI): Interactive Command Line.
3460
                                                              (line 141)
3461
* debug interface configuration:         Debug Interface Configuration.
3462
                                                              (line   6)
3463
* debug mode toggle (Interactive CLI):   Interactive Command Line.
3464
                                                              (line 151)
3465
* debug unit configuration:              Debug Interface Configuration.
3466
                                                              (line   6)
3467
* Debug Unit verification (VAPI):        Verification API.    (line  34)
3468
* debugging enabled (Argtable2):         Configuring the Build.
3469
                                                              (line 121)
3470
* delayr (memory configuration):         Memory Configuration.
3471 82 jeremybenn
                                                              (line 110)
3472 19 jeremybenn
* delayw (memory configuration):         Memory Configuration.
3473 82 jeremybenn
                                                              (line 116)
3474 19 jeremybenn
* dependstats (CPU configuration):       CPU Configuration.   (line  84)
3475
* dev_id (ATA/ATAPI configuration):      Disc Interface Configuration.
3476
                                                              (line  36)
3477
* disassemble (Interactive CLI):         Interactive Command Line.
3478
                                                              (line  41)
3479
* disc interface configuration:          Disc Interface Configuration.
3480
                                                              (line   6)
3481
* disc interface device configuration:   Disc Interface Configuration.
3482
                                                              (line  88)
3483
* display interface configuration:       Display Interface Configuration.
3484
                                                              (line   6)
3485
* displaying memory (Interactive CLI):   Interactive Command Line.
3486
                                                              (line  31)
3487
* displaying registers (Interactive CLI): Interactive Command Line.
3488
                                                              (line  14)
3489
* dm (Interactive CLI):                  Interactive Command Line.
3490
                                                              (line  31)
3491
* dma (Ethernet configuration):          Ethernet Configuration.
3492
                                                              (line  33)
3493
* DMA configuration:                     DMA Configuration.   (line   6)
3494
* DMA verification (VAPI):               Verification API.    (line  73)
3495
* dma_mode0_td (ATA/ATAPI configuration): Disc Interface Configuration.
3496
                                                              (line  70)
3497
* dma_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3498
                                                              (line  71)
3499
* dma_mode0_tm (ATA/ATAPI configuration): Disc Interface Configuration.
3500
                                                              (line  69)
3501
* DME (power management register):       Power Management Configuration.
3502
                                                              (line  15)
3503
* DMMU configuration:                    Memory Management Configuration.
3504
                                                              (line   6)
3505
* doze mode (power management register): Power Management Configuration.
3506
                                                              (line  15)
3507
* dv (Interactive CLI):                  Interactive Command Line.
3508
                                                              (line 124)
3509
* dynamic clock gating (power management register): Power Management Configuration.
3510
                                                              (line  21)
3511
* dynamic model:                         Configuring the Build.
3512
                                                              (line  32)
3513
* dynamic ports, use of:                 Verification API Configuration.
3514
                                                              (line  23)
3515
* edge_trigger (interrupt controller):   Interrupt Configuration.
3516
                                                              (line  16)
3517
* enable_bursts (CUC configuration):     CUC Configuration.   (line  38)
3518
* enabled (ATA/ATAPI configuration):     Disc Interface Configuration.
3519
                                                              (line  18)
3520
* enabled (branch prediction configuration): Branch Prediction Configuration.
3521
                                                              (line  15)
3522
* enabled (cache configuration):         Cache Configuration. (line  11)
3523
* enabled (debug interface configuration): Debug Interface Configuration.
3524
                                                              (line  11)
3525
* enabled (DMA configuration):           DMA Configuration.   (line  20)
3526
* enabled (Ethernet configuration):      Ethernet Configuration.
3527
                                                              (line  18)
3528
* enabled (frame buffer configuration):  Frame Buffer Configuration.
3529
                                                              (line  16)
3530
* enabled (generic peripheral configuration): Generic Peripheral Configuration.
3531
                                                              (line  18)
3532
* enabled (GPIO configuration):          GPIO Configuration.  (line  17)
3533
* enabled (interrupt controller):        Interrupt Configuration.
3534
                                                              (line  12)
3535
* enabled (keyboard configuration):      Keyboard Configuration.
3536
                                                              (line  32)
3537
* enabled (memory controller configuration): Memory Controller Configuration.
3538 82 jeremybenn
                                                              (line  18)
3539 19 jeremybenn
* enabled (MMU configuration):           Memory Management Configuration.
3540
                                                              (line  12)
3541
* enabled (power management configuration): Power Management Configuration.
3542
                                                              (line  35)
3543
* enabled (UART configuration):          UART Configuration.  (line  18)
3544
* enabled (verification API configuration): Verification API Configuration.
3545
                                                              (line  15)
3546
* enabled (VGA configuration):           Display Interface Configuration.
3547
                                                              (line  22)
3548
* enabling Ethernet via socket:          Configuring the Build.
3549
                                                              (line  54)
3550
* entrysize (MMU configuration):         Memory Management Configuration.
3551
                                                              (line  32)
3552
* ETH_VAPI_CTRL (Ethernet verification): Verification API.    (line  86)
3553
* ETH_VAPI_DATA (Ethernet verification): Verification API.    (line  84)
3554
* Ethernet configuration:                Ethernet Configuration.
3555
                                                              (line   6)
3556
* Ethernet verification (VAPI):          Verification API.    (line  78)
3557
* Ethernet via socket, enabling:         Configuring the Build.
3558
                                                              (line  54)
3559 82 jeremybenn
* exe_log (simulator configuration):     Simulator Behavior.  (line  49)
3560
* exe_log_end (simulator configuration): Simulator Behavior.  (line  89)
3561
* exe_log_file (simulator configuration): Simulator Behavior. (line  97)
3562 19 jeremybenn
* exe_log_fn (simulator configuration - deprecated): Simulator Behavior.
3563 82 jeremybenn
                                                              (line  97)
3564 19 jeremybenn
* exe_log_marker (simulator configuration): Simulator Behavior.
3565 82 jeremybenn
                                                              (line  93)
3566 19 jeremybenn
* exe_log_start (simulator configuration): Simulator Behavior.
3567 82 jeremybenn
                                                              (line  86)
3568
* exe_log_type (simulator configuration): Simulator Behavior. (line  55)
3569 19 jeremybenn
* exe_log_type=default (simulator configuration): Simulator Behavior.
3570 82 jeremybenn
                                                              (line  58)
3571 19 jeremybenn
* exe_log_type=hardware (simulator configuration): Simulator Behavior.
3572 82 jeremybenn
                                                              (line  62)
3573 19 jeremybenn
* exe_log_type=simple (simulator configuration): Simulator Behavior.
3574 82 jeremybenn
                                                              (line  69)
3575 19 jeremybenn
* exe_log_type=software (simulator configuration): Simulator Behavior.
3576 82 jeremybenn
                                                              (line  74)
3577 19 jeremybenn
* executing code (Interactive CLI):      Interactive Command Line.
3578
                                                              (line  23)
3579
* execution history (Interactive CLI):   Interactive Command Line.
3580
                                                              (line  67)
3581
* file (ATA/ATAPI device configuration): Disc Interface Configuration.
3582
                                                              (line 104)
3583
* file (keyboard configuration):         Keyboard Configuration.
3584
                                                              (line  51)
3585
* filename (frame buffer configuration - deprecated): Frame Buffer Configuration.
3586 82 jeremybenn
                                                              (line  36)
3587 19 jeremybenn
* filename (VGA configuration - deprecated): Display Interface Configuration.
3588
                                                              (line  47)
3589
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
3590
                                                              (line 117)
3591
* flag setting by instructions:          Configuring the Build.
3592
                                                              (line  93)
3593
* frame buffer configuration:            Frame Buffer Configuration.
3594
                                                              (line   6)
3595
* gdb_enabled (debug interface configuration): Debug Interface Configuration.
3596
                                                              (line  47)
3597
* generic peripheral configuration:      Generic Peripheral Configuration.
3598
                                                              (line   6)
3599
* GPIO configuration:                    GPIO Configuration.  (line   6)
3600
* GPIO verification (VAPI):              Verification API.    (line  88)
3601
* GPIO_VAPI_AUX (GPIO verification):     Verification API.    (line 100)
3602
* GPIO_VAPI_CLOCK (GPIO verification):   Verification API.    (line 103)
3603
* GPIO_VAPI_CTRL (GPIO verification):    Verification API.    (line 119)
3604
* GPIO_VAPI_DATA (GPIO verification):    Verification API.    (line  97)
3605
* GPIO_VAPI_INTE (GPIO verification):    Verification API.    (line 110)
3606
* GPIO_VAPI_PTRIG (GPIO verification):   Verification API.    (line 113)
3607
* GPIO_VAPI_RGPIO (GPIO verification):   Verification API.    (line 107)
3608
* hazards (CPU configuration):           CPU Configuration.   (line  69)
3609
* heads (ATA/ATAPI device configuration): Disc Interface Configuration.
3610
                                                              (line 121)
3611
* help (Interactive CLI):                Interactive Command Line.
3612
                                                              (line 170)
3613
* hexadecimal memory dump (Interactive CLI): Interactive Command Line.
3614
                                                              (line 133)
3615
* hide_device_id (verification API configuration): Verification API Configuration.
3616
                                                              (line  36)
3617
* hist (Interactive CLI):                Interactive Command Line.
3618
                                                              (line  67)
3619 82 jeremybenn
* history (simulator configuration):     Simulator Behavior.  (line  40)
3620 19 jeremybenn
* history of execution (Interactive CLI): Interactive Command Line.
3621
                                                              (line  67)
3622
* hitdelay (branch prediction configuration): Branch Prediction Configuration.
3623
                                                              (line  33)
3624
* hitdelay (instruction cache configuration): Cache Configuration.
3625
                                                              (line  38)
3626
* hitdelay (MMU configuration):          Memory Management Configuration.
3627
                                                              (line  51)
3628
* hw_enabled (generic peripheral configuration): Generic Peripheral Configuration.
3629
                                                              (line  49)
3630
* IMMU configuration:                    Memory Management Configuration.
3631
                                                              (line   6)
3632
* index (memory controller configuration): Memory Controller Configuration.
3633 82 jeremybenn
                                                              (line  51)
3634 19 jeremybenn
* info (Interactive CLI):                Interactive Command Line.
3635
                                                              (line 119)
3636
* installing Or1ksim:                    Installation.        (line   6)
3637
* instruction cache configuration:       Cache Configuration. (line   6)
3638
* instruction MMU configuration:         Memory Management Configuration.
3639
                                                              (line   6)
3640
* instruction profiling for Or1ksim:     Profiling Utility.   (line   6)
3641
* instruction profiling utility (Interactive CLI): Interactive Command Line.
3642
                                                              (line 178)
3643
* internal debugging:                    Internal Debugging.  (line   6)
3644
* interrupt controller configuration:    Interrupt Configuration.
3645
                                                              (line   6)
3646
* irq (ATA/ATAPI configuration):         Disc Interface Configuration.
3647
                                                              (line  32)
3648
* irq (DMA configuration):               DMA Configuration.   (line  34)
3649
* irq (GPIO configuration):              GPIO Configuration.  (line  29)
3650
* irq (keyboard configuration):          Keyboard Configuration.
3651
                                                              (line  47)
3652
* irq (UART configuration):              UART Configuration.  (line  70)
3653
* irq (VGA configuration):               Display Interface Configuration.
3654
                                                              (line  37)
3655
* jitter (UART configuration):           UART Configuration.  (line  78)
3656
* keyboard configuration:                Keyboard Configuration.
3657
                                                              (line   6)
3658
* library version of Or1ksim:            Simulator Library.   (line   6)
3659
* license for Or1ksim:                   GNU Free Documentation License.
3660
                                                              (line   6)
3661
* list breakpoints (Interactive CLI):    Interactive Command Line.
3662
                                                              (line  60)
3663
* load_hitdelay (data cache configuration): Cache Configuration.
3664
                                                              (line  46)
3665
* load_missdelay (data cache configuration): Cache Configuration.
3666
                                                              (line  50)
3667
* log (memory configuration):            Memory Configuration.
3668 82 jeremybenn
                                                              (line 122)
3669 19 jeremybenn
* log_enabled (verification API configuration): Verification API Configuration.
3670
                                                              (line  28)
3671 82 jeremybenn
* long:                                  Simulator Library.   (line  74)
3672 19 jeremybenn
* mc (memory configuration):             Memory Configuration.
3673 82 jeremybenn
                                                              (line 100)
3674 19 jeremybenn
* memory configuration:                  Memory Configuration.
3675
                                                              (line   6)
3676
* memory controller configuration:       Memory Controller Configuration.
3677
                                                              (line   6)
3678
* memory copying (Interactive CLI):      Interactive Command Line.
3679
                                                              (line  54)
3680
* memory display (Interactive CLI):      Interactive Command Line.
3681
                                                              (line  31)
3682
* memory dump, hexadecimal (Interactive CLI): Interactive Command Line.
3683
                                                              (line 133)
3684
* memory dump, Verilog (Interactive CLI): Interactive Command Line.
3685
                                                              (line 124)
3686
* memory patching (Interactive CLI):     Interactive Command Line.
3687
                                                              (line  48)
3688
* memory profiling end address:          Memory Profiling Utility.
3689
                                                              (line  56)
3690
* memory profiling start address:        Memory Profiling Utility.
3691
                                                              (line  56)
3692
* memory profiling utility (Interactive CLI): Interactive Command Line.
3693
                                                              (line 173)
3694
* memory profiling version of Or1ksim:   Memory Profiling Utility.
3695
                                                              (line   6)
3696
* memory_order (CUC configuration):      CUC Configuration.   (line  15)
3697
* memory_order=exact (CUC configuration): CUC Configuration.  (line  27)
3698
* memory_order=none (CUC configuration): CUC Configuration.   (line  18)
3699
* memory_order=strong (CUC configuration): CUC Configuration. (line  25)
3700
* memory_order=weak (CUC configuration): CUC Configuration.   (line  21)
3701
* missdelay (branch prediction configuration): Branch Prediction Configuration.
3702
                                                              (line  37)
3703
* missdelay (instruction cache configuration): Cache Configuration.
3704
                                                              (line  42)
3705
* missdelay (MMU configuration):         Memory Management Configuration.
3706
                                                              (line  55)
3707
* MMU configuration:                     Memory Management Configuration.
3708
                                                              (line   6)
3709 82 jeremybenn
* mprof_file (simulator configuration):  Simulator Behavior.  (line  34)
3710 19 jeremybenn
* mprof_fn (simulator configuration - deprecated): Simulator Behavior.
3711 82 jeremybenn
                                                              (line  34)
3712 19 jeremybenn
* mprofile (Interactive CLI):            Interactive Command Line.
3713
                                                              (line 173)
3714 82 jeremybenn
* mprofile (simulator configuration):    Simulator Behavior.  (line  29)
3715 19 jeremybenn
* mwdma (ATA/ATAPI device configuration): Disc Interface Configuration.
3716
                                                              (line 128)
3717
* name (generic peripheral configuration): Generic Peripheral Configuration.
3718
                                                              (line  42)
3719
* name (memory configuration):           Memory Configuration.
3720 82 jeremybenn
                                                              (line  83)
3721 19 jeremybenn
* no_multicycle (CUC configuration):     CUC Configuration.   (line  42)
3722
* nsets (cache configuration):           Cache Configuration. (line  15)
3723
* nsets (MMU configuration):             Memory Management Configuration.
3724
                                                              (line  16)
3725
* nways (cache configuration):           Cache Configuration. (line  22)
3726
* nways (MMU configuration):             Memory Management Configuration.
3727
                                                              (line  22)
3728 82 jeremybenn
* or1ksim_get_time_period:               Simulator Library.   (line  64)
3729 19 jeremybenn
* or1ksim_init:                          Simulator Library.   (line  18)
3730 82 jeremybenn
* or1ksim_interrupt:                     Simulator Library.   (line  79)
3731
* or1ksim_interrupt_clear:               Simulator Library.   (line  97)
3732
* or1ksim_interrupt_set:                 Simulator Library.   (line  88)
3733
* or1ksim_is_le:                         Simulator Library.   (line  69)
3734
* or1ksim_reset_duration:                Simulator Library.   (line  49)
3735
* or1ksim_run:                           Simulator Library.   (line  44)
3736
* or1ksim_set_time_point:                Simulator Library.   (line  60)
3737 19 jeremybenn
* output rediretion:                     Concepts.            (line   7)
3738
* overflow flag setting by instructions: Configuring the Build.
3739
                                                              (line  70)
3740
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
3741
                                                              (line 113)
3742
* pagesize (MMU configuration):          Memory Management Configuration.
3743
                                                              (line  27)
3744
* patching memory (Interactive CLI):     Interactive Command Line.
3745
                                                              (line  48)
3746
* patching registers (Interactive CLI):  Interactive Command Line.
3747
                                                              (line  28)
3748
* patching the program counter (Interactive CLI): Interactive Command Line.
3749
                                                              (line  51)
3750
* pattern (memory configuration):        Memory Configuration.
3751
                                                              (line  50)
3752
* pc (Interactive CLI):                  Interactive Command Line.
3753
                                                              (line  51)
3754
* PIC configuration:                     Interrupt Configuration.
3755
                                                              (line   6)
3756
* pio (ATA/ATAPI device configuration):  Disc Interface Configuration.
3757
                                                              (line 132)
3758
* pio_mode0_t1 (ATA/ATAPI configuration): Disc Interface Configuration.
3759
                                                              (line  51)
3760
* pio_mode0_t2 (ATA/ATAPI configuration): Disc Interface Configuration.
3761
                                                              (line  52)
3762
* pio_mode0_t4 (ATA/ATAPI configuration): Disc Interface Configuration.
3763
                                                              (line  53)
3764
* pio_mode0_teoc (ATA/ATAPI configuration): Disc Interface Configuration.
3765
                                                              (line  54)
3766
* pm (Interactive CLI):                  Interactive Command Line.
3767
                                                              (line  48)
3768
* PMR - DGCE:                            Power Management Configuration.
3769
                                                              (line  21)
3770
* PMR - DME:                             Power Management Configuration.
3771
                                                              (line  15)
3772
* PMR - SDF:                             Power Management Configuration.
3773
                                                              (line  12)
3774
* PMR - SME:                             Power Management Configuration.
3775
                                                              (line  16)
3776
* PMR - SUME:                            Power Management Configuration.
3777
                                                              (line  24)
3778
* PMU configuration:                     Power Management Configuration.
3779
                                                              (line   6)
3780
* poc (memory controller configuration): Memory Controller Configuration.
3781 82 jeremybenn
                                                              (line  38)
3782 19 jeremybenn
* port range for TCP/IP:                 Verification API Configuration.
3783
                                                              (line  23)
3784
* power management configuration:        Power Management Configuration.
3785
                                                              (line   6)
3786
* power management register, DGCE:       Power Management Configuration.
3787
                                                              (line  21)
3788
* power management register, DME:        Power Management Configuration.
3789
                                                              (line  15)
3790
* power management register, SDF:        Power Management Configuration.
3791
                                                              (line  12)
3792
* power management register, SME:        Power Management Configuration.
3793
                                                              (line  16)
3794
* power management register, SUME:       Power Management Configuration.
3795
                                                              (line  24)
3796
* pr (Interactive CLI):                  Interactive Command Line.
3797
                                                              (line  28)
3798
* private ports, use of:                 Verification API Configuration.
3799
                                                              (line  23)
3800
* processor configuration:               CPU Configuration.   (line   6)
3801
* processor stall (Interactive CLI):     Interactive Command Line.
3802
                                                              (line  72)
3803
* processor unstall (Interactive CLI):   Interactive Command Line.
3804
                                                              (line  78)
3805
* prof_file (simulator configuration):   Simulator Behavior.  (line  23)
3806
* prof_fn (simulator configuration - deprecated): Simulator Behavior.
3807
                                                              (line  23)
3808
* profile (simulator configuration):     Simulator Behavior.  (line  19)
3809
* profiling for Or1ksim:                 Profiling Utility.   (line   6)
3810
* profiling utility (Interactive CLI):   Interactive Command Line.
3811
                                                              (line 178)
3812
* program counter patching (Interactive CLI): Interactive Command Line.
3813
                                                              (line  51)
3814
* programmable interrupt controller configuration: Interrupt Configuration.
3815
                                                              (line   6)
3816
* PS2 configuration:                     Keyboard Configuration.
3817
                                                              (line   6)
3818
* q (Interactive CLI):                   Interactive Command Line.
3819
                                                              (line  11)
3820
* quitting (Interactive CLI):            Interactive Command Line.
3821
                                                              (line  11)
3822
* r (Interactive CLI):                   Interactive Command Line.
3823
                                                              (line  14)
3824
* random_seed (memory configuration):    Memory Configuration.
3825
                                                              (line  40)
3826
* refresh_rate (frame buffer configuration): Frame Buffer Configuration.
3827 82 jeremybenn
                                                              (line  30)
3828 19 jeremybenn
* refresh_rate (VGA configuration):      Display Interface Configuration.
3829
                                                              (line  41)
3830
* reg_sim_reset:                         Concepts.            (line  13)
3831
* register display (Interactive CLI):    Interactive Command Line.
3832
                                                              (line  14)
3833
* register over time statistics:         Configuring the Build.
3834
                                                              (line  64)
3835
* register patching (Interactive CLI):   Interactive Command Line.
3836
                                                              (line  28)
3837
* Remote Serial Protocol:                Debug Interface Configuration.
3838
                                                              (line  20)
3839
* reset (Interactive CLI):               Interactive Command Line.
3840
                                                              (line  63)
3841
* reset hooks:                           Concepts.            (line  13)
3842
* reset the simulator (Interactive CLI): Interactive Command Line.
3843
                                                              (line  63)
3844
* rev (ATA/ATAPI configuration):         Disc Interface Configuration.
3845
                                                              (line  44)
3846
* rev (CPU configuration):               CPU Configuration.   (line  15)
3847
* rsp_enabled (debug interface configuration): Debug Interface Configuration.
3848
                                                              (line  20)
3849
* rsp_port (debug interface configuration): Debug Interface Configuration.
3850
                                                              (line  36)
3851
* rtx_type (Ethernet configuration):     Ethernet Configuration.
3852
                                                              (line  46)
3853
* run (Interactive CLI):                 Interactive Command Line.
3854
                                                              (line  23)
3855
* running code (Interactive CLI):        Interactive Command Line.
3856
                                                              (line  23)
3857
* running Or1ksim:                       Usage.               (line   6)
3858
* runtime:                               Global Data Structures.
3859
                                                              (line  58)
3860
* runtime global structure:              Global Data Structures.
3861
                                                              (line  58)
3862
* runtime.cpu:                           Global Data Structures.
3863
                                                              (line  62)
3864
* runtime.cpu.fout:                      Concepts.            (line   7)
3865
* runtime.cuc:                           Global Data Structures.
3866
                                                              (line  62)
3867
* runtime.vapi:                          Global Data Structures.
3868
                                                              (line  62)
3869
* rx_channel (Ethernet configuration):   Ethernet Configuration.
3870
                                                              (line  59)
3871
* rxfile (Ethernet configuration):       Ethernet Configuration.
3872
                                                              (line  68)
3873
* sbp_bf_fwd (branch prediction configuration): Branch Prediction Configuration.
3874
                                                              (line  23)
3875
* sbp_bnf_fwd (branch prediction configuration): Branch Prediction Configuration.
3876
                                                              (line  28)
3877
* sbuf_len (CPU configuration):          CPU Configuration.   (line  96)
3878
* SDF (power management register):       Power Management Configuration.
3879
                                                              (line  12)
3880
* section ata:                           Disc Interface Configuration.
3881
                                                              (line   6)
3882
* section bpb:                           Branch Prediction Configuration.
3883
                                                              (line   6)
3884
* section cpio:                          GPIO Configuration.  (line   6)
3885
* section cpu:                           CPU Configuration.   (line   6)
3886
* section cuc:                           CUC Configuration.   (line   6)
3887
* section dc:                            Cache Configuration. (line   6)
3888
* section debug:                         Debug Interface Configuration.
3889
                                                              (line   6)
3890
* section dma:                           DMA Configuration.   (line   6)
3891
* section dmmu:                          Memory Management Configuration.
3892
                                                              (line   6)
3893
* section ethernet:                      Ethernet Configuration.
3894
                                                              (line   6)
3895
* section fb:                            Frame Buffer Configuration.
3896
                                                              (line   6)
3897
* section generic:                       Generic Peripheral Configuration.
3898
                                                              (line   6)
3899
* section ic:                            Cache Configuration. (line   6)
3900
* section immu:                          Memory Management Configuration.
3901
                                                              (line   6)
3902
* section kb:                            Keyboard Configuration.
3903
                                                              (line   6)
3904
* section mc:                            Memory Controller Configuration.
3905
                                                              (line   6)
3906
* section memory:                        Memory Configuration.
3907
                                                              (line   6)
3908
* section pic:                           Interrupt Configuration.
3909
                                                              (line   6)
3910
* section pmu:                           Power Management Configuration.
3911
                                                              (line   6)
3912
* section sim:                           Simulator Behavior.  (line   6)
3913
* section uart:                          UART Configuration.  (line   6)
3914
* section vapi:                          Verification API Configuration.
3915
                                                              (line   6)
3916
* section vga:                           Display Interface Configuration.
3917
                                                              (line   6)
3918
* sections:                              Global Data Structures.
3919
                                                              (line  49)
3920
* sectors (ATA/ATAPI device configuration): Disc Interface Configuration.
3921
                                                              (line 125)
3922
* server_port (debug interface configuration): Debug Interface Configuration.
3923
                                                              (line  69)
3924
* server_port (verification API configuration): Verification API Configuration.
3925
                                                              (line  19)
3926
* set (Interactive CLI):                 Interactive Command Line.
3927
                                                              (line 146)
3928
* set breakpoint (Interactive CLI):      Interactive Command Line.
3929
                                                              (line  57)
3930
* setdbch (Interactive CLI):             Interactive Command Line.
3931
                                                              (line 141)
3932
* simple model:                          Configuring the Build.
3933
                                                              (line  32)
3934
* simulator configuration:               Simulator Behavior.  (line   6)
3935
* simulator configuration info (Interactive CLI): Interactive Command Line.
3936
                                                              (line 119)
3937
* simulator reset (Interactive CLI):     Interactive Command Line.
3938
                                                              (line  63)
3939
* simulator statistics (Interactive CLI): Interactive Command Line.
3940
                                                              (line  83)
3941
* size (ATA/ATAPI device configuration): Disc Interface Configuration.
3942
                                                              (line 109)
3943
* size (generic peripheral configuration): Generic Peripheral Configuration.
3944
                                                              (line  30)
3945
* size (memory configuration):           Memory Configuration.
3946
                                                              (line  67)
3947
* sleep mode (power management register): Power Management Configuration.
3948
                                                              (line  16)
3949
* slow down factor (power management register): Power Management Configuration.
3950
                                                              (line  12)
3951
* SME (power management register):       Power Management Configuration.
3952
                                                              (line  16)
3953
* sockif (Ethernet configuration):       Ethernet Configuration.
3954
                                                              (line  83)
3955
* sr (CPU configuration):                CPU Configuration.   (line  53)
3956
* stall (Interactive CLI):               Interactive Command Line.
3957
                                                              (line  72)
3958
* stall the processor (Interactive CLI): Interactive Command Line.
3959
                                                              (line  72)
3960
* statistics, register over time:        Configuring the Build.
3961
                                                              (line  64)
3962
* statistics, simulation (Interactive CLI): Interactive Command Line.
3963
                                                              (line  83)
3964
* stats (Interactive CLI):               Interactive Command Line.
3965
                                                              (line  83)
3966
* stepping code (Interactive CLI):       Interactive Command Line.
3967
                                                              (line  19)
3968
* store_hitdelay (data cache configuration): Cache Configuration.
3969
                                                              (line  54)
3970
* store_missdelay (data cache configuration): Cache Configuration.
3971
                                                              (line  58)
3972
* SUME (power management register):      Power Management Configuration.
3973
                                                              (line  24)
3974
* superscalar (CPU configuration):       CPU Configuration.   (line  58)
3975
* suspend mode (power management register): Power Management Configuration.
3976
                                                              (line  24)
3977
* t (Interactive CLI):                   Interactive Command Line.
3978
                                                              (line  19)
3979
* TCP/IP port range:                     Verification API Configuration.
3980
                                                              (line  23)
3981
* TCP/IP port range for or1ksim service: Debug Interface Configuration.
3982
                                                              (line  74)
3983
* TCP/IP port range for or1ksim-rsp service: Debug Interface Configuration.
3984
                                                              (line  41)
3985 82 jeremybenn
* tests, all enabled.:                   Configuring the Build.
3986
                                                              (line 128)
3987 19 jeremybenn
* timings_file (CUC configuration):      CUC Configuration.   (line  46)
3988
* timings_fn (CUC configuration - deprecated): CUC Configuration.
3989
                                                              (line  46)
3990
* toggle breakpoint (Interactive CLI):   Interactive Command Line.
3991
                                                              (line  57)
3992
* toggle debug channels (Interactive CLI): Interactive Command Line.
3993
                                                              (line 141)
3994
* toggle debug mode (Interactive CLI):   Interactive Command Line.
3995
                                                              (line 151)
3996
* tx_channel (Ethernet configuration):   Ethernet Configuration.
3997
                                                              (line  60)
3998
* txfile (Ethernet configuration):       Ethernet Configuration.
3999
                                                              (line  69)
4000
* txfile (frame buffer configuration):   Frame Buffer Configuration.
4001 82 jeremybenn
                                                              (line  36)
4002 19 jeremybenn
* txfile (VGA configuration):            Display Interface Configuration.
4003
                                                              (line  47)
4004
* type (ATA/ATAPI device configuration): Disc Interface Configuration.
4005
                                                              (line  99)
4006
* type (memory configuration):           Memory Configuration.
4007
                                                              (line  11)
4008
* type=pattern (memory configuration):   Memory Configuration.
4009
                                                              (line  21)
4010
* type=random (memory configuration):    Memory Configuration.
4011
                                                              (line  15)
4012
* type=unknown (memory configuration):   Memory Configuration.
4013
                                                              (line  25)
4014
* type=zero (memory configuration):      Memory Configuration.
4015
                                                              (line  29)
4016
* UART configuration:                    UART Configuration.  (line   6)
4017
* UART I/O from/to a physical serial port: UART Configuration.
4018
                                                              (line  62)
4019
* UART I/O from/to an xterm:             UART Configuration.  (line  38)
4020
* UART I/O from/to files:                UART Configuration.  (line  33)
4021
* UART I/O from/to open file descriptors: UART Configuration. (line  58)
4022
* UART I/O from/to TCP/IP:               UART Configuration.  (line  45)
4023
* UART verification (VAPI):              Verification API.    (line  41)
4024
* unstall (Interactive CLI):             Interactive Command Line.
4025
                                                              (line  78)
4026
* unstall the processor (Interactive CLI): Interactive Command Line.
4027
                                                              (line  78)
4028
* upr (CPU configuration):               CPU Configuration.   (line  21)
4029
* ustates (cache configuration):         Cache Configuration. (line  33)
4030
* ustates (MMU configuration):           Memory Management Configuration.
4031
                                                              (line  41)
4032
* VAPI configuration:                    Verification API Configuration.
4033
                                                              (line   6)
4034
* VAPI for Debug Unit:                   Verification API.    (line  34)
4035
* VAPI for DMA:                          Verification API.    (line  73)
4036
* VAPI for Ethernet:                     Verification API.    (line  78)
4037
* VAPI for GPIO:                         Verification API.    (line  88)
4038
* VAPI for UART:                         Verification API.    (line  41)
4039
* vapi_id (debug interface configuration): Debug Interface Configuration.
4040
                                                              (line  80)
4041
* vapi_id (DMA configuration) <1>:       Ethernet Configuration.
4042
                                                              (line  88)
4043
* vapi_id (DMA configuration):           DMA Configuration.   (line  38)
4044
* vapi_id (GPIO configuration):          GPIO Configuration.  (line  32)
4045
* vapi_id (UART configuration):          UART Configuration.  (line  85)
4046
* vapi_log_file (verification API configuration): Verification API Configuration.
4047
                                                              (line  41)
4048
* vapi_log_fn (verification API configuration - deprecated): Verification API Configuration.
4049
                                                              (line  41)
4050
* ver (CPU configuration):               CPU Configuration.   (line  15)
4051
* verbose (simulator configuration):     Simulator Behavior.  (line  10)
4052
* Verification API configuration:        Verification API Configuration.
4053
                                                              (line   6)
4054
* Verilog memory dump (Interactive CLI): Interactive Command Line.
4055
                                                              (line 124)
4056
* VGA configuration:                     Display Interface Configuration.
4057
 
4058
 
4059
                                                              (line  50)
4060
4061
4062

4063
Tag Table:
4064
Node: Top814
4065
Node: Installation1224
4066
Node: Preparation1471
4067 82 jeremybenn
Node: Configuring the Build1772
4068
Node: Build and Install7257
4069
Node: Known Issues8103
4070
Node: Usage10249
4071
Node: Standalone Simulator10463
4072
Node: Profiling Utility13366
4073
Node: Memory Profiling Utility14276
4074
Node: Simulator Library15641
4075
Node: Configuration21126
4076
Node: Configuration File Format21735
4077
Node: Configuration File Preprocessing22027
4078
Node: Configuration File Syntax22398
4079
Node: Simulator Configuration25183
4080
Node: Simulator Behavior25474
4081
Node: Verification API Configuration29518
4082
Node: CUC Configuration31458
4083
Node: Core OpenRISC Configuration33375
4084
Node: CPU Configuration33877
4085
Node: Memory Configuration37682
4086
Node: Memory Management Configuration42995
4087
Node: Cache Configuration45372
4088
Node: Interrupt Configuration47758
4089
Node: Power Management Configuration48494
4090
Node: Branch Prediction Configuration49771
4091
Node: Debug Interface Configuration51131
4092
Node: Peripheral Configuration55351
4093
Node: Memory Controller Configuration55977
4094
Node: UART Configuration58582
4095
Node: DMA Configuration62101
4096
Node: Ethernet Configuration63968
4097
Node: GPIO Configuration67946
4098
Node: Display Interface Configuration69579
4099
Node: Frame Buffer Configuration71888
4100
Node: Keyboard Configuration73752
4101
Node: Disc Interface Configuration75990
4102
Node: Generic Peripheral Configuration80933
4103
Node: Interactive Command Line83228
4104
Node: Verification API90202
4105
Node: Code Internals94632
4106
Node: Coding Conventions95192
4107
Node: Global Data Structures99619
4108
Node: Concepts102276
4109
Ref: Output Redirection102421
4110
Node: Internal Debugging102960
4111
Node: GNU Free Documentation License103457

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