OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.4.0/] [testsuite/] [test-code-or1k/] [inst-set-test/] [is-add-test.S] - Blame information for rev 116

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 112 jeremybenn 
/* is-add-test.S. l.add, l.addc, l.addi and l.addic instruction test of Or1ksim
2 
 *
3 
 * Copyright (C) 1999-2006 OpenCores
4 
 * Copyright (C) 2010 Embecosm Limited
5 
 *
6 
 * Contributors various OpenCores participants
7 
 * Contributor Jeremy Bennett
8 
 *
9 
 * This file is part of OpenRISC 1000 Architectural Simulator.
10 
 *
11 
 * This program is free software; you can redistribute it and/or modify it
12 
 * under the terms of the GNU General Public License as published by the Free
13 
 * Software Foundation; either version 3 of the License, or (at your option)
14 
 * any later version.
15 
 *
16 
 * This program is distributed in the hope that it will be useful, but WITHOUT
17 
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19 
 * more details.
20 
 *
21 
 * You should have received a copy of the GNU General Public License along
22 
 * with this program.  If not, see .
23 
 */
24 
 
25 
/* ----------------------------------------------------------------------------
26 116 jeremybenn 
 * Coding conventions are described in inst-set-test.S
27 112 jeremybenn 
 * ------------------------------------------------------------------------- */
28 
 
29 
/* ----------------------------------------------------------------------------
30 
 * Test coverage
31 
 *
32 
 * The l.add, l.addc, l.addi and l.addic instructions should set the carry and
33 
 * overflow flags.
34 
 *
35 
 * In addition the l.addc and l.addic instructions should add in the carry
36 
 * bit.
37 
 *
38 115 jeremybenn 
 * Problems in this area were reported in Bugs 1771 and 1776. Having fixed the
39 
 * problem, this is (in good software engineering style), a  regression test
40 
 * to go with the fix.
41 112 jeremybenn 
 *
42 
 * This is not a comprehensive test of any instruction (yet).
43 
 *
44 
 * Of course what is really needed is a comprehensive instruction test...
45 
 * ------------------------------------------------------------------------- */
46 
 
47 
 
48 
#include "inst-set-test.h"
49 
 
50 114 jeremybenn 
/* ----------------------------------------------------------------------------
51 
 * A macro to carry out a test of addition in registers
52 
 *
53 
 *
54 
 * Arguments
55 
 *   set_flags: Flags to set in the SR
56 
 *   clr_flags: Flags to clear in the SR
57 
 *   opc:       The opcode
58 
 *   op1:       First operand value
59 
 *   op2:       Second operand value
60 
 *   res:       Expected result
61 
 *   str:       Output string
62 
 *   cy:        Expected carry flag
63 
 *   ov:        Expected overflow flag
64 
 * ------------------------------------------------------------------------- */
65 
#define TEST_ADD(set_flags, clr_flags, opc, op1, op2, res, str, cy, ov)  \
66 
        l.mfspr r3,r0,SPR_SR                                            ;\
67 
        LOAD_CONST (r2, set_flags)      /* Set flags */                 ;\
68 
        l.or    r3,r3,r2                                                ;\
69 
        LOAD_CONST (r2, ~clr_flags)     /* Clear flags */               ;\
70 
        l.and   r3,r3,r2                                                ;\
71 
        l.mtspr r0,r3,SPR_SR                                            ;\
72 
                                                                        ;\
73 
        LOAD_CONST (r5,op1)             /* Load numbers to add */       ;\
74 
        LOAD_CONST (r6,op2)                                             ;\
75 
        opc     r4,r5,r6                                                ;\
76 
        l.mfspr r2,r0,SPR_SR            /* So we can examine flags */   ;\
77 
        PUSH (r2)                                                       ;\
78 
        CHECK_RES (str, r4, res)                                        ;\
79 
        POP(r2)                         /* Retrieve SR */               ;\
80 
        PUSH(r2)                                                        ;\
81 
        LOAD_CONST (r4, SPR_SR_CY)      /* The carry bit */             ;\
82 
        l.and   r2,r2,r4                                                ;\
83 
        l.sfeq  r2,r4                                                   ;\
84 
        CHECK_FLAG ("- carry flag set:    ", cy)                        ;\
85 
                                                                        ;\
86 
        POP(r2)                         /* Retrieve SR */               ;\
87 
        PUSH(r2)                                                        ;\
88 
        LOAD_CONST (r4, SPR_SR_OV)      /* The overflow bit */          ;\
89 
        l.and   r2,r2,r4                                                ;\
90 
        l.sfeq  r2,r4                                                   ;\
91 
        CHECK_FLAG ("- overflow flag set: ", ov)
92 
 
93 
/* ----------------------------------------------------------------------------
94 
 * A macro to carry out a test of addition with an immediate value
95 
 *
96 
 *
97 
 * Arguments
98 
 *   set_flags: Flags to set in the SR
99 
 *   clr_flags: Flags to clear in the SR
100 
 *   opc:       The opcode
101 
 *   op1:       First operand value
102 
 *   op2:       Second operand value (immediate)
103 
 *   res:       Expected result
104 
 *   str:       Output string
105 
 *   cy:        Expected carry flag
106 
 *   ov:        Expected overflow flag
107 
 * ------------------------------------------------------------------------- */
108 
#define TEST_ADDI(set_flags, clr_flags, opc, op1, op2, res, str, cy, ov) \
109 
        l.mfspr r3,r0,SPR_SR                                            ;\
110 
        LOAD_CONST (r2, set_flags)      /* Set flags */                 ;\
111 
        l.or    r3,r3,r2                                                ;\
112 
        LOAD_CONST (r2, ~clr_flags)     /* Clear flags */               ;\
113 
        l.and   r3,r3,r2                                                ;\
114 
        l.mtspr r0,r3,SPR_SR                                            ;\
115 
                                                                        ;\
116 
        LOAD_CONST (r5,op1)             /* Load first number to add */  ;\
117 
        opc     r4,r5,op2                                               ;\
118 
        l.mfspr r2,r0,SPR_SR            /* So we can examine flags */   ;\
119 
        PUSH (r2)                                                       ;\
120 
        CHECK_RES (str, r4, res)                                        ;\
121 
        POP(r2)                         /* Retrieve SR */               ;\
122 
        PUSH(r2)                                                        ;\
123 
        LOAD_CONST (r4, SPR_SR_CY)      /* The carry bit */             ;\
124 
        l.and   r2,r2,r4                                                ;\
125 
        l.sfeq  r2,r4                                                   ;\
126 
        CHECK_FLAG ("- carry flag set:    ", cy)                        ;\
127 
                                                                        ;\
128 
        POP(r2)                         /* Retrieve SR */               ;\
129 
        PUSH(r2)                                                        ;\
130 
        LOAD_CONST (r4, SPR_SR_OV)      /* The overflow bit */          ;\
131 
        l.and   r2,r2,r4                                                ;\
132 
        l.sfeq  r2,r4                                                   ;\
133 
        CHECK_FLAG ("- overflow flag set: ", ov)
134 
 
135 
 
136 112 jeremybenn 
        .section .text
137 
        .global _start
138 
_start:
139 
 
140 
/* ----------------------------------------------------------------------------
141 
 * Test of add signed, l.add
142 
 * ------------------------------------------------------------------------- */
143 
_add:
144 
        LOAD_STR (r3, "l.add\n")
145 
        l.jal   _puts
146 
        l.nop
147 
 
148 
        /* Add two small positive numbers */
149 114 jeremybenn 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
150 
                  l.add, 1, 2, 3,
151 
                  "0x00000001 + 0x00000002 = 0x00000003: ",
152 
                  FALSE, FALSE)
153 
 
154 
        /* Check carry in is ignored. */
155 
        TEST_ADD (SPR_SR_CY, SPR_SR_OV,
156 
                  l.add, 1, 2, 3,
157 
                  "0x00000001 + 0x00000002 = 0x00000003: ",
158 
                  FALSE, FALSE)
159 
 
160 
        /* Add two small negative numbers. Sets the carry flag but not the
161 
           overflow flag. */
162 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
163 
                  l.add, 0xffffffff, 0xfffffffe, 0xfffffffd,
164 
                  "0xffffffff + 0xfffffffe = 0xfffffffd: ",
165 
                  TRUE, FALSE)
166 
 
167 
        /* Add two quite large positive numbers. Should set neither the
168 
           overflow nor the carry flag. */
169 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
170 
                  l.add, 0x40000000, 0x3fffffff, 0x7fffffff,
171 
                  "0x40000000 + 0x3fffffff = 0x7fffffff: ",
172 
                  FALSE, FALSE)
173 
 
174 
        /* Add two large positive numbers. Should set the overflow, but not
175 
           the carry flag. */
176 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
177 
                  l.add, 0x40000000, 0x40000000, 0x80000000,
178 
                  "0x40000000 + 0x40000000 = 0x80000000: ",
179 
                  FALSE, TRUE)
180 
 
181 
        /* Add two quite large negative numbers. Should set the carry, but not
182 
           the overflow flag. */
183 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
184 
                  l.add, 0xc0000000, 0xc0000000, 0x80000000,
185 
                  "0xc0000000 + 0xc0000000 = 0x80000000: ",
186 
                  TRUE, FALSE)
187 
 
188 
        /* Add two large negative numbers. Should set both the overflow and
189 
           carry flags. */
190 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
191 
                  l.add, 0xbfffffff, 0xbfffffff, 0x7ffffffe,
192 
                  "0xbfffffff + 0xbfffffff = 0x7ffffffe: ",
193 
                  TRUE, TRUE)
194 
 
195 
        /* Check that range exceptions are triggered */
196 112 jeremybenn 
        l.mfspr r3,r0,SPR_SR
197 114 jeremybenn 
        LOAD_CONST (r2, SPR_SR_OVE)     /* Set OVE */
198 
        l.or    r3,r3,r2
199 112 jeremybenn 
        l.mtspr r0,r3,SPR_SR
200 114 jeremybenn 
 
201 
        LOAD_STR (r3, "  ** OVE flag set **\n")
202 
        l.jal   _puts
203 
        l.nop
204 112 jeremybenn 
 
205 114 jeremybenn 
        /* Check that an overflow alone causes a RANGE Exception. */
206 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
207 
                  l.add, 0x40000000, 0x40000000, 0x80000000,
208 
                  "0x40000000 + 0x40000000 = 0x80000000: ",
209 
                  FALSE, TRUE)
210 112 jeremybenn 
 
211 114 jeremybenn 
        /* Check that a carry alone does not cause a RANGE Exception. */
212 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
213 
                  l.add, 0xffffffff, 0xfffffffe, 0xfffffffd,
214 
                  "0xffffffff + 0xfffffffe = 0xfffffffd: ",
215 
                  TRUE, FALSE)
216 112 jeremybenn 
 
217 114 jeremybenn 
        /* Check that carry and overflow together cause an exception. */
218 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
219 
                  l.add, 0xbfffffff, 0xbfffffff, 0x7ffffffe,
220 
                  "0xbfffffff + 0xbfffffff = 0x7ffffffe: ",
221 
                  TRUE, TRUE)
222 112 jeremybenn 
 
223 114 jeremybenn 
        /* Finished checking range exceptions */
224 112 jeremybenn 
        l.mfspr r3,r0,SPR_SR
225 114 jeremybenn 
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
226 112 jeremybenn 
        l.and   r3,r3,r2
227 
        l.mtspr r0,r3,SPR_SR
228 114 jeremybenn 
 
229 
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
230 
        l.jal   _puts
231 
        l.nop
232 112 jeremybenn 
 
233 114 jeremybenn 
/* ----------------------------------------------------------------------------
234 
 * Test of add signed and carry, l.addc
235 
 * ------------------------------------------------------------------------- */
236 
_addc:
237 
        LOAD_STR (r3, "l.addc\n")
238 
        l.jal   _puts
239 
        l.nop
240 112 jeremybenn 
 
241 114 jeremybenn 
        /* Add two small positive numbers */
242 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
243 
                  l.addc, 1, 2, 3,
244 
                  "0x00000001 + 0x00000002     = 0x00000003: ",
245 
                  FALSE, FALSE)
246 112 jeremybenn 
 
247 114 jeremybenn 
        /* Add two small negative numbers. Sets the carry flag but not the
248 
           overflow flag. */
249 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
250 
                  l.addc, 0xffffffff, 0xfffffffe, 0xfffffffd,
251 
                  "0xffffffff + 0xfffffffe     = 0xfffffffd: ",
252 
                  TRUE, FALSE)
253 112 jeremybenn 
 
254 
        /* Add two quite large positive numbers. Should set neither the
255 
           overflow nor the carry flag. */
256 114 jeremybenn 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
257 
                  l.addc, 0x40000000, 0x3fffffff, 0x7fffffff,
258 
                  "0x40000000 + 0x3fffffff     = 0x7fffffff: ",
259 
                  FALSE, FALSE)
260 112 jeremybenn 
 
261 114 jeremybenn 
        /* Add two quite large positive numbers with a carry in. Should set
262 
           the overflow but not the carry flag. */
263 
        TEST_ADD (SPR_SR_CY, SPR_SR_OV,
264 
                  l.addc, 0x40000000, 0x3fffffff, 0x80000000,
265 
                  "0x40000000 + 0x3fffffff + c = 0x80000000: ",
266 
                  FALSE, TRUE)
267 112 jeremybenn 
 
268 
        /* Add two large positive numbers. Should set the overflow, but not
269 
           the carry flag. */
270 114 jeremybenn 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
271 
                  l.addc, 0x40000000, 0x40000000, 0x80000000,
272 
                  "0x40000000 + 0x40000000     = 0x80000000: ",
273 
                  FALSE, TRUE)
274 112 jeremybenn 
 
275 114 jeremybenn 
        /* Add the largest unsigned value to zero with a carry. This
276 
           potentially can break a simplistic test for carry that does not
277 
           consider the carry flag properly. Do it both ways around. */
278 
        TEST_ADD (SPR_SR_CY, SPR_SR_OV,
279 
                  l.addc, 0xffffffff, 0x00000000, 0x00000000,
280 
                  "0xffffffff + 0x00000000 + c = 0x00000000: ",
281 
                  TRUE, FALSE)
282 112 jeremybenn 
 
283 114 jeremybenn 
        TEST_ADD (SPR_SR_CY, SPR_SR_OV,
284 
                  l.addc, 0x00000000, 0xffffffff, 0x00000000,
285 
                  "0x00000000 + 0xffffffff + c = 0x00000000: ",
286 
                  TRUE, FALSE)
287 112 jeremybenn 
 
288 
        /* Add two quite large negative numbers. Should set the carry, but not
289 
           the overflow flag. flag. */
290 114 jeremybenn 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
291 
                  l.addc, 0xc0000000, 0xc0000000, 0x80000000,
292 
                  "0xc0000000 + 0xc0000000     = 0x80000000: ",
293 
                  TRUE, FALSE)
294 
 
295 
        /* Add two quite large negative numbers that would overflow, with a
296 
           carry that just avoids the overflow. Should set the carry, but not
297 
           the overflow flag. flag. */
298 
        TEST_ADD (SPR_SR_CY, SPR_SR_OV,
299 
                  l.addc, 0xc0000000, 0xbfffffff, 0x80000000,
300 
                  "0xc0000000 + 0xbfffffff + c = 0x80000000: ",
301 
                  TRUE, FALSE)
302 
 
303 
        /* Add two large negative numbers. Should set both the overflow and
304 
           carry flags. */
305 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
306 
                  l.addc, 0xbfffffff, 0xbfffffff, 0x7ffffffe,
307 
                  "0xbfffffff + 0xbfffffff     = 0x7ffffffe: ",
308 
                  TRUE, TRUE)
309 
 
310 
        /* Check that range exceptions are triggered */
311 112 jeremybenn 
        l.mfspr r3,r0,SPR_SR
312 114 jeremybenn 
        LOAD_CONST (r2, SPR_SR_OVE)     /* Set OVE */
313 
        l.or    r3,r3,r2
314 112 jeremybenn 
        l.mtspr r0,r3,SPR_SR
315 114 jeremybenn 
 
316 
        LOAD_STR (r3, "  ** OVE flag set **\n")
317 
        l.jal   _puts
318 
        l.nop
319 112 jeremybenn 
 
320 114 jeremybenn 
        /* Check that an overflow alone causes a RANGE Exception, even when it
321 
           is the carry that causes the overflow. */
322 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
323 
                  l.addc, 0x40000000, 0x40000000, 0x80000000,
324 
                  "0x40000000 + 0x40000000     = 0x80000000: ",
325 
                  FALSE, TRUE)
326 112 jeremybenn 
 
327 114 jeremybenn 
        TEST_ADD (SPR_SR_CY, SPR_SR_OV,
328 
                  l.addc, 0x40000000, 0x3fffffff, 0x80000000,
329 
                  "0x40000000 + 0x3fffffff + c = 0x80000000: ",
330 
                  FALSE, TRUE)
331 112 jeremybenn 
 
332 114 jeremybenn 
        /* Check that a carry alone does not cause a RANGE Exception, even
333 
           when it is the carry that causes the overflow. */
334 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
335 
                  l.addc, 0xffffffff, 0xfffffffe, 0xfffffffd,
336 
                  "0xffffffff + 0xfffffffe     = 0xfffffffd: ",
337 
                  TRUE, FALSE)
338 112 jeremybenn 
 
339 114 jeremybenn 
        TEST_ADD (SPR_SR_CY, SPR_SR_OV,
340 
                  l.addc, 0x00000000, 0xffffffff, 0x00000000,
341 
                  "0x00000000 + 0xffffffff + c = 0x00000000: ",
342 
                  TRUE, FALSE)
343 
 
344 
        /* Check that carry and overflow together cause an exception. */
345 
        TEST_ADD (0, SPR_SR_CY | SPR_SR_OV,
346 
                  l.addc, 0xbfffffff, 0xbfffffff, 0x7ffffffe,
347 
                  "0xbfffffff + 0xbfffffff     = 0x7ffffffe: ",
348 
                  TRUE, TRUE)
349 
 
350 
        /* Finished checking range exceptions */
351 112 jeremybenn 
        l.mfspr r3,r0,SPR_SR
352 114 jeremybenn 
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
353 112 jeremybenn 
        l.and   r3,r3,r2
354 
        l.mtspr r0,r3,SPR_SR
355 114 jeremybenn 
 
356 
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
357 
        l.jal   _puts
358 
        l.nop
359 112 jeremybenn 
 
360 114 jeremybenn 
/* ----------------------------------------------------------------------------
361 
 * Test of add signed immediate, l.addi
362 
 * ------------------------------------------------------------------------- */
363 
_addi:
364 
        LOAD_STR (r3, "l.addi\n")
365 
        l.jal   _puts
366 
        l.nop
367 112 jeremybenn 
 
368 114 jeremybenn 
        /* Add two small positive numbers */
369 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
370 
                   l.addi, 1, 2, 3,
371 
                   "0x00000001 + 0x00000002 = 0x00000003: ",
372 
                   FALSE, FALSE)
373 112 jeremybenn 
 
374 114 jeremybenn 
        /* Check carry in is ignored. */
375 
        TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
376 
                   l.addi, 1, 2, 3,
377 
                   "0x00000001 + 0x00000002 = 0x00000003: ",
378 
                   FALSE, FALSE)
379 112 jeremybenn 
 
380 114 jeremybenn 
        /* Add two small negative numbers. Sets the carry flag but not the
381 
           overflow flag. */
382 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
383 
                   l.addi, 0xffffffff, 0xfffe, 0xfffffffd,
384 
                   "0xffffffff + 0xfffffffe = 0xfffffffd: ",
385 
                   TRUE, FALSE)
386 
 
387 
        /* Add two quite large positive numbers. Should set neither the
388 
           overflow nor the carry flag. */
389 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
390 
                   l.addi, 0x7fff8000, 0x7fff, 0x7fffffff,
391 
                   "0x7fff8000 + 0x00007fff = 0x7fffffff: ",
392 
                   FALSE, FALSE)
393 
 
394 
        /* Add two large positive numbers. Should set the overflow, but not
395 
           the carry flag. */
396 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
397 
                   l.addi, 0x7fffc000, 0x4000, 0x80000000,
398 
                   "0x7fffc000 + 0x00004000 = 0x80000000: ",
399 
                   FALSE, TRUE)
400 
 
401 
        /* Add two quite large negative numbers. Should set the carry, but not
402 
           the overflow flag. */
403 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
404 
                   l.addi, 0x80008000, 0x8000, 0x80000000,
405 
                   "0x80008000 + 0xffff8000 = 0x80000000: ",
406 
                   TRUE, FALSE)
407 
 
408 
        /* Add two large negative numbers. Should set both the overflow and
409 
           carry flags. */
410 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
411 
                   l.addi, 0x80007fff, 0x8000, 0x7fffffff,
412 
                   "0x80007fff + 0xffff8000 = 0x7fffffff: ",
413 
                   TRUE, TRUE)
414 
 
415 112 jeremybenn 
        /* Check that range exceptions are triggered */
416 114 jeremybenn 
        l.mfspr r3,r0,SPR_SR
417 112 jeremybenn 
        LOAD_CONST (r2, SPR_SR_OVE)     /* Set OVE */
418 
        l.or    r3,r3,r2
419 
        l.mtspr r0,r3,SPR_SR
420 
 
421 114 jeremybenn 
        LOAD_STR (r3, "  ** OVE flag set **\n")
422 112 jeremybenn 
        l.jal   _puts
423 
        l.nop
424 
 
425 
        /* Check that an overflow alone causes a RANGE Exception. */
426 114 jeremybenn 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
427 
                   l.addi, 0x7fffc000, 0x4000, 0x80000000,
428 
                   "0x7fffc000 + 0x00004000 = 0x80000000: ",
429 
                   FALSE, TRUE)
430 
 
431 
        /* Check that a carry alone does not cause a RANGE Exception. */
432 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
433 
                   l.addi, 0xffffffff, 0xfffe, 0xfffffffd,
434 
                   "0xffffffff + 0xfffffffe = 0xfffffffd: ",
435 
                   TRUE, FALSE)
436 
 
437 
        /* Check that carry and overflow together cause an exception. */
438 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
439 
                   l.addi, 0x80007fff, 0x8000, 0x7fffffff,
440 
                   "0x80007fff + 0xffff8000 = 0x7ffffffe: ",
441 
                   TRUE, TRUE)
442 
 
443 
        /* Finished checking range exceptions */
444 112 jeremybenn 
        l.mfspr r3,r0,SPR_SR
445 114 jeremybenn 
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
446 112 jeremybenn 
        l.and   r3,r3,r2
447 
        l.mtspr r0,r3,SPR_SR
448 114 jeremybenn 
 
449 
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
450 
        l.jal   _puts
451 
        l.nop
452 112 jeremybenn 
 
453 114 jeremybenn 
/* ----------------------------------------------------------------------------
454 
 * Test of add signed and carry, l.addic
455 
 * ------------------------------------------------------------------------- */
456 
_addic:
457 
        LOAD_STR (r3, "l.addic\n")
458 
        l.jal   _puts
459 
        l.nop
460 112 jeremybenn 
 
461 114 jeremybenn 
        /* Add two small positive numbers */
462 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
463 
                   l.addic, 1, 2, 3,
464 
                   "0x00000001 + 0x00000002     = 0x00000003: ",
465 
                   FALSE, FALSE)
466 112 jeremybenn 
 
467 114 jeremybenn 
        /* Add two small negative numbers. Sets the carry flag but not the
468 
           overflow flag. */
469 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
470 
                   l.addic, 0xffffffff, 0xfffe, 0xfffffffd,
471 
                   "0xffffffff + 0xfffffffe     = 0xfffffffd: ",
472 
                   TRUE, FALSE)
473 112 jeremybenn 
 
474 114 jeremybenn 
        /* Add two quite large positive numbers. Should set neither the
475 
           overflow nor the carry flag. */
476 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
477 
                   l.addic, 0x7fff8000, 0x7fff, 0x7fffffff,
478 
                   "0x7fff8000 + 0x00007fff     = 0x7fffffff: ",
479 
                   FALSE, FALSE)
480 112 jeremybenn 
 
481 114 jeremybenn 
        /* Add two quite large positive numbers with a carry in. Should set
482 
           the overflow but not the carry flag. */
483 
        TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
484 
                   l.addic, 0x7fff8000, 0x7fff, 0x80000000,
485 
                   "0x7fff8000 + 0x00007fff + c = 0x80000000: ",
486 
                   FALSE, TRUE)
487 112 jeremybenn 
 
488 114 jeremybenn 
        /* Add two large positive numbers. Should set the overflow, but not
489 
           the carry flag. */
490 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
491 
                   l.addic, 0x7fffc000, 0x4000, 0x80000000,
492 
                   "0x7fffc000 + 0x00004000     = 0x80000000: ",
493 
                   FALSE, TRUE)
494 112 jeremybenn 
 
495 114 jeremybenn 
        /* Add the largest unsigned value to zero with a carry. This
496 
           potentially can break a simplistic test for carry that does not
497 
           consider the carry flag properly. Do it both ways around. */
498 
        TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
499 
                   l.addic, 0xffffffff, 0x0000, 0x00000000,
500 
                   "0xffffffff + 0x00000000 + c = 0x00000000: ",
501 
                   TRUE, FALSE)
502 112 jeremybenn 
 
503 114 jeremybenn 
        TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
504 
                   l.addic, 0x00000000, 0xffff, 0x00000000,
505 
                   "0x00000000 + 0xffffffff + c = 0x00000000: ",
506 
                   TRUE, FALSE)
507 
 
508 
        /* Add two quite large negative numbers. Should set the carry, but not
509 
           the overflow flag. flag. */
510 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
511 
                   l.addic, 0x80008000, 0x8000, 0x80000000,
512 
                   "0x80008000 + 0xffff8000     = 0x80000000: ",
513 
                   TRUE, FALSE)
514 
 
515 
        /* Add two quite large negative numbers that would overflow, with a
516 
           carry that just avoids the overflow. Should set the carry, but not
517 
           the overflow flag. flag. */
518 
        TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
519 
                   l.addic, 0x80007fff, 0x8000, 0x80000000,
520 
                   "0x80007fff + 0xffff8000 + c = 0x80000000: ",
521 
                   TRUE, FALSE)
522 
 
523 
        /* Add two large negative numbers. Should set both the overflow and
524 
           carry flags. */
525 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
526 
                   l.addic, 0x80007fff, 0x8000, 0x7fffffff,
527 
                   "0x80007fff + 0xffff8000     = 0x7fffffff: ",
528 
                   TRUE, TRUE)
529 
 
530 
        /* Check that range exceptions are triggered */
531 112 jeremybenn 
        l.mfspr r3,r0,SPR_SR
532 114 jeremybenn 
        LOAD_CONST (r2, SPR_SR_OVE)     /* Set OVE */
533 
        l.or    r3,r3,r2
534 112 jeremybenn 
        l.mtspr r0,r3,SPR_SR
535 114 jeremybenn 
 
536 
        LOAD_STR (r3, "  ** OVE flag set **\n")
537 
        l.jal   _puts
538 
        l.nop
539 112 jeremybenn 
 
540 114 jeremybenn 
        /* Check that an overflow alone causes a RANGE Exception, even when it
541 
           is the carry that causes the overflow. */
542 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
543 
                   l.addic, 0x7fffc000, 0x4000, 0x80000000,
544 
                   "0x7fffc000 + 0x00004000     = 0x80000000: ",
545 
                   FALSE, TRUE)
546 112 jeremybenn 
 
547 114 jeremybenn 
        TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
548 
                   l.addic, 0x7fffc000, 0x3fff, 0x80000000,
549 
                   "0x7fffc000 + 0x00003fff + c = 0x80000000: ",
550 
                   FALSE, TRUE)
551 112 jeremybenn 
 
552 114 jeremybenn 
        /* Check that a carry alone does not cause a RANGE Exception, even
553 
           when it is the carry that causes the overflow. */
554 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
555 
                   l.addic, 0xffffffff, 0xfffe, 0xfffffffd,
556 
                   "0xffffffff + 0xfffffffe     = 0xfffffffd: ",
557 
                   TRUE, FALSE)
558 112 jeremybenn 
 
559 114 jeremybenn 
        TEST_ADDI (SPR_SR_CY, SPR_SR_OV,
560 
                   l.addic, 0x00000000, 0xffff, 0x00000000,
561 
                   "0x00000000 + 0xffffffff + c = 0x00000000: ",
562 
                   TRUE, FALSE)
563 
 
564 
        /* Check that carry and overflow together cause an exception. */
565 
        TEST_ADDI (0, SPR_SR_CY | SPR_SR_OV,
566 
                   l.addic, 0x80007fff, 0x8000, 0x7fffffff,
567 
                   "0x80007fff + 0xffff8000     = 0x7ffffffe: ",
568 
                   TRUE, TRUE)
569 
 
570 112 jeremybenn 
        /* Finished checking range exceptions */
571 114 jeremybenn 
        l.mfspr r3,r0,SPR_SR
572 112 jeremybenn 
        LOAD_CONST (r2, ~SPR_SR_OVE)    /* Clear OVE */
573 
        l.and   r3,r3,r2
574 
        l.mtspr r0,r3,SPR_SR
575 
 
576 114 jeremybenn 
        LOAD_STR (r3, "  ** OVE flag cleared **\n")
577 112 jeremybenn 
        l.jal   _puts
578 
        l.nop
579 
 
580 
/* ----------------------------------------------------------------------------
581 
 * All done
582 
 * ------------------------------------------------------------------------- */
583 
_exit:
584 
        LOAD_STR (r3, "Test completed\n")
585 
        l.jal   _puts
586 
        l.nop
587 
 
588 
        TEST_EXIT

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.