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/* dyn-rec.c -- Dynamic recompiler implementation for or32

   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

#include <stdio.h>

#include <stdlib.h>

#include <string.h>

#include <sys/mman.h>

#include <signal.h>

#include <errno.h>

#include <execinfo.h>

#include "config.h"

#ifdef HAVE_INTTYPES_H

#include <inttypes.h>

#endif

#include "port.h"

#include "arch.h"

#include "immu.h"

#include "abstract.h"

#include "opcode/or32.h"

#include "spr-defs.h"

#include "execute.h"

#include "except.h"

#include "spr-defs.h"

#include "sim-config.h"

#include "sched.h"

#include "i386-regs.h"

#include "def-op-t.h"

#include "dyn-rec.h"

#include "gen-ops.h"

#include "op-support.h"

#include "toplevel-support.h"

/* NOTE: All openrisc (or) addresses in this file are *PHYSICAL* addresses */

/* FIXME: Optimise sorted list adding */

typedef void (*generic_gen_op)(struct op_queue *opq, int end);

typedef void (*imm_gen_op)(struct op_queue *opq, int end, uorreg_t imm);

void gen_l_invalid(struct op_queue *opq, int param_t[3], int delay_slot);

/* ttg->temporary to gpr */

DEF_GPR_OP(generic_gen_op, gen_op_move_gpr_t, gen_op_ttg_gpr);

/* gtt->gpr to temporary */

DEF_GPR_OP(generic_gen_op, gen_op_move_t_gpr, gen_op_gtt_gpr);

DEF_1T_OP(imm_gen_op, calc_insn_ea_table, gen_op_calc_insn_ea);

/* Linker stubs.  This will allow the linker to link in op.o.  The relocations

 * that the linker does for these will be irrelevent anyway, since we patch the

 * relocations during recompilation. */

uorreg_t __op_param1;

uorreg_t __op_param2;

uorreg_t __op_param3;

/* The number of bytes that a dynamicly recompiled page should be enlarged by */

#define RECED_PAGE_ENLARGE_BY 51200

/* The number of entries that the micro operations array in op_queue should be

 * enlarged by */

#define OPS_ENLARGE_BY 5

#define T_NONE (-1)

/* Temporary is used as a source operand */

#define TFLAG_SRC 1

/* Temporary is used as a destination operand */

#define TFLAG_DST 2

/* Temporary has been saved to permanent storage */

#define TFLAG_SAVED 4

/* Temporary contains the value of the register before the instruction execution

 * occurs (either by an explicit reg->t move or implicitly being left over from

 * a previous instruction) */

#define TFLAG_SOURCED 8

/* FIXME: Put this into some header */

extern int do_stats;

static int sigsegv_state = 0;

static void *sigsegv_addr = NULL;

void dyn_ret_stack_prot(void);

void dyn_sigsegv_debug(int u, siginfo_t *siginf, void *dat)

{

  struct dyn_page *dp;

  FILE *f;

  char filen[18]; /* 18 == strlen("or_page.%08x") + 1 */

  int i;

  struct sigcontext *sigc = dat;

  if(!sigsegv_state) {

    sigsegv_addr = siginf->si_addr;

  } else {

    fprintf(stderr, "Nested SIGSEGV occured, dumping next chuck of info\n");

    sigsegv_state++;

  }

  /* First dump all the data that does not need dereferenceing to get */

  switch(sigsegv_state) {

  case 0:

    fflush(stderr);

    fprintf(stderr, "Segmentation fault on acces to %p at 0x%08lx, (or address: 0x%"PRIxADDR")\n\n",

            sigsegv_addr, sigc->eip, cpu_state.pc);

    sigsegv_state++;

  case 1:

    /* Run through the recompiled pages, dumping them to disk as we go */

    for(i = 0; i < (2 << (32 - immu_state->pagesize_log2)); i++) {

      dp = cpu_state.dyn_pages[i];

      if(!dp)

        continue;

      fprintf(stderr, "Dumping%s page 0x%"PRIxADDR" recompiled to %p (len: %u) to disk\n",

             dp->dirty ? " dirty" : "", dp->or_page, dp->host_page,

             dp->host_len);

      fflush(stdout);

      sprintf(filen, "or_page.%"PRIxADDR, dp->or_page);

      if(!(f = fopen(filen, "w"))) {

        fprintf(stderr, "Unable to open %s to dump the recompiled page to: %s\n",

                filen, strerror(errno));

        continue;

      }

      if(fwrite(dp->host_page, dp->host_len, 1, f) < 1)

        fprintf(stderr, "Unable to write recompiled data to file: %s\n",

                strerror(errno));

      fclose(f);

    }

    sigsegv_state++;

  case 2:

    sim_done();

  }

}

struct dyn_page *new_dp(oraddr_t page)

{

  struct dyn_page *dp = malloc(sizeof(struct dyn_page));

  dp->or_page = IADDR_PAGE(page);

  dp->locs = malloc(sizeof(void *) * (immu_state->pagesize / 4));

  dp->host_len = 0;

  dp->host_page = NULL;

  dp->dirty = 1;

  if(do_stats) {

    dp->insns = malloc(immu_state->pagesize);

    dp->insn_indexs = malloc(sizeof(unsigned int) * (immu_state->pagesize / 4));

  }

  cpu_state.dyn_pages[dp->or_page >> immu_state->pagesize_log2] = dp;

  return dp;

}

void dyn_main(void)

{

  struct dyn_page *target_dp;

  oraddr_t phys_page;

  setjmp(cpu_state.excpt_loc);

  for(;;) {

    phys_page = immu_translate(cpu_state.pc);

/*

    printf("Recompiled code jumping out to %"PRIxADDR" from %"PRIxADDR"\n",

           phys_page, cpu_state.sprs[SPR_PPC] - 4);

*/

    /* immu_translate() adds the hit delay to runtime.sim.mem_cycles but we add

     * it to the cycles when the instruction is executed so if we don't reset it

     * now it will produce wrong results */

    runtime.sim.mem_cycles = 0;

    target_dp = cpu_state.dyn_pages[phys_page >> immu_state->pagesize_log2];

    if(!target_dp)

      target_dp = new_dp(phys_page);

    /* Since writes to the 0x0-0xff range do not dirtyfy a page recompile the

     *  0x0 page if the jump is to that location */

    if(phys_page < 0x100)

      target_dp->dirty = 1;

    if(target_dp->dirty)

      recompile_page(target_dp);

    cpu_state.curr_page = target_dp;

    /* FIXME: If the page is backed by more than one type of memory, this will

     * produce wrong results */

    cpu_state.cycles_dec = target_dp->delayr;

    if(cpu_state.sprs[SPR_SR] & SPR_SR_IME)

      /* Add the mmu hit delay to the cycle counter */

      cpu_state.cycles_dec -= immu_state->hitdelay;

    /* FIXME: ebp, ebx, esi and edi are expected to be preserved across function

     * calls but the recompiled code trashes them... */

    enter_dyn_code(phys_page, target_dp);

  }

}

static void immu_retranslate(void *dat)

{

  int got_en_dis = (int)dat;

  immu_translate(cpu_state.pc);

  runtime.sim.mem_cycles = 0;

  /* Only update the cycle decrementer if the mmu got enabled or disabled */

  if(got_en_dis == IMMU_GOT_ENABLED)

    /* Add the mmu hit delay to the cycle counter */

    cpu_state.cycles_dec = cpu_state.curr_page->delayr - immu_state->hitdelay;

  else if(got_en_dis == IMMU_GOT_DISABLED)

    cpu_state.cycles_dec = cpu_state.curr_page->delayr;

}

/* This is called whenever the immu is either enabled/disabled or reconfigured

 * while enabled.  This checks if an itlb miss would occour and updates the immu

 * hit delay counter */

void recheck_immu(int got_en_dis)

{

  oraddr_t addr;

  if(cpu_state.delay_insn)

    addr = cpu_state.pc_delay;

  else

    addr = cpu_state.pc + 4;

  if(IADDR_PAGE(cpu_state.pc) == IADDR_PAGE(addr))

    /* Schedule a job to do immu_translate() */

    SCHED_ADD(immu_retranslate, (void *)got_en_dis, 0);

}

/* Runs the scheduler.  Called from except_handler (and dirtyfy_page below) */

void run_sched_out_of_line(void)

{

  oraddr_t off = (cpu_state.pc & immu_state->page_offset_mask) >> 2;

  if(do_stats) {

    cpu_state.iqueue.insn_addr = cpu_state.pc;

    cpu_state.iqueue.insn = cpu_state.curr_page->insns[off];

    cpu_state.iqueue.insn_index = cpu_state.curr_page->insn_indexs[off];

    runtime.cpu.instructions++;

    analysis(&cpu_state.iqueue);

  }

  /* Run the scheduler */

  scheduler.job_queue->time += cpu_state.cycles_dec;

  runtime.sim.cycles -= cpu_state.cycles_dec;

  op_join_mem_cycles();

  if(scheduler.job_queue->time <= 0)

    do_scheduler();

}

/* Signals a page as dirty */

static void dirtyfy_page(struct dyn_page *dp)

{

  oraddr_t check;

  printf("Dirtyfying page 0x%"PRIxADDR"\n", dp->or_page);

  dp->dirty = 1;

  /* If the execution is currently in the page that was touched then recompile

   * it now and jump back to the point of execution */

  check = cpu_state.delay_insn ? cpu_state.pc_delay : cpu_state.pc + 4;

  if(IADDR_PAGE(check) == dp->or_page) {

    run_sched_out_of_line();

    recompile_page(dp);

    cpu_state.delay_insn = 0;

    /* Jump out to the next instruction */

    do_jump(check);

  }

}

/* Checks to see if a write happened to a recompiled page.  If so marks it as

 * dirty */

void dyn_checkwrite(oraddr_t addr)

{

  /* FIXME: Do this with mprotect() */

  struct dyn_page *dp = cpu_state.dyn_pages[addr >> immu_state->pagesize_log2];

  /* Since the locations 0x0-0xff are nearly always written to in an exception

   * handler, ignore any writes to these locations.  If code ends up jumping

   * out there, we'll recompile when the jump actually happens. */

  if((addr > 0x100) && dp && !dp->dirty)

    dirtyfy_page(dp);

}

/* Moves the temprary t to its permanent storage if it has been used as a

 * destination register */

static void ship_t_out(struct op_queue *opq, unsigned int t)

{

  unsigned int gpr = opq->reg_t[t];

  for(; opq; opq = opq->prev) {

    if(opq->reg_t[t] != gpr)

      return;

    if((opq->tflags[t] & TFLAG_DST) && !(opq->tflags[t] & TFLAG_SAVED)) {

      opq->tflags[t] |= TFLAG_SAVED;

      /* FIXME: Check if this is still neccesary */

      /* Before takeing the temporaries out, temporarily remove the op_do_sched

       * operation such that dyn_page->ts_bound shall be correct before the

       * scheduler runs */

      if(opq->num_ops && (opq->ops[opq->num_ops - 1] == op_do_sched_indx)) {

        opq->num_ops--;

        gen_op_move_gpr_t[t][gpr](opq, 1);

        gen_op_do_sched(opq, 1);

        return;

      }

      gen_op_move_gpr_t[t][gpr](opq, 1);

      return;

    }

  }

}

static void ship_gprs_out_t(struct op_queue *opq)

{

  int i;

  if(!opq)

    return;

  for(i = 0; i < NUM_T_REGS; i++) {

    if(opq->reg_t[i] < 32)

      /* Ship temporaries out in the last opq that actually touched it */

      ship_t_out(opq, i);

  }

}

/* FIXME: Look at the following instructions to make a better guess at which

 * temporary to return */

static int find_t(struct op_queue *opq, unsigned int reg)

{

  int i, j, t = -1;

  for(i = 0; i < NUM_T_REGS; i++) {

    if(opq->reg_t[i] == reg)

      return i;

    /* Ok, we have found an as-yet unused temporary, check if it is needed

     * later in this instruction */

    for(j = 0; j < opq->param_num; j++) {

      if((opq->param_type[j] & OPTYPE_REG) && (opq->param[j] == opq->reg_t[i]))

        break;

    }

    if(j != opq->param_num)

      continue;

    /* We have found the temporary (temporarily:) fit for use */

    if((t == -1) || (opq->reg_t[i] == 32))

      t = i;

  }

  return t;

}

/* Checks if there is enough space in dp->host_page, if not grow it */

void *enough_host_page(struct dyn_page *dp, void *cur, unsigned int *len,

                       unsigned int amount)

{

  unsigned int used = cur - dp->host_page;

  /* The array is long enough */

  if((used + amount) <= *len)

    return cur;

  /* Reallocate */

  *len += RECED_PAGE_ENLARGE_BY;

  if(!(dp->host_page = realloc(dp->host_page, *len))) {

    fprintf(stderr, "OOM\n");

    exit(1);

  }

  return dp->host_page + used;

}

/* Adds an operation to the opq */

void add_to_opq(struct op_queue *opq, int end, int op)

{

  if(opq->num_ops == opq->ops_len) {

    opq->ops_len += OPS_ENLARGE_BY;

    if(!(opq->ops = realloc(opq->ops, opq->ops_len * sizeof(int)))) {

      fprintf(stderr, "OOM\n");

      exit(1);

    }

  }

  if(end)

    opq->ops[opq->num_ops] = op;

  else {

    /* Shift everything over by one */

    memmove(opq->ops + 1, opq->ops, opq->num_ops* sizeof(int));

    opq->ops[0] = op;

  }

  opq->num_ops++;

}

static void gen_op_mark_loc(struct op_queue *opq, int end)

{

  add_to_opq(opq, end, op_mark_loc_indx);

}

/* Adds a parameter to the opq */

void add_to_op_params(struct op_queue *opq, int end, unsigned long param)

{

  if(opq->num_ops_param == opq->ops_param_len) {

    opq->ops_param_len += OPS_ENLARGE_BY;

    if(!(opq->ops_param = realloc(opq->ops_param, opq->ops_param_len * sizeof(int)))) {

      fprintf(stderr, "OOM\n");

      exit(1);

    }

  }

  if(end)

    opq->ops_param[opq->num_ops_param] = param;

  else {

    /* Shift everything over by one */

    memmove(opq->ops_param + 1, opq->ops_param, opq->num_ops_param);

    opq->ops_param[0] = param;

  }

  opq->num_ops_param++;

}

/* Initialises the recompiler */

void init_dyn_recomp(void)

{

  struct sigaction sigact;

  struct op_queue *opq = NULL;

  unsigned int i;

  cpu_state.opqs = NULL;

  /* Allocate the operation queue list (+1 for the page chaining) */

  for(i = 0; i < (immu_state->pagesize / 4) + 1; i++) {

    if(!(opq = malloc(sizeof(struct op_queue)))) {

      fprintf(stderr, "OOM\n");

      exit(1);

    }

    /* initialise some fields */

    opq->ops_len = 0;

    opq->ops = NULL;

    opq->ops_param_len = 0;

    opq->ops_param = NULL;

    opq->xref = 0;

    if(cpu_state.opqs)

      cpu_state.opqs->prev = opq;

    opq->next = cpu_state.opqs;

    cpu_state.opqs = opq;

  }

  opq->prev = NULL;

  cpu_state.curr_page = NULL;

  if(!(cpu_state.dyn_pages = malloc(sizeof(void *) * (2 << (32 -

                                                immu_state->pagesize_log2))))) {

    fprintf(stderr, "OOM\n");

    exit(1);

  }

  memset(cpu_state.dyn_pages, 0,

         sizeof(void *) * (2 << (32 - immu_state->pagesize_log2)));

  /* Register our segmentation fault handler */

  sigact.sa_sigaction = dyn_sigsegv_debug;

  memset(&sigact.sa_mask, 0, sizeof(sigact.sa_mask));

  sigact.sa_flags = SA_SIGINFO | SA_NOMASK;

  if(sigaction(SIGSEGV, &sigact, NULL))

    printf("WARN: Unable to install SIGSEGV handler! Don't expect to be able to debug the recompiler.\n");

  /* FIXME: Find a better place for this */

    { /* Needed by execution */

      extern int do_stats;

      do_stats = config.cpu.dependstats || config.cpu.superscalar || config.cpu.dependstats

              || config.sim.history || config.sim.exe_log;

    }

  printf("Recompile engine up and running\n");

}

/* Parses instructions and their operands and populates opq with them */

static void eval_insn_ops(struct op_queue *opq, oraddr_t addr)

{

  int breakp;

  struct insn_op_struct *opd;

  for(; opq->next; opq = opq->next, addr += 4) {

    opq->param_num = 0;

    breakp = 0;

    opq->insn = eval_insn(addr, &breakp);

    /* FIXME: If a breakpoint is set at this location, insert exception code */

    if(breakp) {

      fprintf(stderr, "FIXME: Insert breakpoint code\n");

    }

    opq->insn_index = insn_decode(opq->insn);

    if(opq->insn_index == -1)

      continue;

    opd = op_start[opq->insn_index];

    do {

      opq->param[opq->param_num] = eval_operand_val(opq->insn, opd);

      opq->param_type[opq->param_num] = opd->type;

      opq->param_num++;

      while(!(opd->type & OPTYPE_OP)) opd++;

    } while(!(opd++->type & OPTYPE_LAST));

  }

}

/* Adds code to the opq for the instruction pointed to by addr */

static void recompile_insn(struct op_queue *opq, int delay_insn)

{

  int j, k;

  int param_t[5]; /* Which temporary the parameters reside in */

  /* Check if we have an illegal instruction */

  if(opq->insn_index == -1) {

    gen_l_invalid(opq, NULL, delay_insn);

    return;

  }

  /* If we are recompileing an instruction that has a delay slot and is in the

   * delay slot, ignore it.  This is undefined behavour. */

  if(delay_insn && (or32_opcodes[opq->insn_index].flags & OR32_IF_DELAY))

    return;

  param_t[0] = T_NONE;

  param_t[1] = T_NONE;

  param_t[2] = T_NONE;

  param_t[3] = T_NONE;

  param_t[4] = T_NONE;

  /* Jump instructions are special since they have a delay slot and thus they

   * need to control the exact operation sequence.  Special case these here to

   * avoid haveing loads of if(!(.& OR32_IF_DELAY)) below */

  if(or32_opcodes[opq->insn_index].flags & OR32_IF_DELAY) {

    /* Jump instructions don't have a disposition */

    or32_opcodes[opq->insn_index].exec(opq, param_t, delay_insn);

    /* Analysis is done by the individual jump instructions */

    /* Jump instructions don't touch runtime.sim.mem_cycles */

    /* Jump instructions run their own scheduler */

    return;

  }

  /* Before an exception takes place, all registers must be stored. */

  if((or32_opcodes[opq->insn_index].func_unit == it_exception)) {

    ship_gprs_out_t(opq);

    or32_opcodes[opq->insn_index].exec(opq, param_t, delay_insn);

    return;

  }

  for(j = 0; j < opq->param_num; j++) {

    if(!(opq->param_type[j] & OPTYPE_REG))

      continue;

    /* Never, ever, move r0 into a temporary */

    if(!opq->param[j])

      continue;

    k = find_t(opq, opq->param[j]);

    param_t[j] = k;

    if(opq->reg_t[k] == opq->param[j]) {

      if(!(opq->param_type[j] & OPTYPE_DST) &&

         !(opq->tflags[k] & TFLAG_SOURCED)) {

        gen_op_move_t_gpr[k][opq->reg_t[k]](opq, 0);

        opq->tflags[k] |= TFLAG_SOURCED;

      }

      if(opq->param_type[j] & OPTYPE_DST)

        opq->tflags[k] |= TFLAG_DST;

      else

        opq->tflags[k] |= TFLAG_SRC;

      continue;

    }

    if(opq->reg_t[k] < 32) {

      /* Only ship the temporary out if it has been used as a destination

       * register */

      ship_t_out(opq, k);

    }

    if(opq->param_type[j] & OPTYPE_DST)

      opq->tflags[k] = TFLAG_DST;

    else

      opq->tflags[k] = TFLAG_SRC;

    opq->reg_t[k] = opq->param[j];

    /* Only generate code to move the register into a temporary if it is used as

     * a source operand */

    if(!(opq->param_type[j] & OPTYPE_DST)) {

      gen_op_move_t_gpr[k][opq->reg_t[k]](opq, 0);

      opq->tflags[k] |= TFLAG_SOURCED;

    }

  }

  /* To get the execution log correct for instructions like l.lwz r4,0(r4) the

   * effective address needs to be calculated before the instruction is

   * simulated */

  if(do_stats) {

    for(j = 0; j < opq->param_num; j++) {

      if(!(opq->param_type[j] & OPTYPE_DIS))

        continue;

      if(!opq->param[j + 1])

        gen_op_store_insn_ea(opq, 1, opq->param[j]);

      else

        calc_insn_ea_table[param_t[j + 1]](opq, 1, opq->param[j]);

    }

  }

  or32_opcodes[opq->insn_index].exec(opq, param_t, delay_insn);

  if(do_stats) {

    ship_gprs_out_t(opq);