OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [tags/] [or1ksim/] [or1ksim-0.5.0rc1/] [cpu/] [or32/] [op-2t-op.h] - Blame information for rev 403

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 jeremybenn
/* op-1t-op.h -- Micro operations useing two temporaries
2
   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
This program is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2 of the License, or
9
(at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
__or_dynop void glue(op_move, T)(void)
21
{
22
  T0 = T1;
23
}
24
 
25
__or_dynop void glue(op_ff1, T)(void)
26
{
27
  int i;
28
 
29
  for(i = 0; i < 32; i++, T0 >>= 1) {
30
    if(T0 & 1) {
31
      T1 = i;
32
      break;
33
    }
34
  }
35
 
36
  FORCE_RET;
37
}
38
 
39
 
40
__or_dynop void glue(op_neg, T)(void)
41
{
42
  T0 = -T1;
43
}
44
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.