OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [cmds/] [cpu.c] - Blame information for rev 281

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marcus.erl 
#include "common.h"
2 
#include "support.h"
3 246 julius 
#include "spr-defs.h"
4 2 marcus.erl 
 
5 
int ic_enable_cmd (int argc, char *argv[])
6 
{
7 
  unsigned long addr;
8 
  unsigned long sr;
9 
 
10 
  if (argc) return -1;
11 
  /* Invalidate IC */
12 
  for (addr = 0; addr < 8192; addr += 16)
13 
    asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_ICBIR));
14 
 
15 
  /* Enable IC */
16 
  asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
17 
  sr |= SPR_SR_ICE;
18 
  asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
19 
  asm("l.nop");
20 
  asm("l.nop");
21 
  asm("l.nop");
22 
  asm("l.nop");
23 
  return 0;
24 
}
25 
 
26 
int ic_disable_cmd (int argc, char *argv[])
27 
{
28 
  unsigned long sr;
29 
 
30 
  if (argc) return -1;
31 
  /* Disable IC */
32 
  asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
33 
  sr &= ~SPR_SR_ICE;
34 
  asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
35 
  asm("l.nop");
36 
  asm("l.nop");
37 
  asm("l.nop");
38 
  asm("l.nop");
39 
  return 0;
40 
}
41 
 
42 
int dc_enable_cmd (int argc, char *argv[])
43 
{
44 
  unsigned long addr;
45 
  unsigned long sr;
46 
 
47 
  if (argc) return -1;
48 
  /* Invalidate DC */
49 
  for (addr = 0; addr < 8192; addr += 16)
50 
    asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_DCBIR));
51 
 
52 
  /* Enable DC */
53 
  asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
54 
  sr |= SPR_SR_DCE;
55 
  asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
56 
  asm("l.nop");
57 
  asm("l.nop");
58 
  asm("l.nop");
59 
  asm("l.nop");
60 
  return 0;
61 
}
62 
 
63 
int dc_disable_cmd (int argc, char *argv[])
64 
{
65 
 
66 
  if (argc) return -1;
67 246 julius 
 
68 
  unsigned long sr = mfspr(SPR_SR);
69 
 
70 
  // If it's enabled and write back is on, we'd better flush it first
71 
  // (CWS=1 is write back)
72 
 
73 
  unsigned long dccfgr = mfspr(SPR_DCCFGR);
74 
  int i;
75 
  int bs= (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
76 
  int ways = (1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3));
77 
  for(i=0;i<ways;i++)
78 
      mtspr(SPR_DCBFR, i*bs);
79 
 
80 2 marcus.erl 
  /* Disable DC */
81 
  sr &= ~SPR_SR_DCE;
82 
  asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
83 
  asm("l.nop");
84 
  asm("l.nop");
85 
  asm("l.nop");
86 
  asm("l.nop");
87 
  return 0;
88 
}
89 
 
90 
int mfspr_cmd (int argc, char *argv[])
91 
{
92 
  unsigned long val, addr;
93 
 
94 
  if (argc ==   1) {
95 
    addr = strtoul (argv[0], 0, 0);
96 
    /* Read SPR */
97 
    asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
98 
    printf ("\nSPR %04lx: %08lx", addr, val);
99 
  } else return -1;
100 
        return 0;
101 
}
102 
 
103 
int mtspr_cmd (int argc, char *argv[])
104 
{
105 
  unsigned long val, addr;
106 
  if (argc == 2) {
107 
    addr = strtoul (argv[0], 0, 0);
108 
    val = strtoul (argv[1], 0, 0);
109 
    /* Write SPR */
110 
    asm("l.mtspr %0,%1,0": : "r" (addr), "r" (val));
111 
    asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
112 
    printf ("\nSPR %04lx: %08lx", addr, val);
113 
  } else return -1;
114 
        return 0;
115 
}
116 
 
117 
void module_cpu_init (void)
118 
{
119 
  register_command ("ic_enable", "", "enable instruction cache", ic_enable_cmd);
120 
  register_command ("ic_disable", "", "disable instruction cache", ic_disable_cmd);
121 
  register_command ("dc_enable", "", "enable data cache", dc_enable_cmd);
122 
  register_command ("dc_disable", "", "disable data cache", dc_disable_cmd);
123 
  register_command ("mfspr", "<spr_addr>", "show SPR", mfspr_cmd);
124 
  register_command ("mtspr", "<spr_addr> <value>", "set SPR", mtspr_cmd);
125 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.