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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [cmds/] [cpu.c] - Blame information for rev 299

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Line No. Rev Author Line
1 2 marcus.erl 
#include "common.h"
2 
#include "support.h"
3 246 julius 
#include "spr-defs.h"
4 2 marcus.erl 
 
5 
int ic_enable_cmd (int argc, char *argv[])
6 
{
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  unsigned long addr;
8 
  unsigned long sr;
9 
 
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  if (argc) return -1;
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  /* Invalidate IC */
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  for (addr = 0; addr < 8192; addr += 16)
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    asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_ICBIR));
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  /* Enable IC */
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  asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
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  sr |= SPR_SR_ICE;
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  asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
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  asm("l.nop");
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  asm("l.nop");
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  asm("l.nop");
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  asm("l.nop");
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  return 0;
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}
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int ic_disable_cmd (int argc, char *argv[])
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{
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  unsigned long sr;
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  if (argc) return -1;
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  /* Disable IC */
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  asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
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  sr &= ~SPR_SR_ICE;
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  asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
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  asm("l.nop");
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  asm("l.nop");
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  asm("l.nop");
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  asm("l.nop");
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  return 0;
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}
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int dc_enable_cmd (int argc, char *argv[])
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{
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  unsigned long addr;
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  unsigned long sr;
46 
 
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  if (argc) return -1;
48 
  /* Invalidate DC */
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  for (addr = 0; addr < 8192; addr += 16)
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    asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_DCBIR));
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  /* Enable DC */
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  asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
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  sr |= SPR_SR_DCE;
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  asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
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  asm("l.nop");
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  asm("l.nop");
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  asm("l.nop");
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  asm("l.nop");
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  return 0;
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}
62 
 
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int dc_disable_cmd (int argc, char *argv[])
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{
65 
 
66 
  if (argc) return -1;
67 246 julius 
 
68 
  unsigned long sr = mfspr(SPR_SR);
69 
 
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  // If it's enabled and write back is on, we'd better flush it first
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  // (CWS=1 is write back)
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  unsigned long dccfgr = mfspr(SPR_DCCFGR);
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  int i;
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  int bs= (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
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  int ways = (1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3));
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  for(i=0;i<ways;i++)
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      mtspr(SPR_DCBFR, i*bs);
79 
 
80 2 marcus.erl 
  /* Disable DC */
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  sr &= ~SPR_SR_DCE;
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  asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
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  asm("l.nop");
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  asm("l.nop");
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  asm("l.nop");
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  asm("l.nop");
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  return 0;
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}
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int mfspr_cmd (int argc, char *argv[])
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{
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  unsigned long val, addr;
93 
 
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  if (argc ==   1) {
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    addr = strtoul (argv[0], 0, 0);
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    /* Read SPR */
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    asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
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    printf ("\nSPR %04lx: %08lx", addr, val);
99 
  } else return -1;
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        return 0;
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}
102 
 
103 
int mtspr_cmd (int argc, char *argv[])
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{
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  unsigned long val, addr;
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  if (argc == 2) {
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    addr = strtoul (argv[0], 0, 0);
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    val = strtoul (argv[1], 0, 0);
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    /* Write SPR */
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    asm("l.mtspr %0,%1,0": : "r" (addr), "r" (val));
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    asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
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    printf ("\nSPR %04lx: %08lx", addr, val);
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  } else return -1;
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        return 0;
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}
116 
 
117 
void module_cpu_init (void)
118 
{
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  register_command ("ic_enable", "", "enable instruction cache", ic_enable_cmd);
120 
  register_command ("ic_disable", "", "disable instruction cache", ic_disable_cmd);
121 
  register_command ("dc_enable", "", "enable data cache", dc_enable_cmd);
122 
  register_command ("dc_disable", "", "disable data cache", dc_disable_cmd);
123 
  register_command ("mfspr", "<spr_addr>", "show SPR", mfspr_cmd);
124 
  register_command ("mtspr", "<spr_addr> <value>", "set SPR", mtspr_cmd);
125 
}

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