URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [cmds/] [cpu.c] - Blame information for rev 607

Go to most recent revision | Details | Compare with Previous | View Log


#include "common.h"
#include "support.h"
#include "spr-defs.h"
 
int ic_enable_cmd(int argc, char *argv[])
{
        unsigned long addr;
        unsigned long sr;
 
        if (argc)
                return -1;
        /* Invalidate IC */
        for (addr = 0; addr < 8192; addr += 16)
asm("l.mtspr r0,%0,%1": :"r"(addr), "i"(SPR_ICBIR));
 
        /* Enable IC */
asm("l.mfspr %0,r0,%1": "=r"(sr):"i"(SPR_SR));
        sr |= SPR_SR_ICE;
asm("l.mtspr r0,%0,%1": :"r"(sr), "i"(SPR_SR));
        asm("l.nop");
        asm("l.nop");
        asm("l.nop");
        asm("l.nop");
        return 0;
}
 
int ic_disable_cmd(int argc, char *argv[])
{
        unsigned long sr;
 
        if (argc)
                return -1;
        /* Disable IC */
asm("l.mfspr %0,r0,%1": "=r"(sr):"i"(SPR_SR));
        sr &= ~SPR_SR_ICE;
asm("l.mtspr r0,%0,%1": :"r"(sr), "i"(SPR_SR));
        asm("l.nop");
        asm("l.nop");
        asm("l.nop");
        asm("l.nop");
        return 0;
}
 
int dc_enable_cmd(int argc, char *argv[])
{
        unsigned long addr;
        unsigned long sr;
 
        if (argc)
                return -1;
        /* Invalidate DC */
        for (addr = 0; addr < 8192; addr += 16)
asm("l.mtspr r0,%0,%1": :"r"(addr), "i"(SPR_DCBIR));
 
        /* Enable DC */
asm("l.mfspr %0,r0,%1": "=r"(sr):"i"(SPR_SR));
        sr |= SPR_SR_DCE;
asm("l.mtspr r0,%0,%1": :"r"(sr), "i"(SPR_SR));
        asm("l.nop");
        asm("l.nop");
        asm("l.nop");
        asm("l.nop");
        return 0;
}
 
int dc_disable_cmd(int argc, char *argv[])
{
 
        if (argc)
                return -1;
 
        unsigned long sr = mfspr(SPR_SR);
 
        // If it's enabled and write back is on, we'd better flush it first
        // (CWS=1 is write back)
 
        unsigned long dccfgr = mfspr(SPR_DCCFGR);
        int i;
        int bs = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
        int ways = (1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3));
        for (i = 0; i < ways; i++)
                mtspr(SPR_DCBFR, i * bs);
 
        /* Disable DC */
        sr &= ~SPR_SR_DCE;
asm("l.mtspr r0,%0,%1": :"r"(sr), "i"(SPR_SR));
        asm("l.nop");
        asm("l.nop");
        asm("l.nop");
        asm("l.nop");
        return 0;
}
 
int mfspr_cmd(int argc, char *argv[])
{
        unsigned long val, addr;
 
        if (argc == 1) {
                addr = strtoul(argv[0], 0, 0);
                /* Read SPR */
asm("l.mfspr %0,%1,0": "=r"(val):"r"(addr));
                printf("\nSPR %04lx: %08lx", addr, val);
        } else
                return -1;
        return 0;
}
 
int mtspr_cmd(int argc, char *argv[])
{
        unsigned long val, addr;
        if (argc == 2) {
                addr = strtoul(argv[0], 0, 0);
                val = strtoul(argv[1], 0, 0);
                /* Write SPR */
asm("l.mtspr %0,%1,0": :"r"(addr), "r"(val));
asm("l.mfspr %0,%1,0": "=r"(val):"r"(addr));
                printf("\nSPR %04lx: %08lx", addr, val);
        } else
                return -1;
        return 0;
}
 
void module_cpu_init(void)
{
        register_command("ic_enable", "", "enable instruction cache",
                         ic_enable_cmd);
        register_command("ic_disable", "", "disable instruction cache",
                         ic_disable_cmd);
        register_command("dc_enable", "", "enable data cache", dc_enable_cmd);
        register_command("dc_disable", "", "disable data cache",
                         dc_disable_cmd);
        register_command("mfspr", "<spr_addr>", "show SPR", mfspr_cmd);
        register_command("mtspr", "<spr_addr> <value>", "set SPR", mtspr_cmd);
}

Line No.	Rev	Author	Line
1	2	marcus.erl	`#include "common.h"`
2			`#include "support.h"`
3	246	julius	`#include "spr-defs.h"`
4	2	marcus.erl
5	406	julius	`int ic_enable_cmd(int argc, char *argv[])`
6	2	marcus.erl	`{`
7	406	julius	`unsigned long addr;`
8			`unsigned long sr;`
9	2	marcus.erl
10	406	julius	`if (argc)`
11			`return -1;`
12			`/* Invalidate IC */`
13			`for (addr = 0; addr < 8192; addr += 16)`
14			`asm("l.mtspr r0,%0,%1": :"r"(addr), "i"(SPR_ICBIR));`
15
16			`/* Enable IC */`
17			`asm("l.mfspr %0,r0,%1": "=r"(sr):"i"(SPR_SR));`
18			`sr \|= SPR_SR_ICE;`
19			`asm("l.mtspr r0,%0,%1": :"r"(sr), "i"(SPR_SR));`
20			`asm("l.nop");`
21			`asm("l.nop");`
22			`asm("l.nop");`
23			`asm("l.nop");`
24			`return 0;`
25	2	marcus.erl	`}`
26
27	406	julius	`int ic_disable_cmd(int argc, char *argv[])`
28	2	marcus.erl	`{`
29	406	julius	`unsigned long sr;`
30	2	marcus.erl
31	406	julius	`if (argc)`
32			`return -1;`
33			`/* Disable IC */`
34			`asm("l.mfspr %0,r0,%1": "=r"(sr):"i"(SPR_SR));`
35			`sr &= ~SPR_SR_ICE;`
36			`asm("l.mtspr r0,%0,%1": :"r"(sr), "i"(SPR_SR));`
37			`asm("l.nop");`
38			`asm("l.nop");`
39			`asm("l.nop");`
40			`asm("l.nop");`
41			`return 0;`
42	2	marcus.erl	`}`
43
44	406	julius	`int dc_enable_cmd(int argc, char *argv[])`
45	2	marcus.erl	`{`
46	406	julius	`unsigned long addr;`
47			`unsigned long sr;`
48	2	marcus.erl
49	406	julius	`if (argc)`
50			`return -1;`
51			`/* Invalidate DC */`
52			`for (addr = 0; addr < 8192; addr += 16)`
53			`asm("l.mtspr r0,%0,%1": :"r"(addr), "i"(SPR_DCBIR));`
54
55			`/* Enable DC */`
56			`asm("l.mfspr %0,r0,%1": "=r"(sr):"i"(SPR_SR));`
57			`sr \|= SPR_SR_DCE;`
58			`asm("l.mtspr r0,%0,%1": :"r"(sr), "i"(SPR_SR));`
59			`asm("l.nop");`
60			`asm("l.nop");`
61			`asm("l.nop");`
62			`asm("l.nop");`
63			`return 0;`
64	2	marcus.erl	`}`
65
66	406	julius	`int dc_disable_cmd(int argc, char *argv[])`
67	2	marcus.erl	`{`
68
69	406	julius	`if (argc)`
70			`return -1;`
71	246	julius
72	406	julius	`unsigned long sr = mfspr(SPR_SR);`
73	246	julius
74	406	julius	`// If it's enabled and write back is on, we'd better flush it first`
75			`// (CWS=1 is write back)`
76	246	julius
77	406	julius	`unsigned long dccfgr = mfspr(SPR_DCCFGR);`
78			`int i;`
79			`int bs = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;`
80			`int ways = (1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3));`
81			`for (i = 0; i < ways; i++)`
82			`mtspr(SPR_DCBFR, i * bs);`
83
84			`/* Disable DC */`
85			`sr &= ~SPR_SR_DCE;`
86			`asm("l.mtspr r0,%0,%1": :"r"(sr), "i"(SPR_SR));`
87			`asm("l.nop");`
88			`asm("l.nop");`
89			`asm("l.nop");`
90			`asm("l.nop");`
91			`return 0;`
92	2	marcus.erl	`}`
93
94	406	julius	`int mfspr_cmd(int argc, char *argv[])`
95	2	marcus.erl	`{`
96	406	julius	`unsigned long val, addr;`
97	2	marcus.erl
98	406	julius	`if (argc == 1) {`
99			`addr = strtoul(argv[0], 0, 0);`
100			`/* Read SPR */`
101			`asm("l.mfspr %0,%1,0": "=r"(val):"r"(addr));`
102			`printf("\nSPR %04lx: %08lx", addr, val);`
103			`} else`
104			`return -1;`
105	2	marcus.erl	`return 0;`
106			`}`
107
108	406	julius	`int mtspr_cmd(int argc, char *argv[])`
109	2	marcus.erl	`{`
110	406	julius	`unsigned long val, addr;`
111			`if (argc == 2) {`
112			`addr = strtoul(argv[0], 0, 0);`
113			`val = strtoul(argv[1], 0, 0);`
114			`/* Write SPR */`
115			`asm("l.mtspr %0,%1,0": :"r"(addr), "r"(val));`
116			`asm("l.mfspr %0,%1,0": "=r"(val):"r"(addr));`
117			`printf("\nSPR %04lx: %08lx", addr, val);`
118			`} else`
119			`return -1;`
120	2	marcus.erl	`return 0;`
121			`}`
122
123	406	julius	`void module_cpu_init(void)`
124	2	marcus.erl	`{`
125	406	julius	`register_command("ic_enable", "", "enable instruction cache",`
126			`ic_enable_cmd);`
127			`register_command("ic_disable", "", "disable instruction cache",`
128			`ic_disable_cmd);`
129			`register_command("dc_enable", "", "enable data cache", dc_enable_cmd);`
130			`register_command("dc_disable", "", "disable data cache",`
131			`dc_disable_cmd);`
132			`register_command("mfspr", "<spr_addr>", "show SPR", mfspr_cmd);`
133			`register_command("mtspr", "<spr_addr> <value>", "set SPR", mtspr_cmd);`
134	2	marcus.erl	`}`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [cmds/] [cpu.c] - Blame information for rev 607