URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [cmds/] [eth.c] - Blame information for rev 246

Go to most recent revision | Details | Compare with Previous | View Log


#include "common.h"
#include "uart.h"
#include "eth.h"
#include "support.h"
#include "spr-defs.h"
#include "net.h"
 
#if 1
extern int tx_pointer_index;
unsigned long dest_mac_addr[6];
 
 
void show_tx_bd(int start, int max)
{
  int i;
 
  for(i = start; i <= max; i++) {
    /* Read Tx BD */
    printf ("LEN:%04lx", REG32(ETH_BD_BASE + (i << 3)) >> 16);
    printf (" RD:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 15) & 0x1);
    printf (" IRQ:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 14) & 0x1);
    printf (" WR:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 13) & 0x1);
    printf (" PAD:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 12) & 0x1);
    printf (" CRC:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 11) & 0x1);
    printf (" UR:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 8) & 0x1);
    printf (" RTRY:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 4) & 0xf);
    printf (" RL:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 3) & 0x1);
    printf (" LC:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 2) & 0x1);
    printf (" DF:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 1) & 0x1);
    printf (" CS:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 0) & 0x1);
    printf ("\nTx Buffer Pointer: %08lx\n", REG32(ETH_BD_BASE + (i << 3) + 4));
  }
}
 
void show_rx_bd (int start, int max)
{
  int i;
  unsigned long rx_bd_base, rx_bd_num;
 
  rx_bd_num =  REG32(ETH_REG_BASE + ETH_RXBD_NUM);
  rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);
 
  for(i = start; i <= max; i++){
    /* Read Rx BD */
    printf ("LEN:%04lx", REG32(rx_bd_base + (i << 3)) >> 16);
    printf (" E:%04lx", (REG32(rx_bd_base + (i << 3)) >> 15) & 0x1);
    printf (" IRQ:%04lx", (REG32(rx_bd_base + (i << 3)) >> 14) & 0x1);
    printf (" WR:%04lx", (REG32(rx_bd_base + (i << 3)) >> 13) & 0x1);
    printf (" M:%04lx", (REG32(rx_bd_base + (i << 3)) >> 7) & 0x1);
    printf (" OR:%04lx", (REG32(rx_bd_base + (i << 3)) >> 6) & 0x1);
    printf (" IS:%04lx", (REG32(rx_bd_base + (i << 3)) >> 5) & 0x1);
    printf (" DN:%04lx", (REG32(rx_bd_base + (i << 3)) >> 4) & 0x1);
    printf (" TL:%04lx", (REG32(rx_bd_base + (i << 3)) >> 3) & 0x1);
    printf (" SF:%04lx", (REG32(rx_bd_base + (i << 3)) >> 2) & 0x1);
    printf (" CRC:%04lx", (REG32(rx_bd_base + (i << 3)) >> 1) & 0x1);
    printf (" LC:%04lx", (REG32(rx_bd_base + (i << 3)) >> 0) & 0x1);
    printf ("\nRx Buffer Pointer: %08lx\n", REG32(rx_bd_base + (i << 3) + 4));
  }
}
 
void show_buffer(unsigned long start_addr, unsigned long len)
{
  show_mem(start_addr, start_addr + len - 1);
}
 
void show_rx_buffs(int max, int show_all)
{
 
  int i;
  unsigned long rx_bd_base, rx_bd_num;
 
  rx_bd_num =  REG32(ETH_REG_BASE + ETH_RXBD_NUM);
  rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);
 
  for(i=0; i<=max; i++)
  {
    if (!(REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_EMPTY) || show_all)
    {
      printf ("Rx BD No. %04x located at %08lx\n", i, rx_bd_base + (i << 3));
      show_rx_bd(i, i);
      show_buffer(REG32(rx_bd_base + (i << 3) + 4), REG32(rx_bd_base + (i << 3)) >> 16);
      printf ("\n");
    }
    if (REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_WRAP)
      return;
  }
}
 
void show_tx_buffs(int max)
{
  int i;
 
  for(i=0; i<=max; i++)
  {
    if (1)
    {
      printf ("Tx BD No. %04x located at %08x\n", i, ETH_BD_BASE + (i << 3));
      show_tx_bd(i, i);
      show_buffer(REG32(ETH_BD_BASE + (i << 3) + 4), REG32(ETH_BD_BASE + (i << 3)) >> 16);
      printf ("\n");
    }
    if (REG32(ETH_BD_BASE + (i << 3)) & ETH_TX_BD_WRAP)
      return;
  }
}
 
void show_phy_reg (unsigned long start_addr, unsigned long stop_addr)
{
 
  unsigned long addr;
 
  if (start_addr == stop_addr)
  {
    printf ("\nSet MII RGAD ADDRESS to %08lx", start_addr);
    printf ("\nMII Command = Read Status\n");
  }
 
  for (addr = start_addr; addr <= stop_addr; addr++)
  {
    REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;
    REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_RSTAT;
 
    printf ("PHY %04lx", REG32(ETH_REG_BASE + ETH_MIIADDRESS) & 0x1f);
    printf (", addr %04lx", REG32(ETH_REG_BASE + ETH_MIIADDRESS) >> 8);
    printf (": %08lx\n", REG32(ETH_REG_BASE + ETH_MIIRX_DATA));
  }
}
 
void set_phy_reg (unsigned long addr, unsigned long val)
{
  printf ("\nSet MII RGAD ADDRESS to %08lx", addr);
 
  REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;
 
  printf ("\nMII Command = Write Control Data\n");
  REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_WCTRLDATA;
 
  REG32(ETH_REG_BASE + ETH_MIITX_DATA) = val;
 
  show_phy_reg(addr, addr);
}
 
void send_packet (unsigned long len, unsigned long start_data, int num_of_packets)
{
  unsigned long i, TxBD;
 
  while (num_of_packets--) {
    unsigned long *data = (unsigned long *)eth_get_tx_buf ();
 
    /* Set dest & src address */
    *data++ = dest_mac_addr[0] << 24 |
              dest_mac_addr[1] << 16 |
              dest_mac_addr[2] << 8  |
              dest_mac_addr[3] << 0;
 
    *data++ = dest_mac_addr[4] << 24 |
              dest_mac_addr[5] << 16 |
              ETH_MACADDR0     << 8  |
              ETH_MACADDR1     << 0;
 
    *data++ = ETH_MACADDR2     << 24 |
              ETH_MACADDR3     << 16 |
              ETH_MACADDR4     << 8  |
              ETH_MACADDR5     << 0;
 
    /* Write data to buffer */
    for(i = 12; i < len; i += 4)
      *data++ = (i + start_data - 12) << 24 | (i + start_data + 1 - 12) << 16 |
                (i + start_data + 2 - 12) << 8 | (i + start_data + 3 - 12);
 
    eth_send (data, len);
    printf (".");
  }
}
 
int eth_init_cmd (int argc, char *argv[])
{
  if (argc) return -1;
  eth_init (0);
  return 0;
}
 
int show_txbd_cmd (int argc, char *argv[])
{
  int i;
  int start, max;
 
  if (argc == 1) show_tx_bd (strtoul (argv[0], NULL, 0), strtoul (argv[0], NULL, 0));
  else if (argc == 2) show_tx_bd (strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0));
  else show_tx_bd (0, 63);
  return 0;
}
 
int show_rxbd_cmd (int argc, char *argv[])
{
  if (argc == 1) show_rx_bd (strtoul (argv[0], NULL, 0), strtoul (argv[0], NULL, 0));
  else if (argc == 2) show_rx_bd (strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0));
  else show_rx_bd (0, 63);
  return 0;
}
 
int send_packet_cmd (int argc, char *argv[])
{
  if (argc == 1) send_packet(strtoul (argv[0], NULL, 0), 31, 1);
  else if (argc == 2) send_packet(strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0), 1);
  else if (argc == 3) send_packet(strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0), strtoul (argv[2], NULL, 0));
  else return -1;
  return 0;
}
 
int set_dest_addr_cmd (int argc, char *argv[])
{
  if (argc == 3) {
    dest_mac_addr[0] = (strtoul (argv[0], NULL, 0) >> 8) & 0xff;
    dest_mac_addr[1] = (strtoul (argv[0], NULL, 0) >> 0) & 0xff;
    dest_mac_addr[2] = (strtoul (argv[1], NULL, 0) >> 8) & 0xff;
    dest_mac_addr[3] = (strtoul (argv[1], NULL, 0) >> 0) & 0xff;
    dest_mac_addr[4] = (strtoul (argv[2], NULL, 0) >> 8) & 0xff;
    dest_mac_addr[5] = (strtoul (argv[2], NULL, 0) >> 0) & 0xff;
  } else return -1;
  return 0;
}
 
int init_txbd_pool_cmd (int argc, char *argv[])
{
#if 0
  if (argc == 1) init_tx_bd_pool(strtoul (argv[0], NULL, 0));
  else return -1;
#endif
  return 0;
}
 
int init_rxbd_pool_cmd (int argc, char *argv[])
{
  //if (argc == 1) init_rx_bd_pool(strtoul (argv[0], NULL, 0));
  //else return -1;
  init_rx_bd_pool();
 
  return 0;
}
 
int show_phy_reg_cmd (int argc, char *argv[])
{
  if (argc == 1) show_phy_reg(strtoul (argv[0], NULL, 0), strtoul (argv[0], NULL, 0));
  else if (argc == 2) show_phy_reg(strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0));
  else show_phy_reg(0, 30);
  return 0;
}
 
int set_phy_reg_cmd (int argc, char *argv[])
{
  if (argc == 2) set_phy_reg(strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0));
  else return -1;
  return 0;
}
 
int show_mac_regs_cmd (int argc, char *argv[])
{
  if (argc) return -1;
  printf ("\n %08x", ETH_REG_BASE + ETH_MODER);
  printf (" MODER: %08lx",REG32(ETH_REG_BASE + ETH_MODER));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_INT);
  printf (" INT: %08lx", REG32(ETH_REG_BASE + ETH_INT));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_INT_MASK);
  printf (" INT_MASK: %08lx", REG32(ETH_REG_BASE + ETH_INT_MASK));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_IPGT);
  printf (" IPGT: %08lx", REG32(ETH_REG_BASE + ETH_IPGT));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_IPGR1);
  printf (" IPGR1: %08lx", REG32(ETH_REG_BASE + ETH_IPGR1));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_IPGR2);
  printf (" IPGR2: %08lx", REG32(ETH_REG_BASE + ETH_IPGR2));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_PACKETLEN);
  printf (" PACKETLEN: %08lx", REG32(ETH_REG_BASE + ETH_PACKETLEN));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_COLLCONF);
  printf (" COLLCONF: %08lx", REG32(ETH_REG_BASE + ETH_COLLCONF));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_RXBD_NUM);
  printf (" RX_BD_NUM: %08lx", REG32(ETH_REG_BASE + ETH_RXBD_NUM));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_CTRLMODER);
  printf (" CTRLMODER: %08lx", REG32(ETH_REG_BASE + ETH_CTRLMODER));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIIMODER);
  printf (" MIIMODER: %08lx", REG32(ETH_REG_BASE + ETH_MIIMODER));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIICOMMAND);
  printf (" MIICOMMAND: %08lx", REG32(ETH_REG_BASE + ETH_MIICOMMAND));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIIADDRESS);
  printf (" MIIADDRESS: %08lx", REG32(ETH_REG_BASE + ETH_MIIADDRESS));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIITX_DATA);
  printf (" MIITX_DATA: %08lx", REG32(ETH_REG_BASE + ETH_MIITX_DATA));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIIRX_DATA);
  printf (" MIIRX_DATA: %08lx", REG32(ETH_REG_BASE + ETH_MIIRX_DATA));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIISTATUS);
  printf (" MIISTATUS: %08lx", REG32(ETH_REG_BASE + ETH_MIISTATUS));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MAC_ADDR0);
  printf (" MAC_ADDR0: %08lx", REG32(ETH_REG_BASE + ETH_MAC_ADDR0));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MAC_ADDR1);
  printf (" MAC_ADDR1: %08lx", REG32(ETH_REG_BASE + ETH_MAC_ADDR1));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_HASH_ADDR0);
  printf (" ETH_HASH_ADDR0: %08lx", REG32(ETH_REG_BASE + ETH_HASH_ADDR0));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_HASH_ADDR1);
  printf (" ETH_HASH_ADDR1: %08lx", REG32(ETH_REG_BASE + ETH_HASH_ADDR1));
 
  printf ("\n");
  return 0;
}
 
int eth_int_enable_cmd (int argc, char *argv[])
{
  if (argc) return -1;
  eth_int_enable ();
  return 0;
}
int show_rx_buffs_cmd (int argc, char *argv[])
{
  if (argc == 0) show_rx_buffs(63, 0);
  else if (argc == 1) show_rx_buffs(63, 1);
  else return -1;
  return 0;
}
 
int show_tx_buffs_cmd (int argc, char *argv[])
{
  if (argc == 0) show_tx_buffs(63);
  else return -1;
  return 0;
}
#endif
 
int eth_conf_cmd(int argc, char *argv[])
{
  switch(argc) {
  case 0:
    printf("IP: %s", inet_ntoa(global.ip));
    printf("\nmask: %s", inet_ntoa(global.mask));
    printf("\nGW: %s", inet_ntoa(global.gw_ip));
    return 0;
  case 3:
    global.gw_ip = inet_aton(argv[2]);
  case 2:
    global.mask = inet_aton(argv[1]);
  case 1:
    global.ip = inet_aton(argv[0]);
    break;
  }
  printf("Restarting network with new parameters...");
  NetStartAgain();
 
  return 0;
}
 
void toggle_eth_traffic_monitor_cmd(void)
{
  eth_toggle_traffic_mon();
}
 
 
void module_eth_init (void)
{
#if 1
  register_command ("eth_init", "",  "init ethernet", eth_init_cmd);
  register_command ("show_txbd", "[<start BD>] [<max>]", "show Tx buffer desc", show_txbd_cmd);
  register_command ("show_rxbd", "[<start BD>] [<max>]", "show Rx buffer desc", show_rxbd_cmd);
  register_command ("send_packet", "<length> [<start data>] [<num_of_packets>]", "create & send packet(s)", send_packet_cmd);
  register_command ("set_dest_addr", "<addrhi> <addrmid> <addrlo>", "set destination address (for send_packet)", set_dest_addr_cmd);
  register_command ("init_txbd_pool", "<max>", "initialize Tx buffer descriptors", init_txbd_pool_cmd);
  register_command ("init_rxbd_pool", "<max>", "initialize Rx buffer descriptors", init_rxbd_pool_cmd);
  register_command ("show_phy_reg", "[<start_addr>] [<end addr>]", "show PHY registers", show_phy_reg_cmd);
  register_command ("set_phy_reg", "<addr> <value>", "set PHY register", set_phy_reg_cmd);
  register_command ("show_mac_regs", "", "show all MAC registers", show_mac_regs_cmd);
  register_command ("eth_int_enable", "", "enable ethernet interrupt", eth_int_enable_cmd);
  register_command ("show_rx_buffs", "[<show_all>]", "show receive buffers (optional arg will also show empty buffers)", show_rx_buffs_cmd);
  register_command ("show_tx_buffs", "", "show transmit buffers", show_rx_buffs_cmd);
  register_command ("eth_toggle_mon", "", "Toggle traffic monitor", toggle_eth_traffic_monitor_cmd );
#endif
  /* Initialize controller */
  register_command ("eth_conf", "[<ip> [<mask> [<gw>]]]", "Get/set ethernet configuration", eth_conf_cmd);
#if 0
  eth_init();
  printf ("Ethernet not initialized (run eth_init command)\n");
  init_rx_bd_pool(0);
  init_tx_bd_pool(3);
#endif
}
 

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [cmds/] [eth.c] - Blame information for rev 246

Line No.	Rev	Author	Line
1	2	marcus.erl	`#include "common.h"`
2			`#include "uart.h"`
3			`#include "eth.h"`
4			`#include "support.h"`
5	246	julius	`#include "spr-defs.h"`
6	2	marcus.erl	`#include "net.h"`
7
8	140	julius	`#if 1`
9	2	marcus.erl	`extern int tx_pointer_index;`
10			`unsigned long dest_mac_addr[6];`
11
12	140	julius
13	2	marcus.erl	`void show_tx_bd(int start, int max)`
14			`{`
15			`int i;`
16
17			`for(i = start; i <= max; i++) {`
18			`/* Read Tx BD */`
19			`printf ("LEN:%04lx", REG32(ETH_BD_BASE + (i << 3)) >> 16);`
20			`printf (" RD:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 15) & 0x1);`
21			`printf (" IRQ:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 14) & 0x1);`
22			`printf (" WR:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 13) & 0x1);`
23			`printf (" PAD:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 12) & 0x1);`
24			`printf (" CRC:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 11) & 0x1);`
25			`printf (" UR:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 8) & 0x1);`
26			`printf (" RTRY:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 4) & 0xf);`
27			`printf (" RL:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 3) & 0x1);`
28			`printf (" LC:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 2) & 0x1);`
29			`printf (" DF:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 1) & 0x1);`
30			`printf (" CS:%04lx", (REG32(ETH_BD_BASE + (i << 3)) >> 0) & 0x1);`
31			`printf ("\nTx Buffer Pointer: %08lx\n", REG32(ETH_BD_BASE + (i << 3) + 4));`
32			`}`
33			`}`
34
35			`void show_rx_bd (int start, int max)`
36			`{`
37			`int i;`
38			`unsigned long rx_bd_base, rx_bd_num;`
39
40			`rx_bd_num = REG32(ETH_REG_BASE + ETH_RXBD_NUM);`
41			`rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);`
42
43			`for(i = start; i <= max; i++){`
44			`/* Read Rx BD */`
45			`printf ("LEN:%04lx", REG32(rx_bd_base + (i << 3)) >> 16);`
46			`printf (" E:%04lx", (REG32(rx_bd_base + (i << 3)) >> 15) & 0x1);`
47			`printf (" IRQ:%04lx", (REG32(rx_bd_base + (i << 3)) >> 14) & 0x1);`
48			`printf (" WR:%04lx", (REG32(rx_bd_base + (i << 3)) >> 13) & 0x1);`
49			`printf (" M:%04lx", (REG32(rx_bd_base + (i << 3)) >> 7) & 0x1);`
50			`printf (" OR:%04lx", (REG32(rx_bd_base + (i << 3)) >> 6) & 0x1);`
51			`printf (" IS:%04lx", (REG32(rx_bd_base + (i << 3)) >> 5) & 0x1);`
52			`printf (" DN:%04lx", (REG32(rx_bd_base + (i << 3)) >> 4) & 0x1);`
53			`printf (" TL:%04lx", (REG32(rx_bd_base + (i << 3)) >> 3) & 0x1);`
54			`printf (" SF:%04lx", (REG32(rx_bd_base + (i << 3)) >> 2) & 0x1);`
55			`printf (" CRC:%04lx", (REG32(rx_bd_base + (i << 3)) >> 1) & 0x1);`
56			`printf (" LC:%04lx", (REG32(rx_bd_base + (i << 3)) >> 0) & 0x1);`
57			`printf ("\nRx Buffer Pointer: %08lx\n", REG32(rx_bd_base + (i << 3) + 4));`
58			`}`
59			`}`
60
61			`void show_buffer(unsigned long start_addr, unsigned long len)`
62			`{`
63			`show_mem(start_addr, start_addr + len - 1);`
64			`}`
65
66			`void show_rx_buffs(int max, int show_all)`
67			`{`
68
69			`int i;`
70			`unsigned long rx_bd_base, rx_bd_num;`
71
72			`rx_bd_num = REG32(ETH_REG_BASE + ETH_RXBD_NUM);`
73			`rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);`
74
75			`for(i=0; i<=max; i++)`
76			`{`
77			`if (!(REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_EMPTY) \|\| show_all)`
78			`{`
79			`printf ("Rx BD No. %04x located at %08lx\n", i, rx_bd_base + (i << 3));`
80			`show_rx_bd(i, i);`
81			`show_buffer(REG32(rx_bd_base + (i << 3) + 4), REG32(rx_bd_base + (i << 3)) >> 16);`
82			`printf ("\n");`
83			`}`
84			`if (REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_WRAP)`
85			`return;`
86			`}`
87			`}`
88
89			`void show_tx_buffs(int max)`
90			`{`
91			`int i;`
92
93			`for(i=0; i<=max; i++)`
94			`{`
95			`if (1)`
96			`{`
97			`printf ("Tx BD No. %04x located at %08x\n", i, ETH_BD_BASE + (i << 3));`
98			`show_tx_bd(i, i);`
99			`show_buffer(REG32(ETH_BD_BASE + (i << 3) + 4), REG32(ETH_BD_BASE + (i << 3)) >> 16);`
100			`printf ("\n");`
101			`}`
102			`if (REG32(ETH_BD_BASE + (i << 3)) & ETH_TX_BD_WRAP)`
103			`return;`
104			`}`
105			`}`
106
107			`void show_phy_reg (unsigned long start_addr, unsigned long stop_addr)`
108			`{`
109
110			`unsigned long addr;`
111
112			`if (start_addr == stop_addr)`
113			`{`
114			`printf ("\nSet MII RGAD ADDRESS to %08lx", start_addr);`
115			`printf ("\nMII Command = Read Status\n");`
116			`}`
117
118			`for (addr = start_addr; addr <= stop_addr; addr++)`
119			`{`
120			`REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;`
121			`REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_RSTAT;`
122
123			`printf ("PHY %04lx", REG32(ETH_REG_BASE + ETH_MIIADDRESS) & 0x1f);`
124			`printf (", addr %04lx", REG32(ETH_REG_BASE + ETH_MIIADDRESS) >> 8);`
125			`printf (": %08lx\n", REG32(ETH_REG_BASE + ETH_MIIRX_DATA));`
126			`}`
127			`}`
128
129			`void set_phy_reg (unsigned long addr, unsigned long val)`
130			`{`
131			`printf ("\nSet MII RGAD ADDRESS to %08lx", addr);`
132
133			`REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;`
134
135			`printf ("\nMII Command = Write Control Data\n");`
136			`REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_WCTRLDATA;`
137
138			`REG32(ETH_REG_BASE + ETH_MIITX_DATA) = val;`
139
140			`show_phy_reg(addr, addr);`
141			`}`
142
143			`void send_packet (unsigned long len, unsigned long start_data, int num_of_packets)`
144			`{`
145			`unsigned long i, TxBD;`
146
147			`while (num_of_packets--) {`
148			`unsigned long data = (unsigned long )eth_get_tx_buf ();`
149
150			`/* Set dest & src address */`
151			`*data++ = dest_mac_addr[0] << 24 \|`
152			`dest_mac_addr[1] << 16 \|`
153			`dest_mac_addr[2] << 8 \|`
154			`dest_mac_addr[3] << 0;`
155
156			`*data++ = dest_mac_addr[4] << 24 \|`
157			`dest_mac_addr[5] << 16 \|`
158			`ETH_MACADDR0 << 8 \|`
159			`ETH_MACADDR1 << 0;`
160
161			`*data++ = ETH_MACADDR2 << 24 \|`
162			`ETH_MACADDR3 << 16 \|`
163			`ETH_MACADDR4 << 8 \|`
164			`ETH_MACADDR5 << 0;`
165
166			`/* Write data to buffer */`
167			`for(i = 12; i < len; i += 4)`
168			`*data++ = (i + start_data - 12) << 24 \| (i + start_data + 1 - 12) << 16 \|`
169			`(i + start_data + 2 - 12) << 8 \| (i + start_data + 3 - 12);`
170
171			`eth_send (data, len);`
172			`printf (".");`
173			`}`
174			`}`
175
176			`int eth_init_cmd (int argc, char *argv[])`
177			`{`
178			`if (argc) return -1;`
179			`eth_init (0);`
180			`return 0;`
181			`}`
182
183			`int show_txbd_cmd (int argc, char *argv[])`
184			`{`
185			`int i;`
186			`int start, max;`
187
188			`if (argc == 1) show_tx_bd (strtoul (argv[0], NULL, 0), strtoul (argv[0], NULL, 0));`
189			`else if (argc == 2) show_tx_bd (strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0));`
190			`else show_tx_bd (0, 63);`
191			`return 0;`
192			`}`
193
194			`int show_rxbd_cmd (int argc, char *argv[])`
195			`{`
196			`if (argc == 1) show_rx_bd (strtoul (argv[0], NULL, 0), strtoul (argv[0], NULL, 0));`
197			`else if (argc == 2) show_rx_bd (strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0));`
198			`else show_rx_bd (0, 63);`
199			`return 0;`
200			`}`
201
202			`int send_packet_cmd (int argc, char *argv[])`
203			`{`
204			`if (argc == 1) send_packet(strtoul (argv[0], NULL, 0), 31, 1);`
205			`else if (argc == 2) send_packet(strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0), 1);`
206			`else if (argc == 3) send_packet(strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0), strtoul (argv[2], NULL, 0));`
207			`else return -1;`
208			`return 0;`
209			`}`
210
211			`int set_dest_addr_cmd (int argc, char *argv[])`
212			`{`
213			`if (argc == 3) {`
214			`dest_mac_addr[0] = (strtoul (argv[0], NULL, 0) >> 8) & 0xff;`
215			`dest_mac_addr[1] = (strtoul (argv[0], NULL, 0) >> 0) & 0xff;`
216			`dest_mac_addr[2] = (strtoul (argv[1], NULL, 0) >> 8) & 0xff;`
217			`dest_mac_addr[3] = (strtoul (argv[1], NULL, 0) >> 0) & 0xff;`
218			`dest_mac_addr[4] = (strtoul (argv[2], NULL, 0) >> 8) & 0xff;`
219			`dest_mac_addr[5] = (strtoul (argv[2], NULL, 0) >> 0) & 0xff;`
220			`} else return -1;`
221			`return 0;`
222			`}`
223
224			`int init_txbd_pool_cmd (int argc, char *argv[])`
225			`{`
226			`#if 0`
227			`if (argc == 1) init_tx_bd_pool(strtoul (argv[0], NULL, 0));`
228			`else return -1;`
229			`#endif`
230			`return 0;`
231			`}`
232
233			`int init_rxbd_pool_cmd (int argc, char *argv[])`
234			`{`
235	140	julius	`//if (argc == 1) init_rx_bd_pool(strtoul (argv[0], NULL, 0));`
236			`//else return -1;`
237			`init_rx_bd_pool();`
238
239	2	marcus.erl	`return 0;`
240			`}`
241
242			`int show_phy_reg_cmd (int argc, char *argv[])`
243			`{`
244			`if (argc == 1) show_phy_reg(strtoul (argv[0], NULL, 0), strtoul (argv[0], NULL, 0));`
245			`else if (argc == 2) show_phy_reg(strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0));`
246			`else show_phy_reg(0, 30);`
247			`return 0;`
248			`}`
249
250			`int set_phy_reg_cmd (int argc, char *argv[])`
251			`{`
252			`if (argc == 2) set_phy_reg(strtoul (argv[0], NULL, 0), strtoul (argv[1], NULL, 0));`
253			`else return -1;`
254			`return 0;`
255			`}`
256
257			`int show_mac_regs_cmd (int argc, char *argv[])`
258			`{`
259			`if (argc) return -1;`
260			`printf ("\n %08x", ETH_REG_BASE + ETH_MODER);`
261			`printf (" MODER: %08lx",REG32(ETH_REG_BASE + ETH_MODER));`
262
263			`printf ("\n %08x", ETH_REG_BASE + ETH_INT);`
264			`printf (" INT: %08lx", REG32(ETH_REG_BASE + ETH_INT));`
265
266			`printf ("\n %08x", ETH_REG_BASE + ETH_INT_MASK);`
267			`printf (" INT_MASK: %08lx", REG32(ETH_REG_BASE + ETH_INT_MASK));`
268
269			`printf ("\n %08x", ETH_REG_BASE + ETH_IPGT);`
270			`printf (" IPGT: %08lx", REG32(ETH_REG_BASE + ETH_IPGT));`
271
272			`printf ("\n %08x", ETH_REG_BASE + ETH_IPGR1);`
273			`printf (" IPGR1: %08lx", REG32(ETH_REG_BASE + ETH_IPGR1));`
274
275			`printf ("\n %08x", ETH_REG_BASE + ETH_IPGR2);`
276			`printf (" IPGR2: %08lx", REG32(ETH_REG_BASE + ETH_IPGR2));`
277
278			`printf ("\n %08x", ETH_REG_BASE + ETH_PACKETLEN);`
279			`printf (" PACKETLEN: %08lx", REG32(ETH_REG_BASE + ETH_PACKETLEN));`
280
281			`printf ("\n %08x", ETH_REG_BASE + ETH_COLLCONF);`
282			`printf (" COLLCONF: %08lx", REG32(ETH_REG_BASE + ETH_COLLCONF));`
283
284			`printf ("\n %08x", ETH_REG_BASE + ETH_RXBD_NUM);`
285			`printf (" RX_BD_NUM: %08lx", REG32(ETH_REG_BASE + ETH_RXBD_NUM));`
286
287			`printf ("\n %08x", ETH_REG_BASE + ETH_CTRLMODER);`
288			`printf (" CTRLMODER: %08lx", REG32(ETH_REG_BASE + ETH_CTRLMODER));`
289
290			`printf ("\n %08x", ETH_REG_BASE + ETH_MIIMODER);`
291			`printf (" MIIMODER: %08lx", REG32(ETH_REG_BASE + ETH_MIIMODER));`
292
293			`printf ("\n %08x", ETH_REG_BASE + ETH_MIICOMMAND);`
294			`printf (" MIICOMMAND: %08lx", REG32(ETH_REG_BASE + ETH_MIICOMMAND));`
295
296			`printf ("\n %08x", ETH_REG_BASE + ETH_MIIADDRESS);`
297			`printf (" MIIADDRESS: %08lx", REG32(ETH_REG_BASE + ETH_MIIADDRESS));`
298
299			`printf ("\n %08x", ETH_REG_BASE + ETH_MIITX_DATA);`
300			`printf (" MIITX_DATA: %08lx", REG32(ETH_REG_BASE + ETH_MIITX_DATA));`
301
302			`printf ("\n %08x", ETH_REG_BASE + ETH_MIIRX_DATA);`
303			`printf (" MIIRX_DATA: %08lx", REG32(ETH_REG_BASE + ETH_MIIRX_DATA));`
304
305			`printf ("\n %08x", ETH_REG_BASE + ETH_MIISTATUS);`
306			`printf (" MIISTATUS: %08lx", REG32(ETH_REG_BASE + ETH_MIISTATUS));`
307
308			`printf ("\n %08x", ETH_REG_BASE + ETH_MAC_ADDR0);`
309			`printf (" MAC_ADDR0: %08lx", REG32(ETH_REG_BASE + ETH_MAC_ADDR0));`
310
311			`printf ("\n %08x", ETH_REG_BASE + ETH_MAC_ADDR1);`
312			`printf (" MAC_ADDR1: %08lx", REG32(ETH_REG_BASE + ETH_MAC_ADDR1));`
313
314			`printf ("\n %08x", ETH_REG_BASE + ETH_HASH_ADDR0);`
315			`printf (" ETH_HASH_ADDR0: %08lx", REG32(ETH_REG_BASE + ETH_HASH_ADDR0));`
316
317			`printf ("\n %08x", ETH_REG_BASE + ETH_HASH_ADDR1);`
318			`printf (" ETH_HASH_ADDR1: %08lx", REG32(ETH_REG_BASE + ETH_HASH_ADDR1));`
319
320			`printf ("\n");`
321			`return 0;`
322			`}`
323
324			`int eth_int_enable_cmd (int argc, char *argv[])`
325			`{`
326			`if (argc) return -1;`
327			`eth_int_enable ();`
328			`return 0;`
329			`}`
330			`int show_rx_buffs_cmd (int argc, char *argv[])`
331			`{`
332			`if (argc == 0) show_rx_buffs(63, 0);`
333			`else if (argc == 1) show_rx_buffs(63, 1);`
334			`else return -1;`
335			`return 0;`
336			`}`
337
338			`int show_tx_buffs_cmd (int argc, char *argv[])`
339			`{`
340			`if (argc == 0) show_tx_buffs(63);`
341			`else return -1;`
342			`return 0;`
343			`}`
344			`#endif`
345
346			`int eth_conf_cmd(int argc, char *argv[])`
347			`{`
348			`switch(argc) {`
349			`case 0:`
350			`printf("IP: %s", inet_ntoa(global.ip));`
351			`printf("\nmask: %s", inet_ntoa(global.mask));`
352			`printf("\nGW: %s", inet_ntoa(global.gw_ip));`
353			`return 0;`
354			`case 3:`
355			`global.gw_ip = inet_aton(argv[2]);`
356			`case 2:`
357			`global.mask = inet_aton(argv[1]);`
358			`case 1:`
359			`global.ip = inet_aton(argv[0]);`
360			`break;`
361			`}`
362			`printf("Restarting network with new parameters...");`
363			`NetStartAgain();`
364
365			`return 0;`
366			`}`
367
368	140	julius	`void toggle_eth_traffic_monitor_cmd(void)`
369			`{`
370			`eth_toggle_traffic_mon();`
371			`}`
372
373
374	2	marcus.erl	`void module_eth_init (void)`
375			`{`
376	140	julius	`#if 1`
377	2	marcus.erl	`register_command ("eth_init", "", "init ethernet", eth_init_cmd);`
378			`register_command ("show_txbd", "[<start BD>] [<max>]", "show Tx buffer desc", show_txbd_cmd);`
379			`register_command ("show_rxbd", "[<start BD>] [<max>]", "show Rx buffer desc", show_rxbd_cmd);`
380			`register_command ("send_packet", "<length> [<start data>] [<num_of_packets>]", "create & send packet(s)", send_packet_cmd);`
381			`register_command ("set_dest_addr", "<addrhi> <addrmid> <addrlo>", "set destination address (for send_packet)", set_dest_addr_cmd);`
382			`register_command ("init_txbd_pool", "<max>", "initialize Tx buffer descriptors", init_txbd_pool_cmd);`
383			`register_command ("init_rxbd_pool", "<max>", "initialize Rx buffer descriptors", init_rxbd_pool_cmd);`
384			`register_command ("show_phy_reg", "[<start_addr>] [<end addr>]", "show PHY registers", show_phy_reg_cmd);`
385			`register_command ("set_phy_reg", "<addr> <value>", "set PHY register", set_phy_reg_cmd);`
386			`register_command ("show_mac_regs", "", "show all MAC registers", show_mac_regs_cmd);`
387			`register_command ("eth_int_enable", "", "enable ethernet interrupt", eth_int_enable_cmd);`
388			`register_command ("show_rx_buffs", "[<show_all>]", "show receive buffers (optional arg will also show empty buffers)", show_rx_buffs_cmd);`
389			`register_command ("show_tx_buffs", "", "show transmit buffers", show_rx_buffs_cmd);`
390	140	julius	`register_command ("eth_toggle_mon", "", "Toggle traffic monitor", toggle_eth_traffic_monitor_cmd );`
391	2	marcus.erl	`#endif`
392			`/* Initialize controller */`
393			`register_command ("eth_conf", "[<ip> [<mask> [<gw>]]]", "Get/set ethernet configuration", eth_conf_cmd);`
394			`#if 0`
395			`eth_init();`
396			`printf ("Ethernet not initialized (run eth_init command)\n");`
397			`init_rx_bd_pool(0);`
398			`init_tx_bd_pool(3);`
399			`#endif`
400			`}`
401