OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [drivers/] [int.c] - Blame information for rev 435

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marcus.erl
/* This file is part of test microkernel for OpenRISC 1000. */
2
/* (C) 2001 Simon Srot, srot@opencores.org */
3
 
4
#include "common.h"
5
#include "support.h"
6 246 julius
#include "spr-defs.h"
7 2 marcus.erl
#include "int.h"
8
 
9
#ifdef OR1K
10
 
11
/* Interrupt handlers table */
12
struct ihnd int_handlers[MAX_INT_HANDLERS];
13
 
14
/* Initialize routine */
15
int int_init()
16
{
17
  int i;
18
 
19
  for(i = 0; i < MAX_INT_HANDLERS; i++) {
20
    int_handlers[i].handler = 0;
21
  }
22
 
23
  return 0;
24
}
25
 
26
/* Add interrupt handler */
27
int int_add(unsigned long vect, void (* handler)(void))
28
{
29
  if(vect >= MAX_INT_HANDLERS) return -1;
30
 
31
  int_handlers[vect].handler = handler;
32
  debug ("int_add %i: %08lx\n", vect, int_handlers[vect].handler);
33
 
34
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
35
  return 0;
36
}
37
 
38
/* Disable interrupt */
39
int int_disable(unsigned long vect)
40
{
41
  if(vect >= MAX_INT_HANDLERS) return -1;
42
 
43
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
44
 
45
  return 0;
46
}
47
 
48
/* Enable interrupt */
49
int int_enable(unsigned long vect)
50
{
51
  if(vect >= MAX_INT_HANDLERS) return -1;
52
 
53
  mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
54
 
55
  return 0;
56
}
57
 
58
/* Main interrupt handler */
59
void int_main(void)
60
{
61
  unsigned long picsr = mfspr(SPR_PICSR);
62
  unsigned long i = 0;
63
 
64
  mtspr(SPR_PICSR, 0);
65 140 julius
  //printf ("int :%08lx\n", picsr);
66 2 marcus.erl
 
67
  while(i < 32) {
68
    if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
69
      (*int_handlers[i].handler)();
70
      mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i));
71
    }
72
    i++;
73
  }
74
}
75 406 julius
 
76
 
77
void
78 419 julius
int_error(int vect, unsigned long epcr)
79 406 julius
{
80
  printf("\n\nERROR - ");
81
  switch(vect)
82
    {
83
    case 2:
84
      printf("BUS ERROR (0x200)\n");
85
      break;
86
    case 6:
87
      printf("ALIGN ERROR (0x600)\n");
88
      break;
89
    case 7:
90
      printf("ILLEGAL INSN ERROR (0x700)\n");
91
      break;
92
    default:
93
      printf("UNKNOWN ERROR (%d)\n",vect);
94
      break;
95
    }
96
 
97 419 julius
  printf("EPCR: 0x%.8x\n",epcr);
98
 
99 406 julius
  printf("\n");
100 2 marcus.erl
 
101 406 julius
  // TODO - print some more diagnostics here
102
 
103
  printf("Attemping to reset...\n\n");
104
 
105
  asm volatile("l.ori r3, r0, 0x100");
106
  asm volatile("l.jr r3");
107
  asm volatile("l.nop");
108
 
109
  // Stay here forever. 
110
  //while(1);
111
 
112
}
113
 
114 2 marcus.erl
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.