OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [drivers/] [sdc.c] - Blame information for rev 861

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 389 tac2
#include "sdc.h"
2
volatile sd_card dev;
3
 
4
void reset_card()
5
{
6
    SD_REG(SD_ARG)   = 0;
7
    SD_REG(SD_COMMAND) = 0;
8
    return;
9
}
10
 
11
unsigned char sd_wait_rsp()
12
{
13
  volatile unsigned long r1, r2;
14
 
15
 //Polling for timeout and command complete
16
 while (1 )
17
 {
18
  r1= SD_REG(SD_ERROR_INT_STATUS);
19
  r2= SD_REG(SD_NORMAL_INT_STATUS);
20
 
21
   if (( r1 & CMD_TIMEOUT ) == CMD_TIMEOUT)
22
          return 0;
23
   else if ((r2  & CMD_COMPLETE ) == CMD_COMPLETE)
24
          return 1;
25
 
26
 }
27
  //Later Exception restart module
28
  return 0;
29
 
30
}
31
 
32
int setup_bd_transfer(boolean direction, int block_addr, volatile unsigned char *buff)
33
{
34
     int offset;
35
     int block_addr_sd;
36
   //debug("Read mmc_read_block %d to addr %d \n", block_number, buff_addr);
37
        // debug("read  %d to addr %d \n", block_number, buff_addr);
38
    if (dev.phys_spec_2_0 && dev.cid_reg !=66848)
39
       block_addr_sd=block_addr;
40
    else
41
        block_addr_sd=(block_addr<<9);
42
 
43
    if (direction)
44
    {
45
        SD_REG(BD_TX)  = buff;
46
        SD_REG(BD_TX)  = block_addr_sd;
47
 
48
        return TRUE;
49
    }
50
    else
51
    {
52
        SD_REG(BD_RX)  = buff;
53
        SD_REG(BD_RX)  = block_addr_sd;
54
        return TRUE;
55
    }
56
 
57
}
58
 
59
int finnish_bd_transfer()
60
{
61
    volatile  unsigned long rtn_reg=0;
62
 
63
    rtn_reg= SD_REG(BD_ISR);
64
    while ( rtn_reg==0 ){
65
                rtn_reg= SD_REG(BD_ISR) ;
66
        }
67
        SD_REG(BD_ISR) =0;
68
 
69
    if ( rtn_reg & 0x1)
70
    {
71
        DBGA("\n Data transfer succesful\n");
72
        return TRUE;
73
    }
74
    else
75
    {
76
        DBGA("Data transfer failed, rtn %x\n",rtn_reg);
77
        return FALSE;
78
    }
79
}
80
 
81
 
82
 
83
int sd_setup_transfer (sd_card sd_card_0)
84
{
85
    DBGA("Set up transfer\n");
86
 
87
         //Put in transfer state 
88
    SD_REG(SD_COMMAND) = CMD7 | CICE | CRCE | RSP_48;
89
    SD_REG(SD_ARG)=sd_card_0.rca | 0xf0f0;
90
    if (!sd_wait_rsp()){
91
            DBGA("Go send failed TO:/!\n");
92
            return FALSE;
93
    }
94
    else if (   SD_REG(SD_RESP1) == (CARD_STATUS_STB  |  READY_FOR_DATA ) )
95
        DBGA("Ready to transfer data!\n");
96
    else{
97
        DBGA("Card not ready for data %x \n",  SD_REG(SD_RESP1) );
98
        return FALSE;
99
    }
100
    //Set block size
101
 
102
    if (!setBLockLength())
103
         return FALSE;
104
 
105
    //Set Bus width to 4, CMD55 followed by ACMD 6
106
     SD_REG(SD_COMMAND) = CMD55|RSP_48;
107
     SD_REG(SD_ARG) =sd_card_0.rca | 0xf0f0;
108
    if (!sd_wait_rsp())
109
    {
110
            DBGA("CMD55 send failed :/!\n");
111
            return FALSE;
112
    }
113
 
114
 
115
     SD_REG(SD_COMMAND) = ACMD6 | CICE | CRCE | RSP_48;
116
     SD_REG(SD_ARG)=0x2;
117
    if (!sd_wait_rsp())
118
    {
119
            DBGA("ACMD6 send failed :/!\n");
120
            return FALSE;
121
    }
122
 
123
 
124
    DBGA("Card Status reg ACMD6: 0x%x \n", SD_REG(SD_RESP1)  );
125
    DBGA("FREE BD TX/RX: 0x%x \n", SD_REG(BD_STATUS)  ) ;
126
    DBGA("CARD in Transfer state\n");
127
        return TRUE;
128
 
129
}
130
 
131
int setBLockLength(void){
132
 
133
        SD_REG(SD_COMMAND) = CMD16 | CICE | CRCE | RSP_48;
134
                SD_REG(SD_ARG)=512;
135
                if (!sd_wait_rsp()){
136
                                DBGA("Set block size failed :/!\n");
137
                return FALSE;}
138
                DBGA("Set block size to 512 Succes, resp 0x%x \n", SD_REG(SD_RESP1));
139
        return TRUE;
140
}
141
int memCardInit(void)
142
{
143
 
144
    volatile unsigned long rtn_reg=0;
145
    volatile  unsigned long rtn_reg1=0;
146
 
147
 
148
    SD_REG(SD_TIMEOUT)=0x28FF;
149
    SD_REG(SD_SOFTWARE_RST)=1;
150
 
151
    SD_REG(SD_CLOCK_D)  =0;
152
    SD_REG(SD_SOFTWARE_RST)=0;
153
 
154
    reset_card();
155
    sd_wait_rsp();
156
       DBGA("sd reset \n");
157
 
158
    SD_REG(SD_COMMAND) = ( CMD8 | CICE | CRCE | RSP_48);
159
    SD_REG(SD_ARG) = VHS|CHECK_PATTERN;
160
 
161
    dev.phys_spec_2_0 = sd_wait_rsp();
162
    reset_card;
163
    sd_wait_rsp();
164
     if (dev.phys_spec_2_0)
165
     {
166
 
167
        rtn_reg=0;
168
        while ((rtn_reg & BUSY) != BUSY)
169
        {
170
            SD_REG(SD_COMMAND) = CMD55|RSP_48;
171
            SD_REG(SD_ARG) =0;
172
            if (!sd_wait_rsp())
173
                return FALSE;
174
 
175
            SD_REG(SD_COMMAND) =ACMD41 | RSP_48;
176
            SD_REG(SD_ARG)   = 0x40000000 | 0xFF8000;
177
            if (!sd_wait_rsp())
178
                return FALSE;
179
 
180
            rtn_reg= SD_REG(SD_RESP1);
181
        }
182
        dev.Voltage_window=rtn_reg&VOLTAGE_MASK;
183
        dev.HCS_s = 0;
184
 
185
    }
186
    else
187
    {
188
        DBGA("SDC 1.xx card \n");
189
        SD_REG(SD_ARG)   =0x0000;
190
        SD_REG(SD_COMMAND) =0x0000;
191
        while (REG32(SDC_CONTROLLER_BASE+SD_STATUS)& 1) {}
192
 
193
        rtn_reg=0;
194
 
195
        while ((rtn_reg & BUSY) != BUSY)
196
        {
197
            SD_REG(SD_COMMAND) = CMD55|RSP_48;
198
            SD_REG(SD_ARG) = 0;
199
            if (!sd_wait_rsp())
200
            {
201
                rtn_reg= SD_REG(SD_RESP1) ;
202
                DBGA("FAIL rtn CMD55 %x\n", rtn_reg);
203
                   return FALSE;
204
            }
205
            SD_REG(SD_COMMAND) =ACMD41 | RSP_48;
206
            SD_REG(SD_ARG) = 0;
207
            if (!sd_wait_rsp())
208
            {
209
                rtn_reg= SD_REG(SD_RESP1) ;
210
                DBGA("FAIL rtn ACMD41 %x\n", rtn_reg);
211
                   return FALSE;
212
            }
213
            rtn_reg= SD_REG(SD_RESP1) ;
214
            DBGA("rtn ACMD41 %x\n", rtn_reg);
215
        }
216
        dev.Voltage_window=rtn_reg&VOLTAGE_MASK;
217
        dev.HCS_s = 0;
218
 
219
    }
220
    DBGA("get cid \n");
221
    SD_REG(SD_COMMAND) =CMD2 | RSP_146;
222
    SD_REG(SD_ARG) =0;
223
    if (!sd_wait_rsp())
224
             return FALSE;
225
 
226
    DBGA("get rca \n");
227
    SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48;
228
    SD_REG(SD_ARG) = 0;
229
    if (!sd_wait_rsp()){
230
        DBGA("rca failed \n");
231
        return FALSE;
232
    }
233
    rtn_reg = SD_REG(SD_RESP1);
234
    dev.rca = ((rtn_reg&RCA_RCA_MASK));
235
 
236
   SD_REG(SD_COMMAND) = CMD9 | RSP_146;
237
                        SD_REG(SD_ARG)=0;
238
                        if (!sd_wait_rsp())
239
                              DBGA("NO CID! \n");
240
                        dev.cid_reg = SD_REG(SD_RESP1);
241
 
242
    dev.Active=1;
243
    return sd_setup_transfer(dev);
244
 
245
 
246
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.