OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [drivers/] [uart.c] - Blame information for rev 323

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marcus.erl
#include "support.h"
2
#include "board.h"
3
#include "uart.h"
4
 
5
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
6
 
7
#define WAIT_FOR_XMITR \
8
        do { \
9
                lsr = REG8(UART_BASE + UART_LSR); \
10
        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
11
 
12
#define WAIT_FOR_THRE \
13
        do { \
14
                lsr = REG8(UART_BASE + UART_LSR); \
15
        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
16
 
17
#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
18
 
19
#define WAIT_FOR_CHAR \
20
         do { \
21
                lsr = REG8(UART_BASE + UART_LSR); \
22
         } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
23
 
24
#define UART_TX_BUFF_LEN 32
25
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
26
 
27
char tx_buff[UART_TX_BUFF_LEN];
28
volatile int tx_level, rx_level;
29
 
30
void uart_init(void)
31
{
32
        int divisor;
33 140 julius
        float float_divisor;
34 246 julius
 
35 2 marcus.erl
        /* Reset receiver and transmiter */
36
        REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4;
37
 
38
        /* Disable all interrupts */
39
        REG8(UART_BASE + UART_IER) = 0x00;
40
 
41
        /* Set 8 bit char, 1 stop bit, no parity */
42
        REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
43
 
44
        /* Set baud rate */
45 140 julius
        float_divisor = (float) IN_CLK/(16 * UART_BAUD_RATE);
46
        float_divisor += 0.50f; // Ensure round up
47
        divisor = (int) float_divisor;
48
 
49 2 marcus.erl
        REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
50
        REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff;
51
        REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff;
52
        REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
53
}
54
 
55
void uart_putc(char c)
56
{
57
        unsigned char lsr;
58
 
59
        WAIT_FOR_THRE;
60
        REG8(UART_BASE + UART_TX) = c;
61
        if(c == '\n') {
62
          WAIT_FOR_THRE;
63
          REG8(UART_BASE + UART_TX) = '\r';
64
        }
65
        WAIT_FOR_XMITR;
66
}
67
 
68
char uart_getc(void)
69
{
70
        unsigned char lsr;
71
        char c;
72
 
73
        WAIT_FOR_CHAR;
74
        c = REG8(UART_BASE + UART_RX);
75
        return c;
76
}
77
 
78
char uart_testc(void)
79
{
80
        if((REG8(UART_BASE + UART_LSR) & UART_LSR_DR) == UART_LSR_DR)
81
                return REG8(UART_BASE + UART_RX);
82
        else
83
                return 0;
84
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.