OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [flash.ld] - Blame information for rev 347

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marcus.erl
MEMORY
2
        {
3
        flash   : ORIGIN = 0xf0000000, LENGTH = 0x04000000
4
        vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
5
        ram     : ORIGIN = 0x00002000, LENGTH = 0x04000000 - 0x00002000
6
        }
7
 
8
SECTIONS
9
{
10
        .reset :
11
        {
12
        *(.crc)
13
        *(.reset)
14
        } > flash
15
 
16
        .text ALIGN(0x04):
17
        {
18
        *(.text)
19
        } > flash
20
 
21
        .rodata :
22
        {
23
        *(.rodata)
24
        *(.rodata.*)
25
        } > flash
26
 
27
        .monitor ALIGN(0x40000) :
28
        {
29
        *(.monitor)
30
        } > flash
31
 
32
        . += 0x100000;
33
 
34
        .config ALIGN(0x40000) :
35
        {
36
        _config_end = .;
37
        *(.config)
38
        } > flash
39
 
40
        .dummy ALIGN(0x40000):
41
        {
42
        _src_beg = .;
43
        } > flash
44
 
45
        .vectors :
46
        AT ( ADDR (.dummy) )
47
        {
48
        _vec_start = .;
49
        *(.vectors)
50
        _vec_end = .;
51
        } > vectors
52
 
53
        .data :
54
        AT ( ADDR (.dummy) + SIZEOF (.vectors) )
55
        {
56
        _dst_beg = .;
57
        *(.data)
58
        _dst_end = .;
59
        } > ram
60
 
61
        .bss :
62
        {
63
        *(.bss)
64
        } > ram
65
 
66
        .stack :
67
        {
68
        *(.stack)
69
        } > ram
70
 
71
        .mytext :
72
        {
73
        _fprog_addr = .;
74
        *(.mytext)
75
        . += 0x500;
76 246 julius
        src_addr = .;
77 2 marcus.erl
        } > ram
78
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.