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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [flash_reset.S] - Blame information for rev 796

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#include "spr-defs.h"
#include "board.h"
 
#define TRAP_ON_ERROR 0
#define LOOP_ON_ERROR 0
#define EXIT_NOP_ON_ERROR 1
#define PRINT_AND_RESET_ON_ERROR 1
 
        .extern _src_beg
        .extern _dst_beg
        .extern _dst_end
        .extern int_main
        .extern int_error
        .extern tick_interrupt
        .extern _crc32
        .extern _bstart
        .extern _bend
        .global _calc_mycrc32
        .global _mycrc32
        .global _mysize
 
        .section .stack, "aw", @nobits
.space  STACK_SIZE
_stack:
        .section .crc
_mycrc32:
        .word   0xcccccccc
_mysize:
        .word 0xdddddddd
 
.if SELF_CHECK
_calc_mycrc32:
        l.addi  r3,r0,0
        l.movhi r4,hi(_calc_mycrc32)
        l.ori   r4,r4,lo(_calc_mycrc32)
        l.movhi r5,hi(_mysize)
        l.ori   r5,r5,lo(_mysize)
        l.lwz   r5,0(r5)
        l.addi  r1,r1,-4
        l.sw    0(r1),r9
 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
        l.jal           _crc32
        l.nop
 
        l.movhi r3,hi(_mycrc32)
        l.ori   r3,r3,lo(_mycrc32)
        l.lwz   r3,0(r3)
 
        l.xor     r11,r3,r11
        l.lwz   r9,0(r1)
        l.jr    r9
        l.addi  r1,r1,4
.endif
 
        .org 0x100
 
        .section .reset, "ax"
 
 
_reset:
        l.movhi r0, 0
        /* Clear status register, set supervisor mode */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Jump to start routine */
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
 
        .section .vectors, "ax"
        .org 0x200
 
_buserr:
.if TRAP_ON_ERROR
        /* Just trap */
        l.trap 0
.endif
.if EXIT_NOP_ON_ERROR
        l.nop 0x1
.endif
.if LOOP_ON_ERROR
        l.j 0
        l.nop
.endif
.if PRINT_AND_RESET_ON_ERROR
        l.mfspr r4, r0, SPR_EPCR_BASE
        l.j     _int_error /* This will reset */
        l.ori   r3, r0, 0x2
.endif
        .section .vectors, "ax"
        .org 0x500
 
_tickint:
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))
        /* Simply load timer_ticks variable and increment */
        .extern _timer_ticks
        l.addi  r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/
        l.sw    0(r1), r25
        l.sw    4(r1), r26
        l.movhi r25, hi(timestamp)
        l.ori   r25, r25, lo(timestamp)
        l.lwz   r26, 0(r25)                     /* Load variable addr.*/
        l.addi  r26, r26, 1                     /* Increment variable */
        l.sw    0(r25), r26                     /* Store variable */
        l.movhi r25, hi(TIMER_RELOAD_VALUE)     /* Load timer value */
        l.ori   r25, r25, lo(TIMER_RELOAD_VALUE)
        l.mtspr r0, r25, SPR_TTMR               /* Reset timer */
        l.lwz   r25, 0(r1)
        l.lwz   r26, 4(r1)
        l.addi  r1, r1, 136
        l.rfe
 
        .section .vectors, "ax"
        .org 0x600
 
_alignerr:
.if TRAP_ON_ERROR
        /* Just trap */
        l.trap 0
.endif
.if EXIT_NOP_ON_ERROR
        l.nop 0x1
.endif
.if LOOP_ON_ERROR
        l.j 0
        l.nop
.endif
.if PRINT_AND_RESET_ON_ERROR
        l.mfspr r4, r0, SPR_EPCR_BASE
        l.j _int_error /* This will reset */
        l.ori r3, r0, 0x6
.endif
 
        .org 0x700
_illinsn:
.if TRAP_ON_ERROR
        /* Just trap */
        l.trap 0
.endif
.if EXIT_NOP_ON_ERROR
        l.nop 0x1
.endif
.if LOOP_ON_ERROR
        l.j 0
        l.nop
.endif
.if PRINT_AND_RESET_ON_ERROR
        l.mfspr r4, r0, SPR_EPCR_BASE
        l.j _int_error /* This will reset */
        l.ori r3, r0, 0x7
.endif
        .org 0x800
 
_userint:
        l.addi  r1,r1,-256  /*(128 + 128) */
        l.sw    0x0(r1),r2
        l.addi  r2, r1, 256
        l.sw    0x4(r1), r3
        l.movhi r3,hi(_int_wrapper)
        l.ori   r3,r3,lo(_int_wrapper)
        l.jr    r3
        l.nop
 
        .section .text
_start:
        /* Copy form flash to sram */
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_vec_start)
        l.ori   r4,r4,lo(_vec_start)
        l.movhi r5,hi(_vec_end)
        l.ori   r5,r5,lo(_vec_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
1:      l.sfgeu r4,r5
        l.bf    1f
        l.nop
        l.lwz   r8,0(r3)
        l.sw    0(r4),r8
        l.addi  r3,r3,4
        l.bnf   1b
        l.addi  r4,r4,4
1:
        l.addi  r3,r0,0
        l.addi  r4,r0,0
3:
 
        /* Instruction cache enable */
        /* Check if IC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_ICP
        l.sfeq  r26,r0
        l.bf    .L8
        l.nop
 
        /* Disable IC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_ICE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
 
        /* Establish cache block size
        If BS=0, 16;
        If BS=1, 32;
        r14 contain block size
        */
        l.mfspr r24,r0,SPR_ICCFGR
        l.andi  r26,r24,SPR_ICCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
 
        /* Establish number of cache sets
        r16 contains number of cache sets
        r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_ICCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
 
        /* Invalidate IC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
 
.L7:
        l.mtspr r0,r6,SPR_ICBIR
        l.sfne  r6,r5
        l.bf    .L7
        l.add   r6,r6,r14
 
        /* Enable IC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_ICE
        l.mtspr r0,r6,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
.L8:
        /* Data cache enable */
        /* Check if DC present and skip enabling otherwise */
        l.mfspr r24,r0,SPR_UPR
        l.andi  r26,r24,SPR_UPR_DCP
        l.sfeq  r26,r0
        l.bf    .L10
        l.nop
        /* Disable DC */
        l.mfspr r6,r0,SPR_SR
        l.addi  r5,r0,-1
        l.xori  r5,r5,SPR_SR_DCE
        l.and   r5,r6,r5
        l.mtspr r0,r5,SPR_SR
        /* Establish cache block size
           If BS=0, 16;
           If BS=1, 32;
           r14 contain block size
        */
        l.mfspr r24,r0,SPR_DCCFGR
        l.andi  r26,r24,SPR_DCCFGR_CBS
        l.srli  r28,r26,7
        l.ori   r30,r0,16
        l.sll   r14,r30,r28
        /* Establish number of cache sets
           r16 contains number of cache sets
           r28 contains log(# of cache sets)
        */
        l.andi  r26,r24,SPR_DCCFGR_NCS
        l.srli  r28,r26,3
        l.ori   r30,r0,1
        l.sll   r16,r30,r28
        /* Invalidate DC */
        l.addi  r6,r0,0
        l.sll   r5,r14,r28
.L9:
        l.mtspr r0,r6,SPR_DCBIR
        l.sfne  r6,r5
        l.bf    .L9
        l.add   r6,r6,r14
        /* Enable DC */
        l.mfspr r6,r0,SPR_SR
        l.ori   r6,r6,SPR_SR_DCE
        l.mtspr r0,r6,SPR_SR
 
.L10:
        /* Set up stack */
        l.movhi r1,hi(_stack-4)
        l.ori   r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.and   r1,r1,r2
 
 
        l.movhi r3,hi(main)
        l.ori   r3,r3,lo(main)
        l.jr    r3
        l.nop
 
_int_wrapper:
 
        l.sw    0x8(r1), r4
        l.sw    0xc(r1), r5
        l.sw    0x10(r1), r6
        l.sw    0x14(r1), r7
        l.sw    0x18(r1), r8
        l.sw    0x1c(r1), r9
        l.sw    0x20(r1), r10
        l.sw    0x24(r1), r11
        l.sw    0x28(r1), r12
        l.sw    0x2c(r1), r13
        l.sw    0x30(r1), r14
        l.sw    0x34(r1), r15
        l.sw    0x38(r1), r16
        l.sw    0x3c(r1), r17
        l.sw    0x40(r1), r18
        l.sw    0x44(r1), r19
        l.sw    0x48(r1), r20
        l.sw    0x4c(r1), r21
        l.sw    0x50(r1), r22
        l.sw    0x54(r1), r23
        l.sw    0x58(r1), r24
        l.sw    0x5c(r1), r25
        l.sw    0x60(r1), r26
        l.sw    0x64(r1), r27
        l.sw    0x68(r1), r28
        l.sw    0x6c(r1), r29
        l.sw    0x70(r1), r30
        l.sw    0x74(r1), r31
 
        l.movhi r3,hi(int_main)
        l.ori   r3,r3,lo(int_main)
        l.jalr  r3
        l.nop
 
        l.lwz   r3,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
 
        l.lwz   r2, 0x0(r1)
        l.addi  r1,r1,256
        l.rfe
        l.nop
 
 
        /* Jump to error function. Clobber r2 */
_int_error:
        l.movhi r2,hi(int_error)
        l.ori   r2,r2,lo(int_error)
        l.jr  r2
        l.nop

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [flash_reset.S] - Blame information for rev 796

Line No.	Rev	Author	Line
1	463	julius	`#include "spr-defs.h"`
2			`#include "board.h"`
3
4			`#define TRAP_ON_ERROR 0`
5			`#define LOOP_ON_ERROR 0`
6			`#define EXIT_NOP_ON_ERROR 1`
7			`#define PRINT_AND_RESET_ON_ERROR 1`
8
9			`.extern _src_beg`
10			`.extern _dst_beg`
11			`.extern _dst_end`
12			`.extern int_main`
13			`.extern int_error`
14			`.extern tick_interrupt`
15			`.extern _crc32`
16			`.extern _bstart`
17			`.extern _bend`
18			`.global _calc_mycrc32`
19			`.global _mycrc32`
20			`.global _mysize`
21
22			`.section .stack, "aw", @nobits`
23			`.space STACK_SIZE`
24			`_stack:`
25			`.section .crc`
26			`_mycrc32:`
27			`.word 0xcccccccc`
28			`_mysize:`
29			`.word 0xdddddddd`
30
31			`.if SELF_CHECK`
32			`_calc_mycrc32:`
33			`l.addi r3,r0,0`
34			`l.movhi r4,hi(_calc_mycrc32)`
35			`l.ori r4,r4,lo(_calc_mycrc32)`
36			`l.movhi r5,hi(_mysize)`
37			`l.ori r5,r5,lo(_mysize)`
38			`l.lwz r5,0(r5)`
39			`l.addi r1,r1,-4`
40			`l.sw 0(r1),r9`
41
42			`/* unsigned long crc32 (unsigned long crc, const unsigned char buf, unsigned long len); /`
43			`l.jal _crc32`
44			`l.nop`
45
46			`l.movhi r3,hi(_mycrc32)`
47			`l.ori r3,r3,lo(_mycrc32)`
48			`l.lwz r3,0(r3)`
49
50			`l.xor r11,r3,r11`
51			`l.lwz r9,0(r1)`
52			`l.jr r9`
53			`l.addi r1,r1,4`
54			`.endif`
55
56			`.org 0x100`
57
58			`.section .reset, "ax"`
59
60
61			`_reset:`
62			`l.movhi r0, 0`
63			`/* Clear status register, set supervisor mode */`
64			`l.ori r1, r0, SPR_SR_SM`
65			`l.mtspr r0, r1, SPR_SR`
66			`/* Clear timer */`
67			`l.mtspr r0, r0, SPR_TTMR`
68			`/* Jump to start routine */`
69			`l.movhi r3,hi(_start)`
70			`l.ori r3,r3,lo(_start)`
71			`l.jr r3`
72			`l.nop`
73
74			`.section .vectors, "ax"`
75			`.org 0x200`
76
77			`_buserr:`
78			`.if TRAP_ON_ERROR`
79			`/* Just trap */`
80			`l.trap 0`
81			`.endif`
82			`.if EXIT_NOP_ON_ERROR`
83			`l.nop 0x1`
84			`.endif`
85			`.if LOOP_ON_ERROR`
86			`l.j 0`
87			`l.nop`
88			`.endif`
89			`.if PRINT_AND_RESET_ON_ERROR`
90			`l.mfspr r4, r0, SPR_EPCR_BASE`
91			`l.j _int_error /* This will reset */`
92			`l.ori r3, r0, 0x2`
93			`.endif`
94			`.section .vectors, "ax"`
95			`.org 0x500`
96
97			`_tickint:`
98			`#define TIMER_RELOAD_VALUE (SPR_TTMR_IE \| SPR_TTMR_RT \| ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD))`
99			`/* Simply load timer_ticks variable and increment */`
100			`.extern _timer_ticks`
101			`l.addi r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/`
102			`l.sw 0(r1), r25`
103			`l.sw 4(r1), r26`
104			`l.movhi r25, hi(timestamp)`
105			`l.ori r25, r25, lo(timestamp)`
106			`l.lwz r26, 0(r25) /* Load variable addr.*/`
107			`l.addi r26, r26, 1 /* Increment variable */`
108			`l.sw 0(r25), r26 /* Store variable */`
109			`l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */`
110			`l.ori r25, r25, lo(TIMER_RELOAD_VALUE)`
111			`l.mtspr r0, r25, SPR_TTMR /* Reset timer */`
112			`l.lwz r25, 0(r1)`
113			`l.lwz r26, 4(r1)`
114			`l.addi r1, r1, 136`
115			`l.rfe`
116
117			`.section .vectors, "ax"`
118			`.org 0x600`
119
120			`_alignerr:`
121			`.if TRAP_ON_ERROR`
122			`/* Just trap */`
123			`l.trap 0`
124			`.endif`
125			`.if EXIT_NOP_ON_ERROR`
126			`l.nop 0x1`
127			`.endif`
128			`.if LOOP_ON_ERROR`
129			`l.j 0`
130			`l.nop`
131			`.endif`
132			`.if PRINT_AND_RESET_ON_ERROR`
133			`l.mfspr r4, r0, SPR_EPCR_BASE`
134			`l.j _int_error /* This will reset */`
135			`l.ori r3, r0, 0x6`
136			`.endif`
137
138			`.org 0x700`
139			`_illinsn:`
140			`.if TRAP_ON_ERROR`
141			`/* Just trap */`
142			`l.trap 0`
143			`.endif`
144			`.if EXIT_NOP_ON_ERROR`
145			`l.nop 0x1`
146			`.endif`
147			`.if LOOP_ON_ERROR`
148			`l.j 0`
149			`l.nop`
150			`.endif`
151			`.if PRINT_AND_RESET_ON_ERROR`
152			`l.mfspr r4, r0, SPR_EPCR_BASE`
153			`l.j _int_error /* This will reset */`
154			`l.ori r3, r0, 0x7`
155			`.endif`
156			`.org 0x800`
157
158			`_userint:`
159			`l.addi r1,r1,-256 /(128 + 128) /`
160			`l.sw 0x0(r1),r2`
161			`l.addi r2, r1, 256`
162			`l.sw 0x4(r1), r3`
163			`l.movhi r3,hi(_int_wrapper)`
164			`l.ori r3,r3,lo(_int_wrapper)`
165			`l.jr r3`
166			`l.nop`
167
168			`.section .text`
169			`_start:`
170			`/* Copy form flash to sram */`
171			`l.movhi r3,hi(_src_beg)`
172			`l.ori r3,r3,lo(_src_beg)`
173			`l.movhi r4,hi(_vec_start)`
174			`l.ori r4,r4,lo(_vec_start)`
175			`l.movhi r5,hi(_vec_end)`
176			`l.ori r5,r5,lo(_vec_end)`
177			`l.sub r5,r5,r4`
178			`l.sfeqi r5,0`
179			`l.bf 2f`
180			`l.nop`
181			`1: l.lwz r6,0(r3)`
182			`l.sw 0(r4),r6`
183			`l.addi r3,r3,4`
184			`l.addi r4,r4,4`
185			`l.addi r5,r5,-4`
186			`l.sfgtsi r5,0`
187			`l.bf 1b`
188			`l.nop`
189			`2:`
190			`l.movhi r4,hi(_dst_beg)`
191			`l.ori r4,r4,lo(_dst_beg)`
192			`l.movhi r5,hi(_dst_end)`
193			`l.ori r5,r5,lo(_dst_end)`
194			`1: l.sfgeu r4,r5`
195			`l.bf 1f`
196			`l.nop`
197			`l.lwz r8,0(r3)`
198			`l.sw 0(r4),r8`
199			`l.addi r3,r3,4`
200			`l.bnf 1b`
201			`l.addi r4,r4,4`
202			`1:`
203			`l.addi r3,r0,0`
204			`l.addi r4,r0,0`
205			`3:`
206
207			`/* Instruction cache enable */`
208			`/* Check if IC present and skip enabling otherwise */`
209			`l.mfspr r24,r0,SPR_UPR`
210			`l.andi r26,r24,SPR_UPR_ICP`
211			`l.sfeq r26,r0`
212			`l.bf .L8`
213			`l.nop`
214
215			`/* Disable IC */`
216			`l.mfspr r6,r0,SPR_SR`
217			`l.addi r5,r0,-1`
218			`l.xori r5,r5,SPR_SR_ICE`
219			`l.and r5,r6,r5`
220			`l.mtspr r0,r5,SPR_SR`
221
222			`/* Establish cache block size`
223			`If BS=0, 16;`
224			`If BS=1, 32;`
225			`r14 contain block size`
226			`*/`
227			`l.mfspr r24,r0,SPR_ICCFGR`
228			`l.andi r26,r24,SPR_ICCFGR_CBS`
229			`l.srli r28,r26,7`
230			`l.ori r30,r0,16`
231			`l.sll r14,r30,r28`
232
233			`/* Establish number of cache sets`
234			`r16 contains number of cache sets`
235			`r28 contains log(# of cache sets)`
236			`*/`
237			`l.andi r26,r24,SPR_ICCFGR_NCS`
238			`l.srli r28,r26,3`
239			`l.ori r30,r0,1`
240			`l.sll r16,r30,r28`
241
242			`/* Invalidate IC */`
243			`l.addi r6,r0,0`
244			`l.sll r5,r14,r28`
245
246			`.L7:`
247			`l.mtspr r0,r6,SPR_ICBIR`
248			`l.sfne r6,r5`
249			`l.bf .L7`
250			`l.add r6,r6,r14`
251
252			`/* Enable IC */`
253			`l.mfspr r6,r0,SPR_SR`
254			`l.ori r6,r6,SPR_SR_ICE`
255			`l.mtspr r0,r6,SPR_SR`
256			`l.nop`
257			`l.nop`
258			`l.nop`
259			`l.nop`
260			`l.nop`
261			`l.nop`
262			`l.nop`
263			`l.nop`
264
265			`.L8:`
266			`/* Data cache enable */`
267			`/* Check if DC present and skip enabling otherwise */`
268			`l.mfspr r24,r0,SPR_UPR`
269			`l.andi r26,r24,SPR_UPR_DCP`
270			`l.sfeq r26,r0`
271			`l.bf .L10`
272			`l.nop`
273			`/* Disable DC */`
274			`l.mfspr r6,r0,SPR_SR`
275			`l.addi r5,r0,-1`
276			`l.xori r5,r5,SPR_SR_DCE`
277			`l.and r5,r6,r5`
278			`l.mtspr r0,r5,SPR_SR`
279			`/* Establish cache block size`
280			`If BS=0, 16;`
281			`If BS=1, 32;`
282			`r14 contain block size`
283			`*/`
284			`l.mfspr r24,r0,SPR_DCCFGR`
285			`l.andi r26,r24,SPR_DCCFGR_CBS`
286			`l.srli r28,r26,7`
287			`l.ori r30,r0,16`
288			`l.sll r14,r30,r28`
289			`/* Establish number of cache sets`
290			`r16 contains number of cache sets`
291			`r28 contains log(# of cache sets)`
292			`*/`
293			`l.andi r26,r24,SPR_DCCFGR_NCS`
294			`l.srli r28,r26,3`
295			`l.ori r30,r0,1`
296			`l.sll r16,r30,r28`
297			`/* Invalidate DC */`
298			`l.addi r6,r0,0`
299			`l.sll r5,r14,r28`
300			`.L9:`
301			`l.mtspr r0,r6,SPR_DCBIR`
302			`l.sfne r6,r5`
303			`l.bf .L9`
304			`l.add r6,r6,r14`
305			`/* Enable DC */`
306			`l.mfspr r6,r0,SPR_SR`
307			`l.ori r6,r6,SPR_SR_DCE`
308			`l.mtspr r0,r6,SPR_SR`
309
310			`.L10:`
311			`/* Set up stack */`
312			`l.movhi r1,hi(_stack-4)`
313			`l.ori r1,r1,lo(_stack-4)`
314			`l.addi r2,r0,-3`
315			`l.and r1,r1,r2`
316
317
318			`l.movhi r3,hi(main)`
319			`l.ori r3,r3,lo(main)`
320			`l.jr r3`
321			`l.nop`
322
323			`_int_wrapper:`
324
325			`l.sw 0x8(r1), r4`
326			`l.sw 0xc(r1), r5`
327			`l.sw 0x10(r1), r6`
328			`l.sw 0x14(r1), r7`
329			`l.sw 0x18(r1), r8`
330			`l.sw 0x1c(r1), r9`
331			`l.sw 0x20(r1), r10`
332			`l.sw 0x24(r1), r11`
333			`l.sw 0x28(r1), r12`
334			`l.sw 0x2c(r1), r13`
335			`l.sw 0x30(r1), r14`
336			`l.sw 0x34(r1), r15`
337			`l.sw 0x38(r1), r16`
338			`l.sw 0x3c(r1), r17`
339			`l.sw 0x40(r1), r18`
340			`l.sw 0x44(r1), r19`
341			`l.sw 0x48(r1), r20`
342			`l.sw 0x4c(r1), r21`
343			`l.sw 0x50(r1), r22`
344			`l.sw 0x54(r1), r23`
345			`l.sw 0x58(r1), r24`
346			`l.sw 0x5c(r1), r25`
347			`l.sw 0x60(r1), r26`
348			`l.sw 0x64(r1), r27`
349			`l.sw 0x68(r1), r28`
350			`l.sw 0x6c(r1), r29`
351			`l.sw 0x70(r1), r30`
352			`l.sw 0x74(r1), r31`
353
354			`l.movhi r3,hi(int_main)`
355			`l.ori r3,r3,lo(int_main)`
356			`l.jalr r3`
357			`l.nop`
358
359			`l.lwz r3,0x4(r1)`
360			`l.lwz r4,0x8(r1)`
361			`l.lwz r5,0xc(r1)`
362			`l.lwz r6,0x10(r1)`
363			`l.lwz r7,0x14(r1)`
364			`l.lwz r8,0x18(r1)`
365			`l.lwz r9,0x1c(r1)`
366			`l.lwz r10,0x20(r1)`
367			`l.lwz r11,0x24(r1)`
368			`l.lwz r12,0x28(r1)`
369			`l.lwz r13,0x2c(r1)`
370			`l.lwz r14,0x30(r1)`
371			`l.lwz r15,0x34(r1)`
372			`l.lwz r16,0x38(r1)`
373			`l.lwz r17,0x3c(r1)`
374			`l.lwz r18,0x40(r1)`
375			`l.lwz r19,0x44(r1)`
376			`l.lwz r20,0x48(r1)`
377			`l.lwz r21,0x4c(r1)`
378			`l.lwz r22,0x50(r1)`
379			`l.lwz r23,0x54(r1)`
380			`l.lwz r24,0x58(r1)`
381			`l.lwz r25,0x5c(r1)`
382			`l.lwz r26,0x60(r1)`
383			`l.lwz r27,0x64(r1)`
384			`l.lwz r28,0x68(r1)`
385			`l.lwz r29,0x6c(r1)`
386			`l.lwz r30,0x70(r1)`
387			`l.lwz r31,0x74(r1)`
388
389			`l.lwz r2, 0x0(r1)`
390			`l.addi r1,r1,256`
391			`l.rfe`
392			`l.nop`
393
394
395			`/* Jump to error function. Clobber r2 */`
396			`_int_error:`
397			`l.movhi r2,hi(int_error)`
398			`l.ori r2,r2,lo(int_error)`
399			`l.jr r2`
400			`l.nop`