OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [include/] [board.h] - Blame information for rev 802

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 marcus.erl
#ifndef _BOARD_H_
2
#define _BOARD_H_
3
 
4 140 julius
#define CFG_IN_FLASH            0
5 2 marcus.erl
 
6
//LAN controller 
7
//#define SMC91111_LAN          1
8
#define OC_LAN                  1
9
 
10
/* BOARD
11
 * 0 - bender
12
 * 1 - marvin
13 185 julius
 * 2 - ORSoC A3PE1500 board
14
 * 3 - ORSoC A3P1000 board
15 419 julius
 * 4 - ML501
16 2 marcus.erl
 */
17 246 julius
#define BOARD                   2
18 2 marcus.erl
 
19 140 julius
/* Ethernet IP and TFTP config
20
 * 0 - JB ORSoC board
21
 * 1 - AE ORSoC board
22
 * 2 - JB Southpole board
23 246 julius
 * 3 - JB ORSoC board 2
24
 * 4 - Unassigned
25 140 julius
 */
26 246 julius
#define IPCONFIG                 3
27 140 julius
 
28 2 marcus.erl
#if BOARD==0
29
// Nibbler on bender1
30
 
31
#  define FLASH_BASE_ADDR         0xf0000000
32
#  define FLASH_SIZE              0x02000000
33
#  define FLASH_BLOCK_SIZE        0x00020000
34
#  define START_ADD               0x0
35
#  define CONFIG_OR32_MC_VERSION  2
36
#  define IN_CLK                  25000000
37
#  define BOARD_DEF_NAME          "bender"
38
// Flash Organization on board
39
// FLASH_ORG_XX_Y
40
// where XX - flash bit size
41
//       Y  - number of parallel devices connected
42
#  define FLASH_ORG_16_1          1
43
#elif BOARD==1
44
//Marvin
45
#  define FLASH_BASE_ADDR         0xf0000000
46
#  define FLASH_SIZE              0x04000000
47
#  define FLASH_BLOCK_SIZE        0x00040000
48
#  define START_ADD               0x0
49
#  define CONFIG_OR32_MC_VERSION  1
50
#  define IN_CLK                  50000000
51
#  define FLASH_ORG_16_2          1
52
#  define BOARD_DEF_NAME          "marvin"
53 389 tac2
 
54 140 julius
#elif BOARD==2
55 405 julius
//ORSoC ordb1a3pe1500
56 246 julius
#  define SDRAM_SIZE              0x02000000
57
#  define SDRAM_ROW_SIZE          0x00000400
58
#  define SDRAM_BANK_SIZE         0x00800000
59 140 julius
#  define IN_CLK                  20000000
60
 
61
#  define BOARD_DEF_NAME          "ORSoC devboard"
62
#elif BOARD==3
63 419 julius
//ORSoC ordb1a3p1000
64 140 julius
 
65 246 julius
#  define SDRAM_SIZE              0x02000000
66
#  define SDRAM_ROW_SIZE          0x00000400
67
#  define SDRAM_BANK_SIZE         0x00800000
68
#  define IN_CLK                  25000000
69 140 julius
#  define BOARD_DEF_NAME          "ORSoC A3P1000 devboard"
70
 
71 419 julius
#elif BOARD==4
72
//Xilinx ML501
73
 
74
#  define SDRAM_SIZE              0x10000000
75
#  define SDRAM_ROW_SIZE          0x00000400
76
#  define SDRAM_BANK_SIZE         0x00800000
77
#  define IN_CLK                  50000000
78
#  define BOARD_DEF_NAME          "Xilinx ML501"
79
 
80 2 marcus.erl
#else
81
//Custom Board
82 246 julius
 
83 2 marcus.erl
#  define IN_CLK                  25000000
84
#  define BOARD_DEF_NAME          "custom"
85
 
86
#endif
87
 
88 140 julius
 
89
// IP tboot configs
90
#if IPCONFIG==0
91
 
92
#define BOARD_DEF_IP            0xc0a8649b // 192.168.100.155
93
#define BOARD_DEF_MASK          0xffffff00 // 255.255.255.0
94
#define BOARD_DEF_GW            0xc0a86401 // 192.168.100.1
95
#define BOARD_DEF_TBOOT_SRVR    0xc0a86469 //"192.168.100.105"
96
#define BOARD_DEF_IMAGE_NAME    "boot.img"
97
#define ETH_MDIOPHYADDR         0x00
98
#define ETH_MACADDR0            0x00
99
#define ETH_MACADDR1            0x12
100
#define ETH_MACADDR2            0x34
101
#define ETH_MACADDR3            0x56
102
#define ETH_MACADDR4            0x78
103
#define ETH_MACADDR5            0x9a
104
 
105
#elif IPCONFIG==1
106
 
107
#define BOARD_DEF_IP            0xc0a8649c // 192.168.100.156
108
#define BOARD_DEF_MASK          0xffffff00 // 255.255.255.0
109
#define BOARD_DEF_GW            0xc0a86401 // 192.168.100.1
110
#define BOARD_DEF_TBOOT_SRVR    0xc0a864e3 //"192.168.100.227"
111
#define BOARD_DEF_IMAGE_NAME    "boot.img"
112
#define ETH_MDIOPHYADDR         0x00
113 405 julius
#define ETH_MACADDR0            0x00
114
#define ETH_MACADDR1            0x12
115 140 julius
#define ETH_MACADDR2            0x34
116
#define ETH_MACADDR3            0x56
117
#define ETH_MACADDR4            0x78
118 185 julius
#define ETH_MACADDR5            0x9b
119 140 julius
 
120
#elif IPCONFIG==2
121
 
122
#define BOARD_DEF_IP            0xac1e0002 // 172.30.0.2
123 419 julius
#define BOARD_DEF_MASK          0xffff0000 // 255.255.0.0
124 140 julius
#define BOARD_DEF_GW            0xac1e0001 //"172.30.0.1"
125
#define BOARD_DEF_TBOOT_SRVR    0xac1e0001 //"172.30.0.1"
126
#define BOARD_DEF_IMAGE_NAME    "boot.img"
127
#define ETH_MDIOPHYADDR         0x00
128
#define ETH_MACADDR0            0x00
129
#define ETH_MACADDR1            0x12
130
#define ETH_MACADDR2            0x34
131
#define ETH_MACADDR3            0x56
132
#define ETH_MACADDR4            0x78
133 185 julius
#define ETH_MACADDR5            0x9c
134 140 julius
 
135 405 julius
#elif IPCONFIG==3 // JB ORSoC board 2
136 140 julius
 
137 463 julius
#define BOARD_DEF_IP            0xc0a8005a // 192.168.0.90
138 246 julius
#define BOARD_DEF_MASK          0xffffff00 // 255.255.255.0
139 463 julius
#define BOARD_DEF_GW            0xc0a80001 // 192.168.0.1
140
#define BOARD_DEF_TBOOT_SRVR    0xc0a8000f // 192.168.0.15
141 246 julius
#define BOARD_DEF_IMAGE_NAME    "boot.img"
142
#define ETH_MDIOPHYADDR         0x00
143 405 julius
#define ETH_MACADDR0            0x00
144
#define ETH_MACADDR1            0x12
145 246 julius
#define ETH_MACADDR2            0x34
146
#define ETH_MACADDR3            0x56
147
#define ETH_MACADDR4            0x78
148
#define ETH_MACADDR5            0x9d
149
 
150
#elif IPCONFIG==4 // Unassigned config...
151
 
152 140 julius
#define BOARD_DEF_IP            0x0a01010a // 10.1.1.10
153
#define BOARD_DEF_MASK          0xffffff00 // 255.255.255.0
154 185 julius
#define BOARD_DEF_GW            0x0a010101 // 10.1.1.1
155
#define BOARD_DEF_TBOOT_SRVR    0x0a010101 // 10.1.1.1
156 140 julius
#define BOARD_DEF_IMAGE_NAME    "boot.img"
157
#define ETH_MDIOPHYADDR         0x00
158 405 julius
#define ETH_MACADDR0            0x00
159
#define ETH_MACADDR1            0x01
160 140 julius
#define ETH_MACADDR2            0x34
161
#define ETH_MACADDR3            0x56
162
#define ETH_MACADDR4            0x78
163 405 julius
#define ETH_MACADDR5            0x9e
164 140 julius
 
165
#endif
166
 
167 2 marcus.erl
 
168 464 julius
 
169 2 marcus.erl
#define TICKS_PER_SEC           100
170
 
171 140 julius
#define MS_PER_SEC 1000
172
#define US_PER_SEC 1000000
173
#define US_PER_TICK (US_PER_SEC/TICKS_PER_SEC)
174
#define TICKS_PER_US (TICKS_PER_SEC*1000000)
175
 
176 2 marcus.erl
#define STACK_SIZE              0x10000
177
 
178 464 julius
/* UART core defines */
179 2 marcus.erl
#define UART_BASE               0x90000000
180
#define UART_IRQ                2
181 464 julius
#define UART_BAUD_RATE          115200
182
 
183
/* Ethernet core defines */
184 2 marcus.erl
#define ETH_BASE                0x92000000
185
#define ETH_IRQ                 4
186 467 julius
#define ETH_DATA_BASE  ((((unsigned long)&_stack_top) + 16) & ~0x3)
187 140 julius
#define SPI_BASE                0xb0000000
188 2 marcus.erl
#define CRT_BASE_ADDR           0x97000000
189
#define ATA_BASE_ADDR           0x9e000000
190
#define KBD_BASE_ADD            0x94000000
191
#define KBD_IRQ                 5
192
 
193 405 julius
#define SDC_CONTROLLER_BASE     0x9e000000
194
 
195 140 julius
#define CRT_ENABLED             0
196 2 marcus.erl
#define FB_BASE_ADDR            0xa8000000
197
 
198
/* Whether online help is available -- saves space */
199
#define HELP_ENABLED            1
200
 
201
/* Whether self check is enabled */
202
#define SELF_CHECK              0
203
 
204
/* Whether we have keyboard suppport */
205 140 julius
#define KBD_ENABLED             0
206 2 marcus.erl
 
207
/* Keyboard buffer size */
208
#define KBDBUF_SIZE             256
209
 
210
/* Which console is used (CT_NONE, CT_SIM, CT_UART, CT_CRT) */
211
#define CONSOLE_TYPE            CT_UART
212
 
213
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.