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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [include/] [eth.h] - Blame information for rev 271

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#define ETH_REG_BASE  ETH_BASE 
#define ETH_BD_BASE   (ETH_BASE + 0x400)
#define ETH_TOTAL_BD  32
#define ETH_MAXBUF_LEN 0x600
 
#define ETH_TXBD_NUM      16
#define ETH_TXBD_NUM_MASK (ETH_TXBD_NUM - 1)
#define ETH_RXBD_NUM      16
#define ETH_RXBD_NUM_MASK (ETH_RXBD_NUM - 1)
 
typedef unsigned int uint;
 
/* Ethernet configuration registers */
typedef struct _oeth_regs {
        uint    moder;          /* Mode Register */
        uint    int_src;        /* Interrupt Source Register */
        uint    int_mask;       /* Interrupt Mask Register */
        uint    ipgt;           /* Back to Bak Inter Packet Gap Register */
        uint    ipgr1;          /* Non Back to Back Inter Packet Gap Register 1 */
        uint    ipgr2;          /* Non Back to Back Inter Packet Gap Register 2 */
        uint    packet_len;     /* Packet Length Register (min. and max.) */
        uint    collconf;       /* Collision and Retry Configuration Register */
        uint    tx_bd_num;      /* Transmit Buffer Descriptor Number Register */
        uint    ctrlmoder;      /* Control Module Mode Register */
        uint    miimoder;       /* MII Mode Register */
        uint    miicommand;     /* MII Command Register */
        uint    miiaddress;     /* MII Address Register */
        uint    miitx_data;     /* MII Transmit Data Register */
        uint    miirx_data;     /* MII Receive Data Register */
        uint    miistatus;      /* MII Status Register */
        uint    mac_addr0;      /* MAC Individual Address Register 0 */
        uint    mac_addr1;      /* MAC Individual Address Register 1 */
        uint    hash_addr0;     /* Hash Register 0 */
        uint    hash_addr1;     /* Hash Register 1 */
} oeth_regs;
 
/* Ethernet buffer descriptor */
typedef struct _oeth_bd {
        uint    len_status;
        uint    addr;           /* Buffer address */
} oeth_bd;
 
 
/* Ethernet buffer descriptor */
typedef struct _eth_bd {
        volatile unsigned long   len_status;     /* Buffer length and status */
        volatile unsigned long    addr;          /* Buffer address */
} eth_bd;
 
extern void eth_init (void (*rec)(volatile unsigned char *, int));
extern void *eth_get_tx_buf (void);
extern void eth_send (void *buf, unsigned long len);
extern unsigned long eth_rx (void);
extern void eth_halt(void);
extern void init_rx_bd_pool(void);
extern void init_tx_bd_pool(void);
extern void eth_int_enable(void);
extern void eth_toggle_traffic_mon(void);
 
/* Tx BD */
#define ETH_TX_BD_READY    0x8000 /* Tx BD Ready */
#define ETH_TX_BD_IRQ      0x4000 /* Tx BD IRQ Enable */
#define ETH_TX_BD_WRAP     0x2000 /* Tx BD Wrap (last BD) */
#define ETH_TX_BD_PAD      0x1000 /* Tx BD Pad Enable */
#define ETH_TX_BD_CRC      0x0800 /* Tx BD CRC Enable */
 
#define ETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */
#define ETH_TX_BD_RETRY    0x00F0 /* Tx BD Retry Status */
#define ETH_TX_BD_RETLIM   0x0008 /* Tx BD Retransmission Limit Status */
#define ETH_TX_BD_LATECOL  0x0004 /* Tx BD Late Collision Status */
#define ETH_TX_BD_DEFER    0x0002 /* Tx BD Defer Status */
#define ETH_TX_BD_CARRIER  0x0001 /* Tx BD Carrier Sense Lost Status */
#define ETH_TX_BD_STATS        (ETH_TX_BD_UNDERRUN             | \
                                ETH_TX_BD_RETRY                | \
                                ETH_TX_BD_RETLIM               | \
                                ETH_TX_BD_LATECOL              | \
                                ETH_TX_BD_DEFER                | \
                                ETH_TX_BD_CARRIER)
 
/* Rx BD */
#define ETH_RX_BD_EMPTY    0x8000 /* Rx BD Empty */
#define ETH_RX_BD_IRQ      0x4000 /* Rx BD IRQ Enable */
#define ETH_RX_BD_WRAP     0x2000 /* Rx BD Wrap (last BD) */
 
#define ETH_RX_BD_MISS     0x0080 /* Rx BD Miss Status */
#define ETH_RX_BD_OVERRUN  0x0040 /* Rx BD Overrun Status */
#define ETH_RX_BD_INVSIMB  0x0020 /* Rx BD Invalid Symbol Status */
#define ETH_RX_BD_DRIBBLE  0x0010 /* Rx BD Dribble Nibble Status */
#define ETH_RX_BD_TOOLONG  0x0008 /* Rx BD Too Long Status */
#define ETH_RX_BD_SHORT    0x0004 /* Rx BD Too Short Frame Status */
#define ETH_RX_BD_CRCERR   0x0002 /* Rx BD CRC Error Status */
#define ETH_RX_BD_LATECOL  0x0001 /* Rx BD Late Collision Status */
#define ETH_RX_BD_STATS        (ETH_RX_BD_MISS                | \
                                ETH_RX_BD_OVERRUN              | \
                                ETH_RX_BD_INVSIMB              | \
                                ETH_RX_BD_DRIBBLE              | \
                                ETH_RX_BD_TOOLONG              | \
                                ETH_RX_BD_SHORT                | \
                                ETH_RX_BD_CRCERR               | \
                                ETH_RX_BD_LATECOL)
 
/* Register space */
#define ETH_MODER      0x00     /* Mode Register */
#define ETH_INT        0x04     /* Interrupt Source Register */
#define ETH_INT_MASK   0x08 /* Interrupt Mask Register */
#define ETH_IPGT       0x0C /* Back to Bak Inter Packet Gap Register */
#define ETH_IPGR1      0x10 /* Non Back to Back Inter Packet Gap Register 1 */
#define ETH_IPGR2      0x14 /* Non Back to Back Inter Packet Gap Register 2 */
#define ETH_PACKETLEN  0x18 /* Packet Length Register (min. and max.) */
#define ETH_COLLCONF   0x1C /* Collision and Retry Configuration Register */
#define ETH_TX_BD_NUM  0x20 /* Transmit Buffer Descriptor Number Register */
#define ETH_CTRLMODER  0x24 /* Control Module Mode Register */
#define ETH_MIIMODER   0x28 /* MII Mode Register */
#define ETH_MIICOMMAND 0x2C /* MII Command Register */
#define ETH_MIIADDRESS 0x30 /* MII Address Register */
#define ETH_MIITX_DATA 0x34 /* MII Transmit Data Register */
#define ETH_MIIRX_DATA 0x38 /* MII Receive Data Register */
#define ETH_MIISTATUS  0x3C /* MII Status Register */
#define ETH_MAC_ADDR0  0x40 /* MAC Individual Address Register 0 */
#define ETH_MAC_ADDR1  0x44 /* MAC Individual Address Register 1 */
#define ETH_HASH_ADDR0 0x48 /* Hash Register 0 */
#define ETH_HASH_ADDR1 0x4C /* Hash Register 1 */
 
/* MODER Register */
#define ETH_MODER_RXEN     0x00000001 /* Receive Enable  */
#define ETH_MODER_TXEN     0x00000002 /* Transmit Enable */
#define ETH_MODER_NOPRE    0x00000004 /* No Preamble  */
#define ETH_MODER_BRO      0x00000008 /* Reject Broadcast */
#define ETH_MODER_IAM      0x00000010 /* Use Individual Hash */
#define ETH_MODER_PRO      0x00000020 /* Promiscuous (receive all) */
#define ETH_MODER_IFG      0x00000040 /* Min. IFG not required */
#define ETH_MODER_LOOPBCK  0x00000080 /* Loop Back */
#define ETH_MODER_NOBCKOF  0x00000100 /* No Backoff */
#define ETH_MODER_EXDFREN  0x00000200 /* Excess Defer */
#define ETH_MODER_FULLD    0x00000400 /* Full Duplex */
#define ETH_MODER_RST      0x00000800 /* Reset MAC */
#define ETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */
#define ETH_MODER_CRCEN    0x00002000 /* CRC Enable */
#define ETH_MODER_HUGEN    0x00004000 /* Huge Enable */
#define ETH_MODER_PAD      0x00008000 /* Pad Enable */
#define ETH_MODER_RECSMALL 0x00010000 /* Receive Small */
 
/* Interrupt Source Register */
#define ETH_INT_TXB        0x00000001 /* Transmit Buffer IRQ */
#define ETH_INT_TXE        0x00000002 /* Transmit Error IRQ */
#define ETH_INT_RXF        0x00000004 /* Receive Frame IRQ */
#define ETH_INT_RXE        0x00000008 /* Receive Error IRQ */
#define ETH_INT_BUSY       0x00000010 /* Busy IRQ */
#define ETH_INT_TXC        0x00000020 /* Transmit Control Frame IRQ */
#define ETH_INT_RXC        0x00000040 /* Received Control Frame IRQ */
 
/* Interrupt Mask Register */
#define ETH_INT_MASK_TXB   0x00000001 /* Transmit Buffer IRQ Mask */
#define ETH_INT_MASK_TXE   0x00000002 /* Transmit Error IRQ Mask */
#define ETH_INT_MASK_RXF   0x00000004 /* Receive Frame IRQ Mask */
#define ETH_INT_MASK_RXE   0x00000008 /* Receive Error IRQ Mask */
#define ETH_INT_MASK_BUSY  0x00000010 /* Busy IRQ Mask */
#define ETH_INT_MASK_TXC   0x00000020 /* Transmit Control Frame IRQ Mask */
#define ETH_INT_MASK_RXC   0x00000040 /* Received Control Frame IRQ Mask */
 
/* Control Module Mode Register */
#define ETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */
#define ETH_CTRLMODER_RXFLOW  0x00000002 /* Receive Control Flow Enable */
#define ETH_CTRLMODER_TXFLOW  0x00000004 /* Transmit Control Flow Enable */
 
/* MII Mode Register */
#define ETH_MIIMODER_CLKDIV   0x000000FF /* Clock Divider */
#define ETH_MIIMODER_NOPRE    0x00000100 /* No Preamble */
#define ETH_MIIMODER_RST      0x00000200 /* MIIM Reset */
 
/* MII Command Register */
#define ETH_MIICOMMAND_SCANSTAT  0x00000001 /* Scan Status */
#define ETH_MIICOMMAND_RSTAT     0x00000002 /* Read Status */
#define ETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
 
/* MII Address Register */
#define ETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */
#define ETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */
 
/* MII Status Register */
#define ETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
#define ETH_MIISTATUS_BUSY     0x00000002 /* MII Busy */
#define ETH_MIISTATUS_NVALID   0x00000004 /* Data in MII Status Register is invalid */
 

Line No.	Rev	Author	Line
1	2	marcus.erl	`#define ETH_REG_BASE ETH_BASE`
2			`#define ETH_BD_BASE (ETH_BASE + 0x400)`
3	140	julius	`#define ETH_TOTAL_BD 32`
4	2	marcus.erl	`#define ETH_MAXBUF_LEN 0x600`
5
6	140	julius	`#define ETH_TXBD_NUM 16`
7	2	marcus.erl	`#define ETH_TXBD_NUM_MASK (ETH_TXBD_NUM - 1)`
8	140	julius	`#define ETH_RXBD_NUM 16`
9	2	marcus.erl	`#define ETH_RXBD_NUM_MASK (ETH_RXBD_NUM - 1)`
10
11	140	julius	`typedef unsigned int uint;`
12
13			`/* Ethernet configuration registers */`
14			`typedef struct _oeth_regs {`
15			`uint moder; /* Mode Register */`
16			`uint int_src; /* Interrupt Source Register */`
17			`uint int_mask; /* Interrupt Mask Register */`
18			`uint ipgt; /* Back to Bak Inter Packet Gap Register */`
19			`uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */`
20			`uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */`
21			`uint packet_len; /* Packet Length Register (min. and max.) */`
22			`uint collconf; /* Collision and Retry Configuration Register */`
23			`uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */`
24			`uint ctrlmoder; /* Control Module Mode Register */`
25			`uint miimoder; /* MII Mode Register */`
26			`uint miicommand; /* MII Command Register */`
27			`uint miiaddress; /* MII Address Register */`
28			`uint miitx_data; /* MII Transmit Data Register */`
29			`uint miirx_data; /* MII Receive Data Register */`
30			`uint miistatus; /* MII Status Register */`
31			`uint mac_addr0; /* MAC Individual Address Register 0 */`
32			`uint mac_addr1; /* MAC Individual Address Register 1 */`
33			`uint hash_addr0; /* Hash Register 0 */`
34			`uint hash_addr1; /* Hash Register 1 */`
35			`} oeth_regs;`
36
37	2	marcus.erl	`/* Ethernet buffer descriptor */`
38	140	julius	`typedef struct _oeth_bd {`
39			`uint len_status;`
40			`uint addr; /* Buffer address */`
41			`} oeth_bd;`
42
43
44			`/* Ethernet buffer descriptor */`
45	2	marcus.erl	`typedef struct _eth_bd {`
46			`volatile unsigned long len_status; /* Buffer length and status */`
47			`volatile unsigned long addr; /* Buffer address */`
48			`} eth_bd;`
49
50			`extern void eth_init (void (rec)(volatile unsigned char , int));`
51			`extern void *eth_get_tx_buf (void);`
52			`extern void eth_send (void *buf, unsigned long len);`
53			`extern unsigned long eth_rx (void);`
54			`extern void eth_halt(void);`
55			`extern void init_rx_bd_pool(void);`
56			`extern void init_tx_bd_pool(void);`
57	140	julius	`extern void eth_int_enable(void);`
58			`extern void eth_toggle_traffic_mon(void);`
59	2	marcus.erl
60			`/* Tx BD */`
61			`#define ETH_TX_BD_READY 0x8000 /* Tx BD Ready */`
62			`#define ETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */`
63			`#define ETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */`
64			`#define ETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */`
65			`#define ETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */`
66
67			`#define ETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */`
68			`#define ETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */`
69			`#define ETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */`
70			`#define ETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */`
71			`#define ETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */`
72			`#define ETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */`
73			`#define ETH_TX_BD_STATS (ETH_TX_BD_UNDERRUN \| \`
74			`ETH_TX_BD_RETRY \| \`
75			`ETH_TX_BD_RETLIM \| \`
76			`ETH_TX_BD_LATECOL \| \`
77			`ETH_TX_BD_DEFER \| \`
78			`ETH_TX_BD_CARRIER)`
79
80			`/* Rx BD */`
81			`#define ETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */`
82			`#define ETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */`
83			`#define ETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */`
84
85			`#define ETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */`
86			`#define ETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */`
87			`#define ETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */`
88			`#define ETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */`
89			`#define ETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */`
90			`#define ETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */`
91			`#define ETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */`
92			`#define ETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */`
93			`#define ETH_RX_BD_STATS (ETH_RX_BD_MISS \| \`
94			`ETH_RX_BD_OVERRUN \| \`
95			`ETH_RX_BD_INVSIMB \| \`
96			`ETH_RX_BD_DRIBBLE \| \`
97			`ETH_RX_BD_TOOLONG \| \`
98			`ETH_RX_BD_SHORT \| \`
99			`ETH_RX_BD_CRCERR \| \`
100			`ETH_RX_BD_LATECOL)`
101
102			`/* Register space */`
103			`#define ETH_MODER 0x00 /* Mode Register */`
104			`#define ETH_INT 0x04 /* Interrupt Source Register */`
105			`#define ETH_INT_MASK 0x08 /* Interrupt Mask Register */`
106			`#define ETH_IPGT 0x0C /* Back to Bak Inter Packet Gap Register */`
107			`#define ETH_IPGR1 0x10 /* Non Back to Back Inter Packet Gap Register 1 */`
108			`#define ETH_IPGR2 0x14 /* Non Back to Back Inter Packet Gap Register 2 */`
109			`#define ETH_PACKETLEN 0x18 /* Packet Length Register (min. and max.) */`
110			`#define ETH_COLLCONF 0x1C /* Collision and Retry Configuration Register */`
111			`#define ETH_TX_BD_NUM 0x20 /* Transmit Buffer Descriptor Number Register */`
112			`#define ETH_CTRLMODER 0x24 /* Control Module Mode Register */`
113			`#define ETH_MIIMODER 0x28 /* MII Mode Register */`
114			`#define ETH_MIICOMMAND 0x2C /* MII Command Register */`
115			`#define ETH_MIIADDRESS 0x30 /* MII Address Register */`
116			`#define ETH_MIITX_DATA 0x34 /* MII Transmit Data Register */`
117			`#define ETH_MIIRX_DATA 0x38 /* MII Receive Data Register */`
118			`#define ETH_MIISTATUS 0x3C /* MII Status Register */`
119			`#define ETH_MAC_ADDR0 0x40 /* MAC Individual Address Register 0 */`
120			`#define ETH_MAC_ADDR1 0x44 /* MAC Individual Address Register 1 */`
121			`#define ETH_HASH_ADDR0 0x48 /* Hash Register 0 */`
122			`#define ETH_HASH_ADDR1 0x4C /* Hash Register 1 */`
123
124			`/* MODER Register */`
125			`#define ETH_MODER_RXEN 0x00000001 /* Receive Enable */`
126			`#define ETH_MODER_TXEN 0x00000002 /* Transmit Enable */`
127			`#define ETH_MODER_NOPRE 0x00000004 /* No Preamble */`
128			`#define ETH_MODER_BRO 0x00000008 /* Reject Broadcast */`
129			`#define ETH_MODER_IAM 0x00000010 /* Use Individual Hash */`
130			`#define ETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */`
131			`#define ETH_MODER_IFG 0x00000040 /* Min. IFG not required */`
132			`#define ETH_MODER_LOOPBCK 0x00000080 /* Loop Back */`
133			`#define ETH_MODER_NOBCKOF 0x00000100 /* No Backoff */`
134			`#define ETH_MODER_EXDFREN 0x00000200 /* Excess Defer */`
135			`#define ETH_MODER_FULLD 0x00000400 /* Full Duplex */`
136			`#define ETH_MODER_RST 0x00000800 /* Reset MAC */`
137			`#define ETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */`
138			`#define ETH_MODER_CRCEN 0x00002000 /* CRC Enable */`
139			`#define ETH_MODER_HUGEN 0x00004000 /* Huge Enable */`
140			`#define ETH_MODER_PAD 0x00008000 /* Pad Enable */`
141			`#define ETH_MODER_RECSMALL 0x00010000 /* Receive Small */`
142
143			`/* Interrupt Source Register */`
144			`#define ETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */`
145			`#define ETH_INT_TXE 0x00000002 /* Transmit Error IRQ */`
146			`#define ETH_INT_RXF 0x00000004 /* Receive Frame IRQ */`
147			`#define ETH_INT_RXE 0x00000008 /* Receive Error IRQ */`
148			`#define ETH_INT_BUSY 0x00000010 /* Busy IRQ */`
149			`#define ETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */`
150			`#define ETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */`
151
152			`/* Interrupt Mask Register */`
153			`#define ETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */`
154			`#define ETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */`
155			`#define ETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */`
156			`#define ETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */`
157			`#define ETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */`
158			`#define ETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */`
159			`#define ETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */`
160
161			`/* Control Module Mode Register */`
162			`#define ETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */`
163			`#define ETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */`
164			`#define ETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */`
165
166			`/* MII Mode Register */`
167			`#define ETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */`
168			`#define ETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */`
169			`#define ETH_MIIMODER_RST 0x00000200 /* MIIM Reset */`
170
171			`/* MII Command Register */`
172			`#define ETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */`
173			`#define ETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */`
174			`#define ETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */`
175
176			`/* MII Address Register */`
177			`#define ETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */`
178			`#define ETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */`
179
180			`/* MII Status Register */`
181			`#define ETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */`
182			`#define ETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */`
183			`#define ETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */`
184

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[/] [openrisc/] [trunk/] [bootloaders/] [orpmon/] [include/] [eth.h] - Blame information for rev 271